 Aditi Sinha
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2498ff07ea
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Merge branch 'dev' into bisr
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2020-05-02 07:48:35 +00:00 |
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 Joey Kunzler
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0bae652be9
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fix merge conflicts
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2020-04-23 11:51:46 -07:00 |
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Joey Kunzler
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fed1c0bbe1
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s8 col mux array
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2020-04-22 16:22:34 -07:00 |
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 mrg
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32576fb62c
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Convert wordline driver to pand2 rather than pnand2+pdriver
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2020-04-22 13:27:50 -07:00 |
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mrg
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8e243f1b3c
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Merge branch 'dev' into tech_migration
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2020-04-22 11:34:14 -07:00 |
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Matt Guthaus
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fb17abb16c
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-04-22 10:40:27 -07:00 |
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Matt Guthaus
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14f440df73
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Update golden results with new lib syntax
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2020-04-22 10:40:04 -07:00 |
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mrg
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4d6d6af0a1
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Merge remote-tracking branch 'public/dev' into dev
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2020-04-22 09:28:25 -07:00 |
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 David Ratchkov
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c2419af2e2
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Fix voltage_map names (these do not need to match pg_pin names)
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2020-04-22 09:03:22 -07:00 |
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Joey Kunzler
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60ba2c1aa5
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updated pbitcell test names
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2020-04-21 17:20:29 -07:00 |
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mrg
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0bb4a7f93d
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Merge branch 'dev' into tech_migration
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2020-04-21 16:37:36 -07:00 |
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mrg
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f1c1adc9bd
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Simplify supply contacts in delay chain.
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2020-04-21 16:12:54 -07:00 |
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Joey Kunzler
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3d4a40b338
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freepdk45 col_mux fix
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2020-04-21 15:38:19 -07:00 |
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mrg
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0f6998a1c5
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PEP8 cleanup
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2020-04-21 15:36:38 -07:00 |
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mrg
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fc85dfe29f
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Add boundary to all pgates
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2020-04-21 15:21:57 -07:00 |
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mrg
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cd66ddb37c
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Add supply rails to dff array. PEP8 cleanup.
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2020-04-21 15:21:29 -07:00 |
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mrg
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5f76514cf0
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Remove end of line whitespace
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2020-04-21 15:20:51 -07:00 |
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mrg
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ab91d0ab1d
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Add purpose to string output
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2020-04-21 15:20:30 -07:00 |
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Joey Kunzler
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ee1de9ac8c
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Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update
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2020-04-20 22:14:09 -07:00 |
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Joey Kunzler
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829f3e03fa
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col_mux.py update with correct contacts
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2020-04-20 22:08:29 -07:00 |
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Joey Kunzler
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63bea67fb5
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col_mux.py changes
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2020-04-20 20:22:46 -07:00 |
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mrg
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f6135f3471
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PEP8 formatting
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2020-04-20 16:38:30 -07:00 |
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mrg
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90fdaf902c
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Merge branch 'tech_migration' into dev
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2020-04-20 16:28:16 -07:00 |
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mrg
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dfbf6fe45c
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Default is to use preferred layer directions
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2020-04-20 15:33:53 -07:00 |
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mrg
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8c177f9947
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Split col mux test
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2020-04-20 15:03:32 -07:00 |
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mrg
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7995451cbb
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PEP8 formatting
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2020-04-20 14:45:18 -07:00 |
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mrg
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69d0e5e372
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Split port data test into single and multi-port.
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2020-04-20 14:26:44 -07:00 |
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mrg
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7f65176908
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Configured bitline directions into prot_data
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2020-04-20 14:23:40 -07:00 |
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mrg
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2a9dde5401
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Merge branch 'tech_migration' into dev
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2020-04-20 09:07:36 -07:00 |
|
 jcirimel
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32317ce3a5
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-04-18 14:23:31 -07:00 |
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jcirimel
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f590ecf83c
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fix minimum pinv sizing
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2020-04-18 05:51:21 -07:00 |
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jcirimel
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add9ec7b28
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remove excess newlines
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2020-04-18 05:42:23 -07:00 |
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jcirimel
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85bc801689
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fix pinv drc bug
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2020-04-18 05:34:55 -07:00 |
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jcirimel
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1f094b03bc
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use more optimal discrete pinv sizing
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2020-04-18 05:26:39 -07:00 |
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David Ratchkov
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5aea45ed69
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- Fix switched disabled powers
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2020-04-17 16:23:06 -07:00 |
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David Ratchkov
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123cc371be
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- Fix disabled power char
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2020-04-17 16:09:58 -07:00 |
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jcirimel
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486819ae0d
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fix width bin typo
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2020-04-17 15:27:36 -07:00 |
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David Ratchkov
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1f816e2823
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- Characterize actual disabled power (read mode only)
- Report rise/fall power individually
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2020-04-17 14:55:17 -07:00 |
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jcirimel
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a158ad1e81
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add missing import
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2020-04-17 14:24:52 -07:00 |
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mrg
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cbb67ad483
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Update to run LVS when no DRC errors too.
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2020-04-17 13:57:52 -07:00 |
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David Ratchkov
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7e36cd4828
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- Write voltage_map and pg_pin
- Remove 'when' condition on leakage power
- Remove 'clk*' from 'when' condition on internal_power on the same 'clk*' pin
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2020-04-17 13:45:57 -07:00 |
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Joey Kunzler
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7920b0cef9
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m3 min area rounding fix
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2020-04-17 12:36:48 -07:00 |
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Joey Kunzler
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fbc6dfdaac
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split pbitcell tests
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2020-04-17 12:26:18 -07:00 |
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mrg
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f1925420cf
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Only allow DRC fail with LVS pass if using Magic.
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2020-04-17 10:30:26 -07:00 |
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mrg
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75fce9894c
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Allow LVS to run even if DRC fails.
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2020-04-17 09:35:07 -07:00 |
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jcirimel
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9316fb8b01
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Merge branch 'dev' into discrete_models
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2020-04-16 16:48:21 -07:00 |
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jcirimel
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ed54c7ab83
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-04-16 16:48:07 -07:00 |
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mrg
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8ece411954
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Merge branch 'dev' into tech_migration
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2020-04-16 11:32:02 -07:00 |
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mrg
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843e9414df
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Parameterize vdd and gnd pin in write driver array.
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2020-04-16 11:28:35 -07:00 |
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mrg
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770533e7b1
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Parameterize vdd and gnd pin in sense amp array.
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2020-04-16 11:27:26 -07:00 |
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