 Bugra Onal
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22c01d7f27
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Multibank file generation (messy)
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2022-06-14 17:57:04 -07:00 |
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Bugra Onal
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3dd65b1a01
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modified template engine & sram multibank class
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2022-06-09 21:40:19 -07:00 |
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Bugra Onal
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e774cbdf9e
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Template section clone method
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2022-03-09 08:59:20 -08:00 |
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Bugra Onal
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804e5a58c5
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Template section clone method
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2022-03-09 08:58:29 -08:00 |
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Bugra Onal
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b1585355e1
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TEmplate rework
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2022-03-03 11:48:29 -08:00 |
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Bugra Onal
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f971a83e68
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Base-verilog
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2022-02-23 10:34:48 -08:00 |
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Bugra Onal
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9c35add8d6
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Base template additions
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2022-02-16 10:53:18 -08:00 |
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Bugra Onal
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6dc42a7bbb
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Verilog Template additions
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2022-02-07 11:23:43 -08:00 |
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Bugra Onal
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4d38e7df3c
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Base verilog template init
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2022-02-02 12:24:44 -08:00 |
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Bugra Onal
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07f84cb69f
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Template module done
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2022-01-26 10:52:10 -08:00 |
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Bugra Onal
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f895937f02
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Bank select
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2022-01-26 07:47:37 -08:00 |
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Bugra Onal
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500a872c10
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Templatable verilog file
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2022-01-12 11:59:44 -08:00 |
|
 mrg
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d8d8636d0f
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Comment out calibre in freepdk45
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2021-11-22 15:54:22 -08:00 |
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mrg
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66c9501621
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Remove klayout from scmos
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2021-11-22 11:33:27 -08:00 |
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mrg
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fc0516460d
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Use klayout in SCMOS too.
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2021-11-22 11:33:27 -08:00 |
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mrg
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32c7e90662
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Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
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2021-11-22 11:33:27 -08:00 |
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mrg
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48e35588f4
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Fix cheat on wordline driver name.
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2021-11-22 11:33:27 -08:00 |
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mrg
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bfb33ecbb4
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Add DRC rules and display files
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2021-11-22 11:33:27 -08:00 |
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mrg
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779d6ad2b2
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Debugging klayout for SCMOS and FreePDK45.
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2021-11-22 11:33:27 -08:00 |
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mrg
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0c3ee643ab
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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mrg
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b94dd79125
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Add labels to noconn in dummy bitcell for klayout lvs
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2021-11-22 11:33:27 -08:00 |
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mrg
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735f9cf450
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Remove klayout from scmos
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2021-11-22 11:33:27 -08:00 |
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mrg
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552811b41b
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Use klayout in SCMOS too.
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2021-11-22 11:33:27 -08:00 |
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mrg
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b7362ba011
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Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
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2021-11-22 11:33:27 -08:00 |
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mrg
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43bbd2e722
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Fixed incorrect via2 spacing rule in tech file.
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2021-11-22 11:33:27 -08:00 |
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mrg
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8f296810be
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Fix cheat on wordline driver name.
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2021-11-22 11:33:27 -08:00 |
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mrg
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6ee4697711
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Change cell names in lvs file
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2021-11-22 11:33:27 -08:00 |
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mrg
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5d33db0ee4
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Add write driver to well connect list
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2021-11-22 11:33:27 -08:00 |
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mrg
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5dc885a674
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Update nwell spacing to be same potential
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2021-11-22 11:33:27 -08:00 |
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mrg
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2e846cb22f
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Fix regexes for cells without well taps
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2021-11-22 11:33:27 -08:00 |
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mrg
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acc9b2d223
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Connect pwell and bulk when no tap
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2021-11-22 11:33:27 -08:00 |
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mrg
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141b42dc0e
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Add DRC rules and display files
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2021-11-22 11:33:27 -08:00 |
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mrg
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7d7ffe76e0
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Debugging klayout for SCMOS and FreePDK45.
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2021-11-22 11:33:27 -08:00 |
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mrg
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c2e258709b
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Merge branch 'lvs' into dev
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2021-11-22 11:33:12 -08:00 |
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mrg
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ce40f2ae28
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Allow non-unique matching for replica bitcell test.
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2021-11-19 09:42:06 -08:00 |
|
 Jesse Cirimelli-Low
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2fb08af684
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change col mux array poly routing from straight to 'L'
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2021-11-17 17:22:03 -08:00 |
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Bugra Onal
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c8139cf145
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Added OpenPDKS repo to makefile
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2021-10-28 18:43:28 +03:00 |
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mrg
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e6a009312e
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Move mem reg before usage for compatibility
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2021-10-13 09:46:02 -07:00 |
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mrg
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ccab2f8064
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Add CNAME for github pages
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2021-10-08 09:11:43 -07:00 |
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Jesse Cirimelli-Low
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5792256db1
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route spare col
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2021-10-05 15:28:20 -07:00 |
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mrg
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911f479ecb
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Modify Makefile to pull from git repo
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2021-10-04 16:00:37 -07:00 |
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mrg
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fa2232fc11
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Initial commit of sky130 config files
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2021-10-04 15:16:28 -07:00 |
|
 samuelkcrow
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dfbf0ba6e1
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Make git dependency visible and enforce it.
resolves #87
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2021-10-04 14:43:14 -07:00 |
|
 Hunter Nichols
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39ae1270d7
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Merge branch 'dev' into cacti_model
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2021-09-20 17:01:50 -07:00 |
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Hunter Nichols
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bd57a043d7
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Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation.
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2021-09-20 16:51:02 -07:00 |
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Hunter Nichols
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116f102ebf
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Fixed units in LIB files when cacti is selected as the model. Changed model data gather to only use the extended config.
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2021-09-20 16:35:16 -07:00 |
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mrg
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fe077e79d5
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Use local temp DRC/LVS rules file for running.
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2021-09-20 11:06:27 -07:00 |
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mrg
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f2882782e7
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Use calibre by default until klayout LVS is clean.
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2021-09-20 11:05:49 -07:00 |
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mrg
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be92282150
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Prefer open source over commercial
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2021-09-20 11:02:40 -07:00 |
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mrg
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10753a0802
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Change via2 to 65nm to be compatible with Calibre FreePDK45 deck
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2021-09-16 15:42:02 -07:00 |
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