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OpenRAM
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3,736 Commits 4 Branches 63 Tags 78 MiB
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3736 Commits

Author SHA1 Message Date
Bugra Onal 22c01d7f27 Multibank file generation (messy) 2022-06-14 17:57:04 -07:00
Bugra Onal 3dd65b1a01 modified template engine & sram multibank class 2022-06-09 21:40:19 -07:00
Bugra Onal e774cbdf9e Template section clone method 2022-03-09 08:59:20 -08:00
Bugra Onal 804e5a58c5 Template section clone method 2022-03-09 08:58:29 -08:00
Bugra Onal b1585355e1 TEmplate rework 2022-03-03 11:48:29 -08:00
Bugra Onal f971a83e68 Base-verilog 2022-02-23 10:34:48 -08:00
Bugra Onal 9c35add8d6 Base template additions 2022-02-16 10:53:18 -08:00
Bugra Onal 6dc42a7bbb Verilog Template additions 2022-02-07 11:23:43 -08:00
Bugra Onal 4d38e7df3c Base verilog template init 2022-02-02 12:24:44 -08:00
Bugra Onal 07f84cb69f Template module done 2022-01-26 10:52:10 -08:00
Bugra Onal f895937f02 Bank select 2022-01-26 07:47:37 -08:00
Bugra Onal 500a872c10 Templatable verilog file 2022-01-12 11:59:44 -08:00
mrg d8d8636d0f Comment out calibre in freepdk45 2021-11-22 15:54:22 -08:00
mrg 66c9501621 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg fc0516460d Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg 32c7e90662 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 48e35588f4 Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg bfb33ecbb4 Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 779d6ad2b2 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg b94dd79125 Add labels to noconn in dummy bitcell for klayout lvs 2021-11-22 11:33:27 -08:00
mrg 735f9cf450 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg 552811b41b Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 43bbd2e722 Fixed incorrect via2 spacing rule in tech file. 2021-11-22 11:33:27 -08:00
mrg 8f296810be Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg 6ee4697711 Change cell names in lvs file 2021-11-22 11:33:27 -08:00
mrg 5d33db0ee4 Add write driver to well connect list 2021-11-22 11:33:27 -08:00
mrg 5dc885a674 Update nwell spacing to be same potential 2021-11-22 11:33:27 -08:00
mrg 2e846cb22f Fix regexes for cells without well taps 2021-11-22 11:33:27 -08:00
mrg acc9b2d223 Connect pwell and bulk when no tap 2021-11-22 11:33:27 -08:00
mrg 141b42dc0e Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg c2e258709b Merge branch 'lvs' into dev 2021-11-22 11:33:12 -08:00
mrg ce40f2ae28 Allow non-unique matching for replica bitcell test. 2021-11-19 09:42:06 -08:00
Jesse Cirimelli-Low 2fb08af684 change col mux array poly routing from straight to 'L' 2021-11-17 17:22:03 -08:00
Bugra Onal c8139cf145 Added OpenPDKS repo to makefile 2021-10-28 18:43:28 +03:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
mrg ccab2f8064 Add CNAME for github pages 2021-10-08 09:11:43 -07:00
Jesse Cirimelli-Low 5792256db1 route spare col 2021-10-05 15:28:20 -07:00
mrg 911f479ecb Modify Makefile to pull from git repo 2021-10-04 16:00:37 -07:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
samuelkcrow dfbf0ba6e1 Make git dependency visible and enforce it. 
resolves #87
 2021-10-04 14:43:14 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
Hunter Nichols 116f102ebf Fixed units in LIB files when cacti is selected as the model. Changed model data gather to only use the extended config. 2021-09-20 16:35:16 -07:00
mrg fe077e79d5 Use local temp DRC/LVS rules file for running. 2021-09-20 11:06:27 -07:00
mrg f2882782e7 Use calibre by default until klayout LVS is clean. 2021-09-20 11:05:49 -07:00
mrg be92282150 Prefer open source over commercial 2021-09-20 11:02:40 -07:00
mrg 10753a0802 Change via2 to 65nm to be compatible with Calibre FreePDK45 deck 2021-09-16 15:42:02 -07:00