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3,717 Commits 4 Branches 63 Tags 78 MiB
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163 Commits

Author SHA1 Message Date
mrg 735f9cf450 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg 552811b41b Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 6ee4697711 Change cell names in lvs file 2021-11-22 11:33:27 -08:00
mrg 5d33db0ee4 Add write driver to well connect list 2021-11-22 11:33:27 -08:00
mrg 5dc885a674 Update nwell spacing to be same potential 2021-11-22 11:33:27 -08:00
mrg 2e846cb22f Fix regexes for cells without well taps 2021-11-22 11:33:27 -08:00
mrg acc9b2d223 Connect pwell and bulk when no tap 2021-11-22 11:33:27 -08:00
mrg 141b42dc0e Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols a312639ef8 Added tech params for on-resistance and load capacitances 2021-07-21 11:00:32 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
mrg 9720e5af29 Remove default array row/col multiple 2021-06-29 11:28:19 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 8ee6d3be6c Added more data for regression modules. 2021-06-21 17:21:00 -07:00
Jesse Cirimelli-Low 8346ad736e add dimension contraints to other tech files 2021-06-18 14:36:15 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols a73bfe6c2c Added more configs for model and data from scn4m_subm run. 2021-06-09 10:35:58 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 4b1c359089 update copyright year. 2021-01-22 11:24:53 -08:00
Hunter Nichols c8e631108a Updated sim_data for scmos 2021-01-22 00:51:14 -08:00
Hunter Nichols 59200d1048 Added updated data for scmos, removed unused files. 2021-01-13 13:09:21 -08:00
Hunter Nichols d6177b34f0 Added data which includes corner as an input feature 2020-12-17 12:59:06 -08:00
Hunter Nichols f1f6a1a520 Removed windows end of line characters. 2020-12-15 12:08:31 -08:00
Hunter Nichols 06232dee8f Added leakage and slew data. Added temporary fix to model output format. 2020-12-14 14:32:10 -08:00
Hunter Nichols 25544c3974 Added similar interface to linear regression as elmore 2020-12-14 13:59:31 -08:00
Hunter Nichols b1a7e0e55b Added power data 2020-12-09 15:21:22 -08:00
Hunter Nichols 1143dbec94 Added initial scripts and data to generate analytical model 2020-11-20 12:40:04 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg a2f29e5edd Fix missing nand4_leakage #97 2020-11-12 09:48:08 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 423e2c165f Remove test cell in scn4m_subm tech.py 2020-11-03 16:38:55 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00