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OpenRAM
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2512 Commits

Author SHA1 Message Date
Michael Timothy Grimes bf7d846e5f Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-28 04:29:38 -08:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Matt Guthaus 01244347c1 Add git attribute file to ignore spice files in determining language. 2018-02-26 17:27:04 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Matt Guthaus 20dfb81359 Update contribution guidelines. 2018-02-26 15:03:03 -08:00
Matt Guthaus 35137d1c67 Add extra comments in stimulus output. 2018-02-26 14:39:06 -08:00
mguthaus 45295b5cfa Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-26 09:04:01 -08:00
mguthaus 0175870628 Forgot to add directories for tracking of IP files. 2018-02-26 09:03:53 -08:00
Matt Guthaus a732405836 Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
mguthaus cc99025279 Add log files for IP memories. 2018-02-25 11:25:20 -08:00
mguthaus f7a3fb90f0 Add SCMOS IP files. 2018-02-25 11:20:50 -08:00
mguthaus 44d85ecb94 First set of IP library components. Some DRC/LVS errors exist. Some timing characterization errors exist. Logs included with errors. 2018-02-25 11:16:01 -08:00
mguthaus 4a3a0c2c03 Keep Making if encounter errors. 2018-02-25 11:15:28 -08:00
mguthaus 90be96cfe5 Don't ignore log files. 2018-02-25 11:14:53 -08:00
mguthaus 7a14cf16e0 Change priority of debug info for DRC/LVS. 2018-02-25 11:14:31 -08:00
mguthaus 322f354878 Convert period to float to avoid type mismatch. 2018-02-25 11:13:43 -08:00
mguthaus 132c91d68f Adjust makefiles to continue on error. Turned on DRC/LVS to check for errors. 2018-02-23 15:46:13 -08:00
mguthaus a164a14b3f Add a bunch of config files 2018-02-23 15:27:18 -08:00
mguthaus f3efb5fb50 Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
Matt Guthaus d88ff01792 Change default operating conditions to OC 2018-02-23 13:38:55 -08:00
Matt Guthaus 29aa6002e6 Make period into p instead of remove it. Changes file names... 2018-02-23 12:50:02 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Matt Guthaus 107752b1fb Fix num words in example. 2018-02-23 12:17:43 -08:00
Matt Guthaus e51c4e8028 Increase verbosity in lib tests. 2018-02-23 07:48:12 -08:00
Matt Guthaus e3e7a31c6b Fix syntax error in functional test. 2018-02-23 07:47:01 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Matt Guthaus cf4e8ce880 Add -j 2 for top level Makefile. 2018-02-22 11:15:47 -08:00
Matt Guthaus 23f06bfa9a Reduce number of parameters in function calls for delay.py. 2018-02-22 11:14:58 -08:00
Matt Guthaus 4dc1f57881 Makefiles don't run DRC/LVS for now. 2018-02-22 11:14:36 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
Matt Guthaus b31f3c18af Change BSIM3 models to version 3.3.0. Add comment about multithreading selection. 2018-02-21 17:50:12 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
Matt Guthaus cf5f1e94b9 Update hspice results 2018-02-21 16:12:20 -08:00
Matt Guthaus 4e414b6c15 Fix unintended unmerge of changes. Bad bad. 2018-02-21 16:03:49 -08:00
Matt Guthaus a44346110b Fix merge of results. 2018-02-21 15:47:07 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Matt Guthaus ea772b36d9 Unthread makefiles by default. Option to not DRC/LVS check lib for now. 2018-02-21 15:19:19 -08:00
Matt Guthaus 4b9ea66a42 Change names of variables to indicate transistions for clarity. 2018-02-21 15:13:46 -08:00
Matt Guthaus 71831e7737 Get delays only for successful run. 2018-02-21 14:05:39 -08:00
Matt Guthaus 9600dae7df Remove print statements. 2018-02-21 13:45:14 -08:00
Matt Guthaus 7d2f4386e2 Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit. 2018-02-21 13:38:43 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
Michael Timothy Grimes 4ea2a70a1b removing unnecessary unit test for pbitcell 2018-02-19 10:58:08 -08:00
mguthaus 0aba4ee483 Add library README file. 2018-02-16 15:31:36 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus c1c1ba38a3 Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00