mirror of https://github.com/VLSIDA/OpenRAM.git
Makefiles don't run DRC/LVS for now.
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4dc1f57881
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@ -1,7 +1,7 @@
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CUR_DIR = $(shell pwd)
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TEST_DIR = ${CUR_DIR}/tests
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MAKEFLAGS += -j 2
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#MAKEFLAGS += -j 2
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CONFIG_DIR = configs
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OUT_DIRS = sp lib lef gds verilog
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@ -14,7 +14,7 @@ all : $(SPICES)
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# Characterize and perform DRC/LVS
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OPTS = -c
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# Do not characterize or perform DRC/LVS
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#OPTS = -n
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OPTS += -n
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%.sp : %.py
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$(eval bname=$(basename $(notdir $<)))
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openram.py $(OPTS) $< 2>&1 > $(bname).log
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@ -1,7 +1,7 @@
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CUR_DIR = $(shell pwd)
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TEST_DIR = ${CUR_DIR}/tests
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MAKEFLAGS += -j 2
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#MAKEFLAGS += -j 2
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CONFIG_DIR = configs
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OUT_DIRS = sp lib lef gds verilog
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@ -12,9 +12,9 @@ SPICES=$(SRCS:.py=.sp)
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all : $(SPICES)
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# Characterize and perform DRC/LVS
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OPTS = -c
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OPTS = -c
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# Do not characterize or perform DRC/LVS
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#OPTS = -n
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OPTS += -n
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%.sp : %.py
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$(eval bname=$(basename $(notdir $<)))
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openram.py $(OPTS) $< 2>&1 > $(bname).log
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