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Author SHA1 Message Date
Bugra Onal bac40fa630 Removed SRAM directory 2022-07-28 15:04:53 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal d36f74a514 Not mathcing whitespace bug fixed 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal 9bd3f1b45a None check syntax fix 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal e130ba736c Fixed indent error on write_size init 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bbcbddd934 Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 2b1d0bd9f7 Template module done 2022-07-28 15:03:41 -07:00
Bugra Onal 0970095415 Bank select 2022-07-28 15:03:41 -07:00
Bugra Onal 859548f19f Templatable verilog file 2022-07-28 15:03:41 -07:00
Bugra Onal f08da6acc5 Fixed globals conflict 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal a0c6a0ad03 Set write_size default to word_size 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
samuelkcrow 1c8aeaa68a fix imports 2022-07-27 11:09:10 -07:00
samuelkcrow 2ff9ea4f78 move generic functions from control_logic module to new control_logic_base module 2022-07-26 23:22:02 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
mrg 69d5731d67 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-07-22 13:47:19 -07:00
Matt Guthaus f1e452c8e3 Merge pull request #150 from erendn/fix_whitespace 
Fix whitespace
 2022-07-22 13:38:48 -07:00
samuelkcrow f01e73328d remove superfluous imports from multiport test 2022-07-22 13:12:03 -07:00
samuelkcrow b82213caff use packages for imports in modules 2022-07-22 12:56:47 -07:00
samuelkcrow 480862c765 remove sys.path.append calls from tests 2022-07-22 11:24:54 -07:00
Eren Dogan 03422be48c Fix carriage return 2022-07-22 19:54:35 +03:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Eren Dogan 2a778dca82 Add whitespace check to code format test 2022-07-22 18:22:40 +03:00
Eren Dogan 64c72ee19d Fix typo 2022-07-22 18:15:27 +03:00
Eren Dogan 449c68ccae Fix file setup in code format test 2022-07-22 18:11:14 +03:00
samuelkcrow 75efc476f7 add remaining tests 2022-07-21 19:35:02 -07:00
samuelkcrow 5fa0689c02 fix drc error in wlen_row 2022-07-21 19:35:02 -07:00
samuelkcrow 08ac1c176a connect in pin via m2 instead of m3, passes lvs now 2022-07-21 19:35:02 -07:00
samuelkcrow 12c58b0457 use spice names for delay chain output pins in layout 2022-07-21 19:35:02 -07:00
samuelkcrow 73021be8eb copy vertical bus spacing from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 2611468dd7 replace route_supply with route supplies from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 9182ad7c61 add m4 spacing for route_rails same as control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 7f52e63aca route glitch3 to inverter on wen row 2022-07-21 19:35:02 -07:00