Bugra Onal
aada5a0d09
Not mathcing whitespace bug fixed
2022-07-13 16:38:22 -07:00
Bugra Onal
e041b101a7
Fixed the bad commas with post-process regex
2022-07-13 16:37:47 -07:00
Bugra Onal
94f166e2d0
None check syntax fix
2022-07-13 16:36:14 -07:00
Bugra Onal
45d8c43376
write_size init in sram_config
2022-07-13 16:20:06 -07:00
Bugra Onal
a38826f073
Fixed indent error on write_size init
2022-07-13 16:11:45 -07:00
mrg
d92c7a634d
Use packages for imports.
...
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
Bugra Onal
78d4e2aa8b
Cleaned up tests dir after bad run
2022-07-08 17:03:53 -07:00
Bugra Onal
4028534a84
Fixed verilog filename double extension
2022-07-08 17:01:30 -07:00
Bugra Onal
289f48c3f3
Merge branch 'multibank' of github.com:VLSIDA/PrivateRAM into multibank
2022-07-08 14:23:05 -07:00
Bugra Onal
3647acda9e
Fixed globals conflict
2022-07-08 14:17:51 -07:00
Bugra Onal
a1645570a8
Replaced instances of addr_size with bank_addr
2022-07-08 13:55:02 -07:00
Bugra Onal
660226c192
Set write_size default to word_size
2022-07-08 13:54:56 -07:00
Bugra Onal
2c6d3223ea
Added conditional sections to template
2022-07-08 13:51:07 -07:00
Bugra Onal
34f28554ad
Multibank file generation (messy)
2022-07-08 13:51:07 -07:00
Bugra Onal
3b43cefdc5
modified template engine & sram multibank class
2022-07-08 13:51:07 -07:00
Bugra Onal
3805db072a
Template section clone method
2022-07-08 13:51:07 -07:00
Bugra Onal
a7db6d182e
Template section clone method
2022-07-08 13:51:07 -07:00
Bugra Onal
5bbb8eae4c
TEmplate rework
2022-07-08 13:51:07 -07:00
Bugra Onal
41d04f88f4
Base-verilog
2022-07-08 13:51:07 -07:00
Bugra Onal
4afa391a87
Base template additions
2022-07-08 13:51:07 -07:00
Bugra Onal
e6ca67e945
Verilog Template additions
2022-07-08 13:51:07 -07:00
Bugra Onal
31bf5364ee
Base verilog template init
2022-07-08 13:51:07 -07:00
Bugra Onal
16512bc4ee
Template module done
2022-07-08 13:51:07 -07:00
Bugra Onal
a69a016d9f
Bank select
2022-07-08 13:51:07 -07:00
Bugra Onal
38a035a7da
Templatable verilog file
2022-07-08 13:51:07 -07:00
mrg
58ea148d47
Add dlxtn latch for open reg file
2022-06-22 09:53:10 -07:00
mrg
f7738c60a3
Don't install SRAM macros.
2022-06-21 13:53:08 -07:00
mrg
ac86ad0e8a
Move pdk installation inside docker to use Magic from docker image.
2022-06-21 12:10:15 -07:00
Jesse Cirimelli-Low
374562f354
rbc substrate issues
2022-06-16 15:17:07 -07:00
Bugra Onal
3ebb719535
Added conditional sections to template
2022-06-16 15:12:43 -07:00
mrg
c479915c02
Update colenda with new device sizes.
2022-06-16 11:23:13 -07:00
mrg
dc9ae6cd1a
Increase column width in netgen LVS scripts
2022-06-16 10:30:58 -07:00
Jesse Cirimelli-Low
98fe4c74a4
colend fixes in progress
2022-06-15 22:34:21 -07:00
Bugra Onal
22c01d7f27
Multibank file generation (messy)
2022-06-14 17:57:04 -07:00
mrg
69bb6826dc
Remove duplicate mount target
2022-06-14 12:08:56 -07:00
mrg
956fac2cec
Add patch.
2022-06-13 14:13:35 -07:00
mrg
c07f6d195f
Update docker to magic with patch for port first/next.
2022-06-13 14:13:20 -07:00
mrg
f0f2c26e8d
Add both sp and dp tiny test macro.
2022-06-13 14:13:05 -07:00
mrg
cf03454ecf
Don't add wdriver_sel_n pins which aren't used.
2022-06-10 09:18:40 -07:00
Bugra Onal
3dd65b1a01
modified template engine & sram multibank class
2022-06-09 21:40:19 -07:00
mrg
e744ffd6ea
Move mount to shared target in openram.mk
2022-06-09 06:44:23 -07:00
mrg
ef7120c5cd
Change pdk path in root directory mount command.
2022-06-09 06:38:33 -07:00
mrg
d30f05a1ae
Update power layer on li for sky130
2022-06-08 17:19:26 -07:00
mrg
9e3a28237f
Update port data test for sky130 single port
2022-06-08 17:18:53 -07:00
mrg
00ca2d45b6
Extract unique is option not command.
2022-06-08 15:06:06 -07:00
mrg
4814cf6eac
Merge branch 'sky130_fixes' into dev
2022-06-08 14:27:30 -07:00
mrg
280582d4d6
Add missing via in dff array
2022-06-08 14:24:17 -07:00
mrg
76bc4e1fc2
Only do one extract. Flatten transistors since bug fixed in magic.
2022-06-08 14:23:50 -07:00
mrg
910bcf9df3
Update magic to 8.3.310
2022-06-08 14:23:28 -07:00
mrg
ad6633ddca
Update versions of tools. Fix supply bug in predecode.
2022-06-08 13:50:25 -07:00
Bugra Onal
mrg
Jesse Cirimelli-Low