Convert bitcells to 1port and 2port

technology/freepdk45/sp_lib/cell_1rw_1r.sp

@@ -1,14 +0,0 @@
-
-.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
-MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
-MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
-.ENDS
-

technology/freepdk45/sp_lib/cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1

technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp

@@ -1,14 +0,0 @@
-
-.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
-MM9 RA_to_R_right wl1 br1_noconn gnd NMOS_VTG W=180.0n L=50n m=1
-MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM6 RA_to_R_left wl1 bl1_noconn gnd NMOS_VTG W=180.0n L=50n m=1
-MM5 Q wl0 bl0_noconn gnd NMOS_VTG W=135.00n L=50n m=1
-MM4 Q_bar wl0 br0_noconn gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
-MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
-.ENDS
-

technology/freepdk45/sp_lib/dummy_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT dummy_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT dummy_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1_noconn gnd NMOS_VTG W=180.0n L=50n m=1
 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1

technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp

@@ -1,14 +0,0 @@
-
-.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
-MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
-MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
-MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
-MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
-MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
-.ENDS
-

technology/freepdk45/sp_lib/replica_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT replica_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
 MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1

technology/freepdk45/tech/tech.py

@@ -35,6 +35,13 @@ cell_properties.bitcell.mirror.x = True
 cell_properties.bitcell.mirror.y = False
 cell_properties.bitcell_power_pin_directions = ("V", "V")
 
+cell_properties.names["bitcell_1port"] = "cell_6t"
+cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t"
+cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t"
+cell_properties.names["bitcell_2port"] = "cell_2rw"
+cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
+cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw"
+
 ###################################################
 # Custom cell properties
 ###################################################

technology/scn4m_subm/sp_lib/cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
 MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
 MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u

technology/scn4m_subm/sp_lib/dummy_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT dummy_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1_noconn gnd n w=1.2u l=0.4u
 MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
 MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u

technology/scn4m_subm/sp_lib/replica_cell_2rw.sp

@@ -1,5 +1,5 @@
 
-.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
+.SUBCKT replica_cell_2rw bl0 br0 bl1 br1 wl0 wl1 vdd gnd
 MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
 MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
 MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u

technology/scn4m_subm/tech/tech.py

@@ -33,6 +33,13 @@ cell_properties = cell_properties()
 cell_properties.bitcell.mirror.x = True
 cell_properties.bitcell.mirror.y = False
 
+cell_properties.names["bitcell_1port"] = "cell_6t"
+cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t"
+cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t"
+cell_properties.names["bitcell_2port"] = "cell_2rw"
+cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
+cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw"
+
 ###################################################
 # Custom cell properties
 ###################################################