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fix merge conflicts
This commit is contained in:
jcirimel
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+228
-143
@@ -7,12 +7,37 @@
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#
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import os
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from design_rules import *
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from module_type import *
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from custom_cell_properties import cell_properties
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"""
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File containing the process technology parameters for FreePDK 45nm.
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"""
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#GDS file info
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###################################################
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# Custom modules
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###################################################
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# This uses the default classes to instantiate module from
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# '$OPENRAM_HOME/compiler/modules'.
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# Using tech_modules['cellname'] you can override each class by providing a custom
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# implementation in '$OPENRAM_TECHDIR/modules/'
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# For example: tech_modules['contact'] = 'contact_freepdk45'
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tech_modules = module_type()
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###################################################
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# Custom cell properties
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###################################################
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cell_properties = cell_properties()
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cell_properties.bitcell.mirror.x = True
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cell_properties.bitcell.mirror.y = False
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cell_properties.bitcell_power_pin_directions = ("V", "V")
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###################################################
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# GDS file info
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###################################################
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GDS = {}
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# gds units
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# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
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@@ -29,52 +54,86 @@ GDS["unit"] = (0.0005,1e-9)
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GDS["zoom"] = 0.05
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###################################################
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##GDS Layer Map
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# Interconnect stacks
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###################################################
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poly_stack = ("poly", "contact", "m1")
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active_stack = ("active", "contact", "m1")
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m1_stack = ("m1", "via1", "m2")
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m2_stack = ("m2", "via2", "m3")
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m3_stack = ("m3", "via3", "m4")
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layer_indices = {"poly": 0,
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"active": 0,
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"m1": 1,
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"m2": 2,
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"m3": 3,
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"m4": 4}
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# The FEOL stacks get us up to m1
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feol_stacks = [poly_stack,
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active_stack]
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# The BEOL stacks are m1 and up
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beol_stacks = [m1_stack,
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m2_stack,
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m3_stack]
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layer_stacks = feol_stacks + beol_stacks
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preferred_directions = {"poly": "V",
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"active": "V",
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"m1": "H",
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"m2": "V",
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"m3": "H",
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"m4": "V"}
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###################################################
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# Power grid
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###################################################
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# Use M3/M4
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power_grid = m3_stack
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###################################################
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# GDS Layer Map
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###################################################
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# create the GDS layer map
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# FIXME: parse the gds layer map from the cadence map?
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layer = {}
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layer["active"] = 1
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layer["pwell"] = 2
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layer["nwell"] = 3
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layer["nimplant"]= 4
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layer["pimplant"]= 5
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layer["vtg"] = 6
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layer["vth"] = 7
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layer["thkox"] = 8
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layer["poly"] = 9
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layer["contact"] = 10
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layer["active_contact"] = 10
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layer["metal1"] = 11
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layer["via1"] = 12
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layer["metal2"] = 13
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layer["via2"] = 14
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layer["metal3"] = 15
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layer["via3"] = 16
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layer["metal4"] = 17
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layer["via4"] = 18
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layer["metal5"] = 19
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layer["via5"] = 20
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layer["metal6"] = 21
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layer["via6"] = 22
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layer["metal7"] = 23
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layer["via7"] = 24
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layer["metal8"] = 25
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layer["via8"] = 26
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layer["metal9"] = 27
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layer["via9"] = 28
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layer["metal10"] = 29
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layer["text"] = 239
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layer["boundary"]= 239
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layer["blockage"]= 239
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layer["active"] = (1, 0)
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layer["pwell"] = (2, 0)
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layer["nwell"] = (3, 0)
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layer["nimplant"]= (4, 0)
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layer["pimplant"]= (5, 0)
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layer["vtg"] = (6, 0)
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layer["vth"] = (7, 0)
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layer["thkox"] = (8, 0)
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layer["poly"] = (9, 0)
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layer["contact"] = (10, 0)
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layer["m1"] = (11, 0)
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layer["via1"] = (12, 0)
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layer["m2"] = (13, 0)
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layer["via2"] = (14, 0)
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layer["m3"] = (15, 0)
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layer["via3"] = (16, 0)
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layer["m4"] = (17, 0)
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layer["via4"] = (18, 0)
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layer["m5"] = (19, 0)
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layer["via5"] = (20, 0)
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layer["m6"] = (21, 0)
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layer["via6"] = (22, 0)
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layer["m7"] = (23, 0)
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layer["via7"] = (24, 0)
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layer["m8"] = (25, 0)
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layer["via8"] = (26, 0)
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layer["m9"] = (27, 0)
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layer["via9"] = (28, 0)
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layer["m10"] = (29, 0)
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layer["text"] = (239, 0)
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layer["boundary"]= (239, 0)
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###################################################
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##END GDS Layer Map
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###################################################
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###################################################
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##DRC/LVS Rules Setup
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# DRC/LVS Rules Setup
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###################################################
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#technology parameter
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@@ -90,10 +149,6 @@ drclvs_home=os.environ.get("DRCLVS_HOME")
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drc = design_rules("freepdk45")
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drc["body_tie_down"] = 0
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drc["has_pwell"] = True
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drc["has_nwell"] = True
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#grid size
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drc["grid"] = 0.0025
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@@ -110,20 +165,26 @@ drc["minlength_channel"] = 0.05
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# WELL.2 Minimum spacing of nwell/pwell at different potential
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drc["pwell_to_nwell"] = 0.225
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# WELL.3 Minimum spacing of nwell/pwell at the same potential
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drc["well_to_well"] = 0.135
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# WELL.4 Minimum width of nwell/pwell
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drc["minwidth_well"] = 0.2
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drc.add_layer("nwell",
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width = 0.2,
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spacing = 0.135)
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drc.add_layer("pwell",
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width = 0.2,
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spacing = 0.135)
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# POLY.1 Minimum width of poly
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drc["minwidth_poly"] = 0.05
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# POLY.2 Minimum spacing of poly AND active
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drc["poly_to_poly"] = 0.14
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drc.add_layer("poly",
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width = 0.05,
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spacing = 0.14)
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# POLY.3 Minimum poly extension beyond active
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drc["poly_extend_active"] = 0.055
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# Not a rule
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drc["poly_to_polycontact"] = 0.075
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drc["poly_to_contact"] = 0.075
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# POLY.4 Minimum enclosure of active around gate
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drc["active_enclosure_gate"] = 0.07
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drc["active_enclose_gate"] = 0.07
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# POLY.5 Minimum spacing of field poly to active
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drc["poly_to_active"] = 0.05
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# POLY.6 Minimum Minimum spacing of field poly
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@@ -131,150 +192,169 @@ drc["poly_to_field_poly"] = 0.075
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# Not a rule
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drc["minarea_poly"] = 0.0
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# ACTIVE.2 Minimum spacing of active
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drc["active_to_body_active"] = 0.08
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# ACTIVE.1 Minimum width of active
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drc["minwidth_active"] = 0.09
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# Not a rule
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drc["active_to_active"] = 0
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# ACTIVE.2 Minimum spacing of active
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drc.add_layer("active",
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width = 0.09,
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spacing = 0.08)
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# ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active
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drc["well_enclosure_active"] = 0.055
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 0.055
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# Not a rule
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drc["minarea_active"] = 0
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drc.add_enclosure("nwell",
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layer = "active",
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enclosure = 0.055)
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drc.add_enclosure("pwell",
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layer = "active",
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enclosure = 0.055)
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# IMPLANT.1 Minimum spacing of nimplant/ pimplant to channel
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drc["implant_to_channel"] = 0.07
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# Not a rule
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drc["implant_enclosure_active"] = 0
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drc.add_enclosure("implant",
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layer = "active",
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enclosure = 0)
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# Not a rule
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drc["implant_enclosure_contact"] = 0
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drc.add_enclosure("implant",
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layer = "contact",
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enclosure = 0)
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# IMPLANT.2 Minimum spacing of nimplant/ pimplant to contact
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drc["implant_to_contact"] = 0.025
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# IMPLANT.3 Minimum width/ spacing of nimplant/ pimplant
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drc["implant_to_implant"] = 0.045
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# IMPLANT.4 Minimum width/ spacing of nimplant/ pimplant
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drc["minwidth_implant"] = 0.045
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drc.add_layer("implant",
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width = 0.045,
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spacing = 0.045)
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# CONTACT.1 Minimum width of contact
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drc["minwidth_contact"] = 0.065
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# CONTACT.2 Minimum spacing of contact
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drc["contact_to_contact"] = 0.075
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drc.add_layer("contact",
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width = 0.065,
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spacing = 0.075)
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# CONTACT.4 Minimum enclosure of active around contact
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drc["active_enclosure_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["active_extend_contact"] = 0.005
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drc.add_enclosure("active",
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layer = "contact",
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enclosure = 0.005)
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# CONTACT.6 Minimum spacing of contact and gate
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drc["active_contact_to_gate"] = 0.0375 #changed from 0.035
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# CONTACT.7 Minimum spacing of contact and poly
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drc["poly_contact_to_gate"] = 0.090
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# CONTACT.1 Minimum width of contact
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# CONTACT.2 Minimum spacing of contact
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drc.add_layer("contact",
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width = 0.065,
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spacing = 0.075)
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# CONTACT.5 Minimum enclosure of poly around contact
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drc["poly_enclosure_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.005
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drc.add_enclosure("poly",
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layer = "contact",
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enclosure = 0.005)
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# CONTACT.6 Minimum spacing of contact and gate
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drc["contact_to_gate"] = 0.0375 #changed from 0.035
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# CONTACT.7 Minimum spacing of contact and poly
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drc["contact_to_poly"] = 0.090
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# METAL1.1 Minimum width of metal1
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drc["minwidth_metal1"] = 0.065
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# METAL1.2 Minimum spacing of metal1
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drc["metal1_to_metal1"] = 0.065
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drc.add_layer("m1",
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width = 0.065,
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spacing = 0.065)
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# METAL1.3 Minimum enclosure around contact on two opposite sides
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drc["metal1_enclosure_contact"] = 0
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# Reserved for asymmetric enclosures
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drc["metal1_extend_contact"] = 0.035
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drc.add_enclosure("m1",
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layer = "contact",
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enclosure = 0,
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extension = 0.035)
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# METAL1.4 inimum enclosure around via1 on two opposite sides
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drc["metal1_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal1_enclosure_via1"] = 0
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# Not a rule
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drc["minarea_metal1"] = 0
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drc.add_enclosure("m1",
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layer = "via1",
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enclosure = 0,
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extension = 0.035)
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# VIA1.1 Minimum width of via1
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drc["minwidth_via1"] = 0.065
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# VIA1.2 Minimum spacing of via1
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drc["via1_to_via1"] = 0.075
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drc.add_layer("via1",
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width = 0.065,
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spacing = 0.075)
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal2"] = 0.07
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# METALINT.2 Minimum spacing of intermediate metal
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drc["metal2_to_metal2"] = 0.07
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drc.add_layer("m2",
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width = 0.07,
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spacing = 0.07)
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal2_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = 0
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drc.add_enclosure("m2",
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layer = "via1",
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enclosure = 0,
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extension = 0.035)
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal2_extend_via2"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = 0
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# Not a rule
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drc["minarea_metal2"] = 0
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drc.add_enclosure("m2",
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layer = "via2",
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enclosure = 0,
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extension = 0.035)
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via2"] = 0.065
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via2_to_via2"] = 0.075
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drc.add_layer("via2",
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width = 0.065,
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spacing = 0.075)
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal3"] = 0.07
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# METALINT.2 Minimum spacing of intermediate metal
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#drc["metal3_to_metal3"] = 0.07
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# Minimum spacing of metal3 wider than 0.09 & longer than 0.3 = 0.09
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# Minimum spacing of metal3 wider than 0.27 & longer than 0.9 = 0.27
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# Minimum spacing of metal3 wider than 0.5 & longer than 1.8 = 0.5
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||||
# Minimum spacing of metal3 wider than 0.9 & longer than 2.7 = 0.9
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# Minimum spacing of metal3 wider than 1.5 & longer than 4.0 = 1.5
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drc["metal3_to_metal3"] = drc_lut({(0.00, 0.0) : 0.07,
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(0.09, 0.3) : 0.09,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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||||
(1.50, 4.0) : 1.5})
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||||
# Minimum spacing of m3 wider than 0.09 & longer than 0.3 = 0.09
|
||||
# Minimum spacing of m3 wider than 0.27 & longer than 0.9 = 0.27
|
||||
# Minimum spacing of m3 wider than 0.5 & longer than 1.8 = 0.5
|
||||
# Minimum spacing of m3 wider than 0.9 & longer than 2.7 = 0.9
|
||||
# Minimum spacing of m3 wider than 1.5 & longer than 4.0 = 1.5
|
||||
drc.add_layer("m3",
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||||
width = 0.07,
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||||
spacing = drc_lut({(0.00, 0.0) : 0.07,
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||||
(0.09, 0.3) : 0.09,
|
||||
(0.27, 0.9) : 0.27,
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||||
(0.50, 1.8) : 0.5,
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||||
(0.90, 2.7) : 0.9,
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||||
(1.50, 4.0) : 1.5}))
|
||||
# METALINT.3 Minimum enclosure around via1 on two opposite sides
|
||||
drc["metal3_extend_via2"] = 0.035
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||||
# Reserved for asymmetric enclosures
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||||
drc["metal3_enclosure_via2"] = 0
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||||
drc.add_enclosure("m3",
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||||
layer = "via2",
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||||
enclosure = 0,
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||||
extension = 0.035)
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||||
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||||
# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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||||
drc["metal3_extend_via3"]=0.035
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||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via3"] = 0
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||||
# Not a rule
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||||
drc["minarea_metal3"] = 0
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||||
drc.add_enclosure("m3",
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||||
layer = "via3",
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||||
enclosure = 0,
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||||
extension = 0.035)
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||||
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||||
# VIA2-3.1 Minimum width of Via[2-3]
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||||
drc["minwidth_via3"] = 0.07
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||||
# VIA2-3.2 Minimum spacing of Via[2-3]
|
||||
drc["via3_to_via3"] = 0.085
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||||
drc.add_layer("via3",
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||||
width = 0.07,
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||||
spacing = 0.085)
|
||||
|
||||
# METALSMG.1 Minimum width of semi-global metal
|
||||
drc["minwidth_metal4"] = 0.14
|
||||
# METALSMG.2 Minimum spacing of semi-global metal
|
||||
#drc["metal4_to_metal4"] = 0.14
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||||
# Minimum spacing of metal4 wider than 0.27 & longer than 0.9 = 0.27
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||||
# Minimum spacing of metal4 wider than 0.5 & longer than 1.8 = 0.5
|
||||
# Minimum spacing of metal4 wider than 0.9 & longer than 2.7 = 0.9
|
||||
# Minimum spacing of metal4 wider than 1.5 & longer than 4.0 = 1.5
|
||||
drc["metal4_to_metal4"] = drc_lut({(0.00, 0.0) : 0.14,
|
||||
(0.27, 0.9) : 0.27,
|
||||
(0.50, 1.8) : 0.5,
|
||||
(0.90, 2.7) : 0.9,
|
||||
(1.50, 4.0) : 1.5})
|
||||
# Minimum spacing of m4 wider than 0.27 & longer than 0.9 = 0.27
|
||||
# Minimum spacing of m4 wider than 0.5 & longer than 1.8 = 0.5
|
||||
# Minimum spacing of m4 wider than 0.9 & longer than 2.7 = 0.9
|
||||
# Minimum spacing of m4 wider than 1.5 & longer than 4.0 = 1.5
|
||||
drc.add_layer("m4",
|
||||
width = 0.14,
|
||||
spacing = drc_lut({(0.00, 0.0) : 0.14,
|
||||
(0.27, 0.9) : 0.27,
|
||||
(0.50, 1.8) : 0.5,
|
||||
(0.90, 2.7) : 0.9,
|
||||
(1.50, 4.0) : 1.5}))
|
||||
# METALSMG.3 Minimum enclosure around via[3-6] on two opposite sides
|
||||
drc["metal4_extend_via3"] = 0.0025
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["metal4_enclosure_via3"] = 0.0025
|
||||
# Not a rule
|
||||
drc["minarea_metal4"] = 0
|
||||
drc.add_enclosure("m4",
|
||||
layer = "via3",
|
||||
enclosure = 0.0025)
|
||||
|
||||
# Metal 5-10 are ommitted
|
||||
|
||||
|
||||
|
||||
###################################################
|
||||
##END DRC/LVS Rules
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##Spice Simulation Parameters
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
#spice info
|
||||
@@ -337,6 +417,11 @@ parameter["sa_inv_nmos_size"] = 0.27 #micro-meters
|
||||
parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
|
||||
blackbox_bitcell = False
|
||||
|
||||
@@ -35,9 +35,5 @@ except:
|
||||
DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
|
||||
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
|
||||
|
||||
# try:
|
||||
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
|
||||
# except:
|
||||
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
|
||||
os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
|
||||
os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__))
|
||||
|
||||
|
||||
@@ -1,9 +1,24 @@
|
||||
import os
|
||||
from design_rules import *
|
||||
from module_type import *
|
||||
from custom_cell_properties import CellProperties
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for SCMOS 3me, subm, 180nm.
|
||||
"""
|
||||
# This uses the default classes to instantiate module from
|
||||
# '$OPENRAM_HOME/compiler/modules'.
|
||||
# Using tech_modules['cellname'] you can override each class by providing a custom
|
||||
# implementation in '$OPENRAM_TECHDIR/modules/'
|
||||
# For example: tech_modules['contact'] = 'contact_scn3me'
|
||||
tech_modules = ModuleType()
|
||||
|
||||
###################################################
|
||||
# Custom cell properties
|
||||
###################################################
|
||||
cell_properties = CellProperties()
|
||||
cell_properties.bitcell.mirror.x = True
|
||||
cell_properties.bitcell.mirror.y = False
|
||||
|
||||
#GDS file info
|
||||
GDS={}
|
||||
@@ -29,24 +44,24 @@ GDS["zoom"] = 0.5
|
||||
|
||||
# create the GDS layer map
|
||||
layer={}
|
||||
layer["vtg"] = -1
|
||||
layer["vth"] = -1
|
||||
layer["contact"] = 47
|
||||
layer["pwell"] = 41
|
||||
layer["nwell"] = 42
|
||||
layer["active"] = 43
|
||||
layer["pimplant"] = 44
|
||||
layer["nimplant"] = 45
|
||||
layer["poly"] = 46
|
||||
layer["active_contact"] = 48
|
||||
layer["metal1"] = 49
|
||||
layer["via1"] = 50
|
||||
layer["metal2"] = 51
|
||||
layer["via2"] = 61
|
||||
layer["metal3"] = 62
|
||||
layer["text"] = 63
|
||||
layer["boundary"] = 63
|
||||
layer["blockage"] = 83
|
||||
layer["vtg"] = (-1, 0)
|
||||
layer["vth"] = (-1, 0)
|
||||
layer["contact"] = (47, 0)
|
||||
layer["pwell"] = (41, 0)
|
||||
layer["nwell"] = (42, 0)
|
||||
layer["active"] = (43, 0)
|
||||
layer["pimplant"] = (44, 0)
|
||||
layer["nimplant"] = (45, 0)
|
||||
layer["poly"] = (46, 0)
|
||||
layer["active_contact"] = (48, 0)
|
||||
layer["metal1"] = (49, 0)
|
||||
layer["via1"] = (50, 0)
|
||||
layer["metal2"] = (51, 0)
|
||||
layer["via2"] = (61, 0)
|
||||
layer["metal3"] = (62, 0)
|
||||
layer["text"] = (63, 0)
|
||||
layer["boundary"] = (63, 0)
|
||||
layer["blockage"] = (83, 0)
|
||||
|
||||
###################################################
|
||||
##END GDS Layer Map
|
||||
@@ -277,3 +292,15 @@ parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of dr
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##BEGIN Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
###################################################
|
||||
##END Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
@@ -35,9 +35,5 @@ except:
|
||||
DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech"
|
||||
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
|
||||
|
||||
# try:
|
||||
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
|
||||
# except:
|
||||
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
|
||||
os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
|
||||
os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__))
|
||||
|
||||
|
||||
@@ -1,5 +0,0 @@
|
||||
path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech
|
||||
tech load SCN4M_SUBM.20 -noprompt
|
||||
scalegrid 1 4
|
||||
set GND gnd
|
||||
set VDD vdd
|
||||
@@ -0,0 +1,8 @@
|
||||
set openram_paths [split $::env(OPENRAM_TECH) ":"]
|
||||
foreach p $openram_paths {
|
||||
path sys +$p/scn4m_subm/tech
|
||||
}
|
||||
tech load SCN4M_SUBM.20 -noprompt
|
||||
scalegrid 1 4
|
||||
set GND gnd
|
||||
set VDD vdd
|
||||
@@ -6,7 +6,7 @@ equate class {-circuit1 pfet} {-circuit2 p}
|
||||
flatten class {-circuit1 dummy_cell_6t}
|
||||
flatten class {-circuit1 dummy_cell_1rw_1r}
|
||||
flatten class {-circuit1 dummy_cell_1w_1r}
|
||||
flatten class {-circuit1 bitcell_array_0}
|
||||
flatten class {-circuit1 pbitcell}
|
||||
flatten class {-circuit1 pbitcell_0}
|
||||
flatten class {-circuit1 pbitcell_1}
|
||||
property {-circuit1 nfet} remove as ad ps pd
|
||||
+203
-123
@@ -7,12 +7,34 @@
|
||||
#
|
||||
import os
|
||||
from design_rules import *
|
||||
from module_type import *
|
||||
from custom_cell_properties import cell_properties
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for SCMOS 4m, 0.35um
|
||||
"""
|
||||
|
||||
#GDS file info
|
||||
###################################################
|
||||
# Custom modules
|
||||
###################################################
|
||||
|
||||
# This uses the default classes to instantiate module from
|
||||
# '$OPENRAM_HOME/compiler/modules'.
|
||||
# Using tech_modules['cellname'] you can override each class by providing a custom
|
||||
# implementation in '$OPENRAM_TECHDIR/modules/'
|
||||
# For example: tech_modules['contact'] = 'contact_scn4m'
|
||||
tech_modules = module_type()
|
||||
|
||||
###################################################
|
||||
# Custom cell properties
|
||||
###################################################
|
||||
cell_properties = cell_properties()
|
||||
cell_properties.bitcell.mirror.x = True
|
||||
cell_properties.bitcell.mirror.y = False
|
||||
|
||||
###################################################
|
||||
# GDS file info
|
||||
###################################################
|
||||
GDS={}
|
||||
# gds units
|
||||
# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
|
||||
@@ -28,40 +50,73 @@ GDS["unit"]=(0.001,1e-6)
|
||||
# default label zoom
|
||||
GDS["zoom"] = 0.5
|
||||
|
||||
###################################################
|
||||
# Interconnect stacks
|
||||
###################################################
|
||||
|
||||
poly_stack = ("poly", "poly_contact", "m1")
|
||||
active_stack = ("active", "active_contact", "m1")
|
||||
m1_stack = ("m1", "via1", "m2")
|
||||
m2_stack = ("m2", "via2", "m3")
|
||||
m3_stack = ("m3", "via3", "m4")
|
||||
|
||||
layer_indices = {"poly": 0,
|
||||
"active": 0,
|
||||
"m1": 1,
|
||||
"m2": 2,
|
||||
"m3": 3,
|
||||
"m4": 4}
|
||||
|
||||
# The FEOL stacks get us up to m1
|
||||
feol_stacks = [poly_stack,
|
||||
active_stack]
|
||||
|
||||
# The BEOL stacks are m1 and up
|
||||
beol_stacks = [m1_stack,
|
||||
m2_stack,
|
||||
m3_stack]
|
||||
|
||||
layer_stacks = feol_stacks + beol_stacks
|
||||
|
||||
preferred_directions = {"poly": "V",
|
||||
"active": "V",
|
||||
"m1": "H",
|
||||
"m2": "V",
|
||||
"m3": "H",
|
||||
"m4": "V"}
|
||||
|
||||
###################################################
|
||||
# Power grid
|
||||
###################################################
|
||||
# Use M3/M4
|
||||
power_grid = m3_stack
|
||||
|
||||
###################################################
|
||||
##GDS Layer Map
|
||||
###################################################
|
||||
|
||||
# create the GDS layer map
|
||||
layer={}
|
||||
layer["vtg"] = -1
|
||||
layer["vth"] = -1
|
||||
layer["contact"] = 47
|
||||
layer["pwell"] = 41
|
||||
layer["nwell"] = 42
|
||||
layer["active"] = 43
|
||||
layer["pimplant"] = 44
|
||||
layer["nimplant"] = 45
|
||||
layer["poly"] = 46
|
||||
layer["active_contact"] = 48
|
||||
layer["metal1"] = 49
|
||||
layer["via1"] = 50
|
||||
layer["metal2"] = 51
|
||||
layer["via2"] = 61
|
||||
layer["metal3"] = 62
|
||||
layer["via3"] = 30
|
||||
layer["metal4"] = 31
|
||||
layer["text"] = 63
|
||||
layer["boundary"] = 63
|
||||
layer["blockage"] = 83
|
||||
layer={}
|
||||
layer["pwell"] = (41, 0)
|
||||
layer["nwell"] = (42, 0)
|
||||
layer["active"] = (43, 0)
|
||||
layer["pimplant"] = (44, 0)
|
||||
layer["nimplant"] = (45, 0)
|
||||
layer["poly"] = (46, 0)
|
||||
layer["poly_contact"] = (47, 0)
|
||||
layer["active_contact"] = (48, 0)
|
||||
layer["m1"] = (49, 0)
|
||||
layer["via1"] = (50, 0)
|
||||
layer["m2"] = (51, 0)
|
||||
layer["via2"] = (61, 0)
|
||||
layer["m3"] = (62, 0)
|
||||
layer["via3"] = (30, 0)
|
||||
layer["m4"] = (31, 0)
|
||||
layer["text"] = (63, 0)
|
||||
layer["boundary"] = (63, 0)
|
||||
|
||||
###################################################
|
||||
##END GDS Layer Map
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##DRC/LVS Rules Setup
|
||||
# DRC/LVS Rules Setup
|
||||
###################################################
|
||||
_lambda_ = 0.2
|
||||
|
||||
@@ -79,10 +134,6 @@ drclvs_home=os.environ.get("DRCLVS_HOME")
|
||||
|
||||
drc = design_rules("scn4me_sub")
|
||||
|
||||
drc["body_tie_down"] = 0
|
||||
drc["has_pwell"] = True
|
||||
drc["has_nwell"] = True
|
||||
|
||||
#grid size is 1/2 a lambda
|
||||
drc["grid"]=0.5*_lambda_
|
||||
|
||||
@@ -95,150 +146,173 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
|
||||
drc["minwidth_tx"] = 4*_lambda_
|
||||
drc["minlength_channel"] = 2*_lambda_
|
||||
|
||||
# 1.3 Minimum spacing between wells of same type (if both are drawn)
|
||||
drc["well_to_well"] = 6*_lambda_
|
||||
# 1.4 Minimum spacing between wells of different type (if both are drawn)
|
||||
# 1.4 Minimum spacing between wells of different type (if both are drawn)
|
||||
drc["pwell_to_nwell"] = 0
|
||||
# 1.1 Minimum width
|
||||
drc["minwidth_well"] = 12*_lambda_
|
||||
# 1.3 Minimum spacing between wells of same type (if both are drawn)
|
||||
# 1.1 Minimum width
|
||||
drc.add_layer("nwell",
|
||||
width = 12*_lambda_,
|
||||
spacing = 6*_lambda_)
|
||||
drc.add_layer("pwell",
|
||||
width = 12*_lambda_,
|
||||
spacing = 6*_lambda_)
|
||||
|
||||
# 3.1 Minimum width
|
||||
drc["minwidth_poly"] = 2*_lambda_
|
||||
# 3.2 Minimum spacing over active
|
||||
drc["poly_to_poly"] = 3*_lambda_
|
||||
drc.add_layer("poly",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 3.3 Minimum gate extension of active
|
||||
drc["poly_extend_active"] = 2*_lambda_
|
||||
# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
|
||||
drc["poly_to_polycontact"] = 4*_lambda_
|
||||
drc["poly_to_contact"] = 4*_lambda_
|
||||
# ??
|
||||
drc["active_enclosure_gate"] = 0.0
|
||||
drc["active_enclose_gate"] = 0.0
|
||||
# 3.5 Minimum field poly to active
|
||||
drc["poly_to_active"] = _lambda_
|
||||
# 3.2.a Minimum spacing over field poly
|
||||
drc["poly_to_field_poly"] = 3*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_poly"] = 0.0
|
||||
|
||||
# ??
|
||||
drc["active_to_body_active"] = 4*_lambda_ # Fix me
|
||||
# 2.1 Minimum width
|
||||
drc["minwidth_active"] = 3*_lambda_
|
||||
# 2.2 Minimum spacing
|
||||
drc["active_to_active"] = 3*_lambda_
|
||||
drc.add_layer("active",
|
||||
width = 3*_lambda_,
|
||||
spacing = 4*_lambda_)
|
||||
|
||||
# 2.3 Source/drain active to well edge
|
||||
drc["well_enclosure_active"] = 6*_lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["well_extend_active"] = 6*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_active"] = 0.0
|
||||
drc.add_enclosure("nwell",
|
||||
layer = "active",
|
||||
enclosure = 6*_lambda_)
|
||||
drc.add_enclosure("pwell",
|
||||
layer = "active",
|
||||
enclosure = 6*_lambda_)
|
||||
|
||||
# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
|
||||
drc["implant_to_channel"] = 3*_lambda_
|
||||
# 4.2 Minimum select overlap of active
|
||||
drc["implant_enclosure_active"] = 2*_lambda_
|
||||
drc.add_enclosure("implant",
|
||||
layer = "active",
|
||||
enclosure = 2*_lambda_)
|
||||
# 4.3 Minimum select overlap of contact
|
||||
drc["implant_enclosure_contact"] = _lambda_
|
||||
drc.add_enclosure("implant",
|
||||
layer = "contact",
|
||||
enclosure = _lambda_)
|
||||
# Not a rule
|
||||
drc["implant_to_contact"] = 0
|
||||
# Not a rule
|
||||
drc["implant_to_implant"] = 0
|
||||
# Not a rule
|
||||
drc["minwidth_implant"] = 0
|
||||
drc.add_layer("implant",
|
||||
width = 0,
|
||||
spacing = 0)
|
||||
|
||||
# 6.1 Exact contact size
|
||||
drc["minwidth_contact"] = 2*_lambda_
|
||||
# 5.3 Minimum contact spacing
|
||||
drc["contact_to_contact"] = 3*_lambda_
|
||||
# 6.2.b Minimum active overlap
|
||||
drc["active_enclosure_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["active_extend_contact"] = _lambda_
|
||||
# 5.2.b Minimum poly overlap
|
||||
drc["poly_enclosure_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["poly_extend_contact"] = _lambda_
|
||||
drc.add_layer("active_contact",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 6.2.b Minimum active overlap
|
||||
drc.add_enclosure("active",
|
||||
layer = "active_contact",
|
||||
enclosure = _lambda_)
|
||||
drc.add_enclosure("active",
|
||||
layer = "contact",
|
||||
enclosure = _lambda_)
|
||||
# Reserved for other technologies
|
||||
drc["contact_to_gate"] = 2*_lambda_
|
||||
drc["active_contact_to_gate"] = 2*_lambda_
|
||||
# 5.4 Minimum spacing to gate of transistor
|
||||
drc["contact_to_poly"] = 2*_lambda_
|
||||
|
||||
drc["poly_contact_to_gate"] = 2*_lambda_
|
||||
|
||||
# 6.1 Exact contact size
|
||||
# 5.3 Minimum contact spacing
|
||||
drc.add_layer("poly_contact",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 5.2.b Minimum poly overlap
|
||||
drc.add_enclosure("poly",
|
||||
layer = "poly_contact",
|
||||
enclosure = _lambda_)
|
||||
# Reserved for other technologies
|
||||
drc["poly_contact_to_gate"] = 2*_lambda_
|
||||
# 5.4 Minimum spacing to gate of transistor
|
||||
drc["poly_contact_to_poly"] = 2*_lambda_
|
||||
|
||||
# 7.1 Minimum width
|
||||
drc["minwidth_metal1"] = 3*_lambda_
|
||||
# 7.2 Minimum spacing
|
||||
drc["metal1_to_metal1"] = 3*_lambda_
|
||||
drc.add_layer("m1",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 7.3 Minimum overlap of any contact
|
||||
drc["metal1_enclosure_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["metal1_extend_contact"] = _lambda_
|
||||
# 8.3 Minimum overlap by metal1
|
||||
drc["metal1_enclosure_via1"] = _lambda_
|
||||
# Reserve for asymmetric enclosures
|
||||
drc["metal1_extend_via1"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal1"] = 0
|
||||
drc.add_enclosure("m1",
|
||||
layer = "poly_contact",
|
||||
enclosure = _lambda_)
|
||||
drc.add_enclosure("m1",
|
||||
layer = "active_contact",
|
||||
enclosure = _lambda_)
|
||||
# 8.3 Minimum overlap by m1
|
||||
drc.add_enclosure("m1",
|
||||
layer = "via1",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 8.1 Exact size
|
||||
drc["minwidth_via1"] = 2*_lambda_
|
||||
# 8.2 Minimum via1 spacing
|
||||
drc["via1_to_via1"] = 3*_lambda_
|
||||
drc.add_layer("via1",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 9.1 Minimum width
|
||||
drc["minwidth_metal2"] = 3*_lambda_
|
||||
# 9.2 Minimum spacing
|
||||
drc["metal2_to_metal2"] = 3*_lambda_
|
||||
drc.add_layer("m2",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
# 9.3 Minimum overlap of via1
|
||||
drc["metal2_extend_via1"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via1"] = _lambda_
|
||||
# 14.3 Minimum overlap by metal2
|
||||
drc["metal2_extend_via2"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via2"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal2"] = 0
|
||||
drc.add_enclosure("m2",
|
||||
layer = "via1",
|
||||
enclosure = _lambda_)
|
||||
# 14.3 Minimum overlap by m2
|
||||
drc.add_enclosure("m2",
|
||||
layer = "via2",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 14.1 Exact size
|
||||
drc["minwidth_via2"] = 2*_lambda_
|
||||
# 14.2 Minimum spacing
|
||||
drc["via2_to_via2"] = 3*_lambda_
|
||||
drc.add_layer("via2",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 15.1 Minimum width
|
||||
drc["minwidth_metal3"] = 3*_lambda_
|
||||
# 15.2 Minimum spacing to metal3
|
||||
drc["metal3_to_metal3"] = 3*_lambda_
|
||||
# 15.2 Minimum spacing to m3
|
||||
drc.add_layer("m3",
|
||||
width = 3*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 15.3 Minimum overlap of via 2
|
||||
drc["metal3_extend_via2"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via2"] = _lambda_
|
||||
# 21.3 Minimum overlap by metal3
|
||||
drc["metal3_extend_via3"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via3"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal3"] = 0
|
||||
drc.add_enclosure("m3",
|
||||
layer = "via2",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 21.3 Minimum overlap by m3
|
||||
drc.add_enclosure("m3",
|
||||
layer = "via3",
|
||||
enclosure = _lambda_)
|
||||
|
||||
# 21.1 Exact size
|
||||
drc["minwidth_via3"] = 2*_lambda_
|
||||
# 21.2 Minimum spacing
|
||||
drc["via3_to_via3"] = 3*_lambda_
|
||||
drc.add_layer("via3",
|
||||
width = 2*_lambda_,
|
||||
spacing = 3*_lambda_)
|
||||
|
||||
# 22.1 Minimum width
|
||||
drc["minwidth_metal4"] = 6*_lambda_
|
||||
# 22.2 Minimum spacing to metal4
|
||||
drc["metal4_to_metal4"] = 6*_lambda_
|
||||
# 22.2 Minimum spacing to m4
|
||||
drc.add_layer("m4",
|
||||
width = 6*_lambda_,
|
||||
spacing = 6*_lambda_)
|
||||
|
||||
# 22.3 Minimum overlap of via 3
|
||||
drc["metal4_extend_via3"] = 2*_lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal4_enclosure_via3"] = 2*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal4"] = 0
|
||||
drc.add_enclosure("m4",
|
||||
layer = "via3",
|
||||
enclosure = 2*_lambda_)
|
||||
|
||||
###################################################
|
||||
##END DRC/LVS Rules
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##Spice Simulation Parameters
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice model info
|
||||
@@ -303,5 +377,11 @@ parameter["sa_inv_nmos_size"] = 9*_lambda_
|
||||
parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
blackbox_bitcell = False
|
||||
|
||||
Reference in New Issue
Block a user