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Author SHA1 Message Date
Emil J. Tywoniak f5e357dbf6 equiv_make: don't copy $input_port 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 32bc4c869c rtlil: fix cloneInto in signorm 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 1c08281114 rtlil: sigNormalize Module when added to Design in signorm mode 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 6ab0147609 rtlil_bufnorm: more xlog 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak d48be905be intel: register bram celltypes 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 35263298db rtlil_bufnorm: ignore timing info harder 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak d2c99efa2a gowin: replace positional arguments in cells_sim.v with named 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak b632f6dc3d Revert "techmap: call hierarchy on map files to determine port directions" 
This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.
 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 3ecb03eaa0 hierarchy: tolerance for apparent recursive instances in techmap files 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 9226f55d17 techmap: call hierarchy on map files to determine port directions 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 74118fa9d2 tests: use memory -bram-register in tests/bram 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak a02f731a2e memory: add -bram-register 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 027f84c2e5 memory_bram: add -register 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 5b0023b476 ffmerge: initvals signorm compatibility fixup 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 1336ca079e timinginfo: special-case $specify2 in signorm invariant 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 8e3d56c0d8 opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 17a8797d1a connect: remove input ports on conflict 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 610c560a2a opt_dff: sigma harder, FfDataSigMapped 2026-09-17 15:43:54 +02:00
Emil J. Tywoniak 49548b2648 ff: add FfDataSigMapped 2026-09-17 14:23:07 +02:00
Emil J. Tywoniak 7818419608 tests: fix rtlil roundtrip test 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 1e1cc5c916 design: fix signorm commit connectivity to design 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak b17441aa0d cxxrtl: ignore $input_port 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 375f4600db flatten: redo signormalization to work around fanout issue 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak c3807b4137 abstract: fix test signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 7a09c32040 signorm: disable passes that use rewrite_sigspecs 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 238bf5905d aiger: ignore $input_port 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 2f37005ada check: stitch info about $connect ports together for driver analysis 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 6dd987ee3c signorm: remove $input cells when leaving 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 5938e03e5d abstract: skip $input_port cells 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak bd4f16fd9e flatten: skip $input_port cells in template module 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 3a606ec48e signorm: skip const when fixing fanout 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 6c048fdfb9 signorm: disable in passes that use swap_names 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak db1b0ee8a2 opt_expr: fix invert_map 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 41d4c1da36 satgen: support $connect 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 8d8a1cb46c rtlil: add dump_sigmap for hacky signorm debugging 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak e6b7a50b30 techmap: disable signorm more 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak e4b62727bd techmap: disable signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 01e17a383a opt_hier: disable signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak a55244ee3c timinginfo: disable output wire check due to signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 196cb50038 rtlil: forbid rewrite_sigspecs in signorm 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 8a9f038d54 opt_merge_inc: re add initvals deletion 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 2ccfd2b23b synth_ice40: always read abc9 model to understand port direction 2026-09-17 14:13:55 +02:00
Emil J. Tywoniak ba37814053 tests: adjust to input_port and init behavior (sketchy) 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak fc7f53ba76 tests: adjust to input_port and init behavior (sketchy) 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak d5f55fcd11 tests: adjust to input_port and init behavior (sketchy) 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak 34b8284bcb wreduce: fixup initvals after setPort 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak 42a9ec0dba ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak 33fc543083 tests: adjust to input_port and init behavior (sketchy) 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak 6f27925eff rtlil: fix zero width SigSpec crash in signorm setPort unsetPort 2026-09-17 14:12:38 +02:00
Emil J. Tywoniak e2817ef5a1 bug2920: disable 2026-09-17 14:12:38 +02:00