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synth_ice40: always read abc9 model to understand port direction

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This commit is contained in:
Emil J. Tywoniak
2026-09-17 14:13:55 +02:00
parent ba37814053
commit 2ccfd2b23b
1 changed files with 1 additions and 1 deletions
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techlibs/ice40/synth_ice40.cc
+1 -1
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@@ -360,6 +360,7 @@ struct SynthIce40Pass : public ScriptPass
run("techmap");
else {
run("ice40_wrapcarry");
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
run("opt -fast");
@@ -389,7 +390,6 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
}
if (!noabc) {
run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))