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timinginfo: special-case $specify2 in signorm invariant

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This commit is contained in:
Emil J. Tywoniak
2026-09-17 15:43:54 +02:00
parent 8e3d56c0d8
commit 1336ca079e
2 changed files with 4 additions and 5 deletions
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kernel/rtlil_bufnorm.cc
+1 -1
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@@ -1062,7 +1062,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
{
bool is_input_port = false;
if (module->sig_norm_index != nullptr) {
if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) {
module->sig_norm_index->sigmap.apply(signal);
auto dir = port_dir(portname);
kernel/timinginfo.h
+3 -4
View File
@@ -106,10 +106,9 @@ struct TimingInfo
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
// TODO disabled check because signorm breaks this assumption
// for (const auto &c : dst.chunks())
// if (!c.wire || !c.wire->port_output)
// log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
for (const auto &c : dst.chunks())
if (!c.wire || !c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);