Emil J. Tywoniak
52faadc45a
pyosys: twines
2026-10-02 18:42:01 +02:00
Emil J. Tywoniak
2dc8c1474f
tests: cover twines, name publicity, hashing and sorting
2026-10-02 18:42:01 +02:00
Emil J. Tywoniak
c3268923f4
tests: trivial twine damage
2026-10-02 18:42:01 +02:00
Tharaka
ebaecb50bf
mcm: refactor and move score_intermediate into scorer
2026-10-02 09:26:57 +02:00
Tharaka
ca911ddb38
multiple constant multiplication (mcm) pass
2026-10-02 09:26:57 +02:00
Emil J
2750a02e0c
Merge pull request #6264 from YosysHQ/emil/read_verilog-array-signedness
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read_verilog: fix sign extension in array pattern assignments
2026-10-01 13:56:38 +00:00
nella
a74edc9be8
Check shift B signedness in shiftadd.
2026-09-30 18:15:40 +02:00
Emil J
cd7af6bcb6
Merge pull request #6263 from YosysHQ/emil/abc_new-unmapped-error-handling
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abc_new: improve error handling of &get
2026-09-30 14:11:56 +00:00
nella
8ce92653e4
Merge pull request #6238 from YosysHQ/nella/shiftadd-signed-a
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Materialize A sign extension in shiftadd [sc-924]
2026-09-30 13:40:11 +00:00
Emil J. Tywoniak
c783ccfdd6
read_verilog: fix sign extension in array pattern assignments
2026-09-30 12:59:01 +02:00
Emil J
4ca90baf18
Merge pull request #6260 from YosysHQ/emil/proc_dlatch-feedback-loop
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proc_dlatch: error on logic loop in mux tree
2026-09-30 10:36:26 +00:00
Emil J. Tywoniak
a51ed0614c
abc_new: add test for &get error handling
2026-09-30 12:19:21 +02:00
Emil J. Tywoniak
8520f2385a
proc_dlatch: reject a logic loop in feedback traversal
2026-09-29 17:28:27 +02:00
nella
2b4f1bce68
Fix abc9 private init.
2026-09-27 19:55:42 +02:00
Emil J. Tywoniak
692ca9c0b8
bufnorm: cover IO pad handling with tests
2026-09-23 11:50:36 +02:00
nella
3b7c09934a
Materialize A sign extension in shiftadd.
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$shr and $shift sign-extend A to max(A_WIDTH, Y_WIDTH) before shifting.
shiftadd resliced A without that extension and left A_SIGNED set, so the
narrowed A was sign-extended a second time, from the wrong bit. Bake the
extension in before reslicing and clear A_SIGNED.
When the constant offset consumed all of A this also left an empty A on a
signed $shr, which techmap lowered to x.
Fixes #6214 , fixes #6041 .
2026-09-23 08:00:44 +02:00
nella
57ab8ef2c6
Merge remote-tracking branch 'origin/main' into nella/latch-diagnostics-2
2026-09-22 16:49:41 +02:00
nella
d4f0028e7f
Merge pull request #6178 from YosysHQ/nella/muladd-reassoc
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canonicalize $macc unmapping for better DSP inference [sc-814]
2026-09-22 13:04:16 +00:00
nella
ec2b287c1e
Merge pull request #6150 from YosysHQ/nella/rm-unused-ports
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rmports: remove output ports unused by all instances [sc-799]
2026-09-22 13:01:17 +00:00
nella
90e281a964
Reject abc9 boxes without an input or an output.
2026-09-21 16:58:03 +02:00
nella
315f8194a0
Don't mark cells w no unput as boxes.
2026-09-21 16:58:03 +02:00
nella
d8d54fafd7
Mark cells as imported correctly.
2026-09-21 16:57:58 +02:00
nella
c3c5388ed9
Clean up after bufnorm.
2026-09-21 16:57:53 +02:00
nella
5726f981fa
Keep keep wires in abc.
2026-09-21 16:57:41 +02:00
nella
c0f8629f7c
Keep scopeinfo.
2026-09-21 16:57:41 +02:00
nella
859b245eb5
Don't divide by zero with zero delays.
2026-09-21 16:57:41 +02:00
nella
e7dd15a4b8
Clear options per invocation.
2026-09-21 16:57:26 +02:00
nella
ce87b2fb3d
Expect abc error.
2026-09-21 16:39:09 +02:00
nella
edb9422be5
Rm undeclared cell type test.
2026-09-21 16:33:47 +02:00
nella
ba063d0af2
Skip failing tests.
2026-09-21 16:33:47 +02:00
nella
b60492b203
Repro tie box, portarcs, read_liberty.
2026-09-21 16:33:47 +02:00
nella
fb74fe275d
Repro dropped keep and scopeinfo.
2026-09-21 16:33:47 +02:00
nella
aa19d5ea02
Repro bufnorm leftovers.
2026-09-21 16:33:47 +02:00
nella
03e33b4cd6
Repro option accumulation.
2026-09-21 16:33:47 +02:00
nella
ba581d42d1
Add issue regressions.
2026-09-21 16:33:47 +02:00
nella
fd766716f4
Generate librelane ABC scripts.
2026-09-21 16:33:47 +02:00
nella
f3934d1ed8
Add librelane spm tests.
2026-09-21 16:33:47 +02:00
nella
5a11d677dd
Test memory macro.
2026-09-21 16:33:47 +02:00
nella
22b5ab620c
Port OpenROAD syn cases.
2026-09-21 16:33:47 +02:00
nella
9a7221f103
Port OpenROAD cut tests.
2026-09-21 16:33:47 +02:00
nella
7649fac442
Test hierarchy and selections.
2026-09-21 16:33:47 +02:00
nella
666df5e9c8
Test boundary cells.
2026-09-21 16:33:47 +02:00
nella
ed8b0bf9f7
Test port corner cases.
2026-09-21 16:33:47 +02:00
nella
8955e0fe7a
Add abc_new tests.
2026-09-21 16:33:47 +02:00
nella
9e8f12b9b3
Merge pull request #6207 from YosysHQ/nella/xilinx-rdfirst-xc7
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xilinx: fix BRAM mapping for negedge port next to READ_FIRST port [sc-917]
2026-09-16 13:14:35 +00:00
nella
5c338c559a
Reassociate sums of products via $macc.
2026-09-16 14:26:07 +02:00
nella
e2051bddb3
Revert.
2026-09-16 14:26:07 +02:00
nella
4ef51514f1
Add muladd rule.
2026-09-16 14:26:07 +02:00
nella
a651db986a
xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
Lofty
415dfc0960
xaiger2: add testcase from #4349
2026-09-16 08:13:23 +01:00
Emil J. Tywoniak
Tharaka
Emil J
nella
nella
Lofty