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Merge pull request #6150 from YosysHQ/nella/rm-unused-ports
rmports: remove output ports unused by all instances [sc-799]
This commit is contained in:
nella
+118
-9
@@ -30,33 +30,127 @@ struct RmportsPassPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" rmports [selection]\n");
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log(" rmports [options] [selection]\n");
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log("\n");
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log("This pass identifies ports in the selected modules which are not used or\n");
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log("driven and removes them.\n");
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log("\n");
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log("An output which is driven inside the module is also removed, if no\n");
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log("instance of the module uses it. The top module, a module which nothing\n");
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log("instantiates, and a port with the keep attribute stay. This needs a module\n");
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log("with the top attribute (see hierarchy -top). Without one, a parent design\n");
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log("which is not loaded can still use these ports.\n");
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log("\n");
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log(" -purge\n");
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log(" remove driven outputs also when no module has the top attribute\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
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size_t argidx = 1;
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bool purge_mode = false;
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size_t argidx;
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for(argidx = 1; argidx < args.size(); argidx++)
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{
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if(args[argidx] == "-purge")
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{
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purge_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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// The set of ports we removed
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dict<IdString, pool<IdString>> removed_ports;
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// Find the ports which are used by some instance in the design
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dict<IdString, pool<IdString>> used_instance_ports;
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pool<IdString> instantiated;
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pool<IdString> positional;
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CollectInstantiated(design, instantiated);
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bool scan_outputs = purge_mode || HasTopModule(design);
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if(scan_outputs)
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ScanInstances(design, used_instance_ports, positional);
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else
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log("The design has no module with the top attribute. Outputs which are driven inside their module stay.\n");
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// Find all of the unused ports, and remove them from that module
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auto modules = design->selected_modules();
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for(auto mod : modules)
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ScanModule(mod, removed_ports);
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for(auto mod : design->selected_modules())
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{
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bool keep_outputs = !scan_outputs || !instantiated.count(mod->name) ||
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positional.count(mod->name) || mod->get_bool_attribute(ID::top);
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ScanModule(mod, removed_ports, used_instance_ports[mod->name], keep_outputs);
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}
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// Remove the unused ports from all instances of those modules
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for(auto mod : modules)
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for(auto mod : design->modules())
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CleanupModule(mod, removed_ports);
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}
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// The cell types which some cell in the design instantiates
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void CollectInstantiated(Design *design, pool<IdString> &instantiated)
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{
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for(auto mod : design->modules())
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for(auto cell : mod->cells())
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instantiated.insert(cell->type);
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}
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bool HasTopModule(Design *design)
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{
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for(auto mod : design->modules())
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if(mod->get_bool_attribute(ID::top))
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return true;
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return false;
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}
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// A port is used by an instance if some bit of its connection goes anywhere
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// else in the parent module: a public, port or kept wire, a second reference
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// to the same bit, or any wire at all if the parent still contains processes
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void ScanInstances(Design *design, dict<IdString, pool<IdString>> &used_instance_ports, pool<IdString> &positional)
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{
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// Count how often each wire bit is referenced anywhere in the design
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dict<SigBit, int> bit_refs;
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for(auto mod : design->modules())
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{
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for(auto &conn : mod->connections())
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for(auto bit : SigSpec{conn.first, conn.second})
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if(bit.wire != NULL)
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bit_refs[bit]++;
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for(auto cell : mod->cells())
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for(auto &conn : cell->connections())
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for(auto bit : conn.second)
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if(bit.wire != NULL)
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bit_refs[bit]++;
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}
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for(auto mod : design->modules())
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{
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bool has_procs = !mod->processes.empty();
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for(auto cell : mod->cells())
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for(auto &conn : cell->connections())
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{
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if(!conn.first.isPublic())
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positional.insert(cell->type);
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for(auto bit : conn.second)
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{
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if(bit.wire == NULL)
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continue;
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if(has_procs || bit.wire->name.isPublic() || bit.wire->port_input || bit.wire->port_output ||
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bit.wire->get_bool_attribute(ID::keep) || bit_refs.at(bit) > 1)
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{
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used_instance_ports[cell->type].insert(conn.first);
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break;
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}
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}
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}
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}
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}
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void CleanupModule(Module *module, dict<IdString, pool<IdString>> &removed_ports)
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{
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log("Removing now-unused cell ports in module %s\n", module->name);
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@@ -81,7 +175,8 @@ struct RmportsPassPass : public Pass {
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}
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}
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void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports)
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void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports,
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const pool<IdString> &used_instance_ports, bool keep_outputs)
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{
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log("Finding unconnected ports in module %s\n", module->name);
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@@ -142,9 +237,23 @@ struct RmportsPassPass : public Pass {
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pool<IdString> unused_ports;
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for(auto port : module->ports)
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{
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if(used_ports.find(port) != used_ports.end())
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if(used_ports.find(port) == used_ports.end())
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{
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unused_ports.insert(port);
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continue;
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unused_ports.insert(port);
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}
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// An output which no instance of this module uses can be removed
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// even if it is driven internally
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auto wire = module->wire(port);
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if(
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wire->port_output &&
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!wire->port_input &&
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!keep_outputs &&
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used_instance_ports.find(port) == used_instance_ports.end() &&
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!wire->get_bool_attribute(ID::keep)
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)
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unused_ports.insert(port);
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}
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// Print the ports out as we go through them
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@@ -0,0 +1,159 @@
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# rmports: remove output ports which are driven internally but unused by all instances
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# https://github.com/YosysHQ/yosys/issues/1793
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read_verilog <<EOT
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module sub(input a, input z, output x, output y);
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assign x = a;
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assign y = ~a;
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endmodule
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module top(input a, output o);
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sub s(.a(a), .z(), .x(o), .y());
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endmodule
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EOT
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hierarchy -top top
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design -save simple
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select -assert-count 2 sub/o:*
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select -assert-count 2 sub/i:*
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rmports
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hierarchy -check
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select -assert-count 0 sub/o:y
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select -assert-count 1 sub/w:y
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select -assert-count 1 sub/o:*
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select -assert-count 1 sub/i:a
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select -assert-count 1 sub/i:*
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select -assert-count 1 top/o:*
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select -assert-count 1 top/i:*
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# a parent outside the selection is cleaned up as well
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design -load simple
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rmports sub
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select -assert-count 1 sub/o:*
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hierarchy -check
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# an output is kept when any instance uses it
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design -reset
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read_verilog <<EOT
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module sub(input a, output x, output y);
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assign x = a;
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assign y = ~a;
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endmodule
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module top(input a, output o, output p);
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sub s1(.a(a), .x(o), .y());
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sub s2(.a(a), .x(), .y(p));
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endmodule
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EOT
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hierarchy -top top
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rmports
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hierarchy -check
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select -assert-count 2 sub/o:*
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# a cell which is not derived yet names its ports $1, $2, etc
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design -reset
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read_verilog <<EOT
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module sub(input as, output xs, input bs, output ys, input cs);
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assign xs = as & bs;
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assign ys = as ^ cs;
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endmodule
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(* top *)
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module top(input a, input b, output o);
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wire t;
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sub s(a, t, b);
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assign o = t ^ a;
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endmodule
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EOT
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rmports
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hierarchy -check -top top
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select -assert-count 2 sub/o:*
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# a box parent is never selected, but should also be cleaned up
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design -reset
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read_verilog <<EOT
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module sub(input a, output x, output y);
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assign x = a;
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assign y = ~a;
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endmodule
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module mid(input a, output x);
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wire dead;
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sub s(.a(a), .x(x), .y(dead));
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endmodule
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module top(input a, output o);
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mid m(.a(a), .x(o));
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endmodule
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EOT
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hierarchy -top top
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# a public wire counts as a use
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rename -hide mid/w:dead
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setattr -mod -set whitebox 1 mid
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select -clear
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rmports
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select -assert-count 1 sub/o:*
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hierarchy -check
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# no module has the top attribute, so driven outputs stay
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design -reset
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read_verilog <<EOT
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module sub(input a, output x, output y);
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assign x = a;
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assign y = ~a;
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endmodule
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module use1(input a, output o);
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sub s(.a(a), .x(o), .y());
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endmodule
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module use2(input a, output o);
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sub s(.a(a), .x(o), .y());
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endmodule
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EOT
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design -save roots
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rmports
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select -assert-count 2 sub/o:*
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rmports -purge
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hierarchy -check
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select -assert-count 1 sub/o:x
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design -load roots
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delete use2
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rmports
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select -assert-count 2 sub/o:*
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hierarchy -top use1
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rmports
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hierarchy -check
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select -assert-count 1 sub/o:x
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# repro
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design -reset
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read_verilog <<EOT
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module TOP(a, b, y);
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input [3:0] a, b;
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output [2:0] y;
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reg [2:0] tmp;
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wire NC;
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sub p(a, b, {NC, tmp});
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assign y = tmp;
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endmodule
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module sub(as, bs, ys);
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input [3:0] as, bs;
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output [3:0] ys;
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assign ys = as & bs;
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endmodule
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EOT
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hierarchy -top TOP
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delete w:NC
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splitnets -ports
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rmports
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hierarchy -check
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clean -purge
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select -assert-count 3 sub/o:*
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select -assert-count 8 sub/i:*
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select -assert-count 3 TOP/o:*
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select -assert-count 8 TOP/i:*
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