Merge pull request #6263 from YosysHQ/emil/abc_new-unmapped-error-handling

abc_new: improve error handling of &get

frontends/aiger/aigerparse.cc

@@ -400,14 +400,19 @@ void AigerReader::parse_xaiger()
 	if (n0)
 		module->connect(n0, State::S0);
 
+	// Skip the symbol table (present after e.g. '&get -n'); XAIGER wires are positional
+	std::string s;
 	int c = f.get();
+	while (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
+		std::getline(f, s);
+		c = f.get();
+	}
 	if (c != 'c') // 'c'omment section (used for extensions)
 		log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
 	if (f.peek() == '\n')
 		f.get();
 
-	// Parse footer (symbol table, comments, etc.)
-	std::string s;
+	// Parse footer (comments, extensions)
 	for (int c = f.get(); c != EOF; c = f.get()) {
 		// XAIGER extensions
 		if (c == 'm') { // LUT 'm'apping

passes/techmap/abc_new.cc

@@ -196,7 +196,7 @@ struct AbcNewPass : public ScriptPass {
 				run(stringf("  abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
 				run(stringf("  read_aiger -xaiger -module_name %s$abc9 %s/output.aig",
 							modname, tmpdir));
-				run(stringf("  abc_ops_reintegrate -map %s/input.map2", tmpdir));
+				run(stringf("  abc_ops_reintegrate -stdcell -map %s/input.map2", tmpdir));
 				if (!help_mode && mod->has_attribute(ID(abc9_script))) {
 					if (script_save.empty())
 						active_design->scratchpad_unset("abc9.script");

passes/techmap/abc_ops_reintegrate.cc

@@ -45,7 +45,12 @@ struct KeptWire {
 	int offset;
 };
 
-void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
+void unmapped_error(RTLIL::Cell *cell)
+{
+	log_error("ABC returned unmapped node '%s'. Check your abc script.\n", cell);
+}
+
+void reintegrate(RTLIL::Module *module, bool dff_mode, bool stdcell_mode, std::string map_filename)
 {
 	auto design = module->design;
 	log_assert(design);
@@ -348,6 +353,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 		if (mapped_cell->type == ID($_NOT_)) {
 			RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
 			RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
+			if (stdcell_mode && a_bit != State::S0)
+				unmapped_error(mapped_cell);
 			bit_users[a_bit].insert(mapped_cell->name);
 			// Ignore inouts for topo ordering
 			if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
@@ -391,6 +398,9 @@ void reintegrate(RTLIL::Module *module, bool dff_mode, std::string map_filename)
 			continue;
 		}
 
+		if (stdcell_mode && mapped_cell->type.in(ID($lut), ID($_AND_)))
+			unmapped_error(mapped_cell);
+
 		if (mapped_cell->type == ID($lut) || mapped_cell->get_bool_attribute(ID::abc9_cell)) {
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = mapped_cell->parameters;
@@ -718,12 +728,17 @@ struct AbcOpsReintegratePass : public Pass {
 		log("    -map <filename>\n");
 		log("        read file with port and latch symbols\n");
 		log("\n");
+		log("    -stdcell\n");
+		log("        expect a result mapped to standard cells. AIG nodes and LUTs in the\n");
+		log("        result are an error.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).\n");
 
 		bool dff_mode = false;
+		bool stdcell_mode = false;
 		std::string map_filename;
 
 		size_t argidx;
@@ -733,6 +748,10 @@ struct AbcOpsReintegratePass : public Pass {
 				dff_mode = true;
 				continue;
 			}
+			if (arg == "-stdcell") {
+				stdcell_mode = true;
+				continue;
+			}
 			if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
 				map_filename = args[++argidx];
 				continue;
@@ -749,7 +768,7 @@ struct AbcOpsReintegratePass : public Pass {
 			if (!design->selected_whole_module(mod))
 				log_error("Can't handle partially selected module %s!\n", mod);
 
-			reintegrate(mod, dff_mode, map_filename);
+			reintegrate(mod, dff_mode, stdcell_mode, map_filename);
 		}
 	}
 } AbcOpsReintegratePass;

tests/abc_new/classic_map.ys

@@ -0,0 +1,15 @@
+# https://github.com/YosysHQ/yosys/issues/6235
+# '&get' loses the mapping
+read_verilog <<EOT
+module top(input [7:0] a, b, input [2:0] s, output [7:0] y);
+	assign y = (a << s) | (b >> s);
+endmodule
+EOT
+
+hierarchy -top top
+proc
+techmap
+opt
+
+logger -expect error "ABC returned unmapped node" 1
+abc_new -liberty openroad/cm_test_cells.lib -script +&put;strash;map;&get