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https://github.com/YosysHQ/yosys.git
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Revert.
This commit is contained in:
nella
nella
@@ -83,7 +83,6 @@ pmgen_command(peepopt
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peepopt_shiftpow2.pmg
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peepopt_muldiv.pmg
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peepopt_muldiv_c.pmg
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peepopt_muladd.pmg
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peepopt_formal_clockgateff.pmg
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PREFIX
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peepopt
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@@ -29,80 +29,6 @@ bool did_something;
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// scratchpad configurations for pmgen
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int shiftadd_max_ratio;
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pool<SigBit> muladd_keep_bits, muladd_mul_bits;
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int muladd_min_product_width;
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int muladd_max_chain_depth;
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struct MuladdLevel {
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Cell *adder;
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IdString port;
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SigSpec product;
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};
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IdString muladd_other_port(IdString name)
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{
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return name == ID::A ? ID::B : ID::A;
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}
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IdString muladd_width_param(IdString name)
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{
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return name == ID::A ? ID::A_WIDTH : ID::B_WIDTH;
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}
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bool muladd_is_product(Cell *cell)
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{
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if (cell == nullptr || cell->type != ID($mul))
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return false;
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int operand_width = GetSize(cell->getPort(ID::A)) + GetSize(cell->getPort(ID::B));
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return operand_width >= muladd_min_product_width;
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}
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bool muladd_holds_product(const SigSpec &sig)
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{
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for (auto bit : sig)
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if (muladd_mul_bits.count(bit))
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return true;
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return false;
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}
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bool muladd_signal_kept(const SigSpec &sig)
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{
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for (auto bit : sig)
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if (muladd_keep_bits.count(bit))
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return true;
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return false;
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}
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bool muladd_signals_overlap(const SigSpec &lhs, const SigSpec &rhs)
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{
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pool<SigBit> lhs_bits(lhs.begin(), lhs.end());
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for (auto bit : rhs)
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if (lhs_bits.count(bit))
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return true;
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return false;
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}
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// reassociating is only exact when both hold
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bool muladd_levels_compatible(Cell *upper, Cell *lower)
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{
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if (upper->getParam(ID::Y_WIDTH).as_int() > lower->getParam(ID::Y_WIDTH).as_int())
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return false;
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// the parameter is a bool of any width
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return lower->getParam(ID::A_SIGNED).as_bool() == upper->getParam(ID::A_SIGNED).as_bool();
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}
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void muladd_rotate(Cell *outer, IdString outer_port, const vector<MuladdLevel> &levels, const SigSpec &addend)
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{
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outer->setPort(outer_port, levels.front().product);
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outer->setParam(muladd_width_param(outer_port), GetSize(levels.front().product));
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for (int i = 0; i < GetSize(levels); i++) {
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SigSpec moved = i + 1 < GetSize(levels) ? levels[i + 1].product : addend;
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levels[i].adder->setPort(levels[i].port, moved);
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levels[i].adder->setParam(muladd_width_param(levels[i].port), GetSize(moved));
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}
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}
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// Helper function, removes LSB 0s
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SigSpec remove_bottom_padding(SigSpec sig)
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{
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@@ -113,20 +39,6 @@ SigSpec remove_bottom_padding(SigSpec sig)
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#include "passes/opt/peepopt_pm.h"
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void collect_muladd_bits(peepopt_pm &pm)
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{
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muladd_keep_bits.clear();
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muladd_mul_bits.clear();
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for (auto wire : pm.module->wires())
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if (wire->get_bool_attribute(ID::keep))
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for (auto bit : pm.sigmap(wire))
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muladd_keep_bits.insert(bit);
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for (auto cell : pm.module->cells())
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if (cell->type == ID($mul))
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for (auto bit : pm.sigmap(cell->getPort(ID::Y)))
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muladd_mul_bits.insert(bit);
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}
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struct PeepoptPass : public Pass {
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PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }
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void help() override
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@@ -162,13 +74,6 @@ struct PeepoptPass : public Pass {
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log(" Scratchpad: 'peepopt.shiftpow2.max_data_multiple' (default: 2)\n");
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log(" limits padding for out-of-range select values.\n");
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log("\n");
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log(" * muladd - Replace ((P+A*B)+C*D)+E with ((P+E)+A*B)+C*D, so that DSP\n");
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log(" inference can give both multipliers a post-adder.\n");
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log(" Scratchpad: 'peepopt.muladd.min_product_width' (default: 11)\n");
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log(" is the smallest A_WIDTH+B_WIDTH that counts as a product.\n");
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log(" Scratchpad: 'peepopt.muladd.max_chain_depth' (default: 64,\n");
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log(" max 256) limits how far the operand is sunk.\n");
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log("\n");
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log("If -formalclk is specified it instead employs the following rules:\n");
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log("\n");
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log(" * clockgateff - Replace latch based clock gating patterns with a flip-flop\n");
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@@ -198,12 +103,6 @@ struct PeepoptPass : public Pass {
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// 2x implies there is a constant shift larger than the input-data which should be extremely rare
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shiftadd_max_ratio = design->scratchpad_get_int("peepopt.shiftadd.max_data_multiple", 2);
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// 11 is the A_WIDTH+B_WIDTH ice40_dsp asks for
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muladd_min_product_width = design->scratchpad_get_int("peepopt.muladd.min_product_width", 11);
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muladd_max_chain_depth = design->scratchpad_get_int("peepopt.muladd.max_chain_depth", 64);
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// the walk recurses per level, so an unbounded setting overflows the stack
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muladd_max_chain_depth = std::min(muladd_max_chain_depth, 256);
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for (auto module : design->selected_modules())
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{
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did_something = true;
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@@ -225,10 +124,6 @@ struct PeepoptPass : public Pass {
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pm.run_shiftpow2();
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pm.run_muldiv();
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pm.run_muldiv_c();
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if (!did_something) {
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collect_muladd_bits(pm);
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pm.run_muladd();
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}
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}
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}
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}
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@@ -1,132 +0,0 @@
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// Sink a non-product operand to the bottom of an $add chain, lifting every
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// product one adder up: ((P + M1) + M2) + C -> ((P + C) + M1) + M2
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pattern muladd
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udata <vector<MuladdLevel>> chain
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state <IdString> innerAB outerAB walkPort nextPort
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state <SigSpec> sigC
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state <Cell*> walkAdder
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match mul
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select mul->type == $mul
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// the product must feed the adder and nothing else
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select nusers(port(mul, \Y)) == 2
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select muladd_is_product(mul)
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endmatch
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match inner
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select inner->type == $add
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select nusers(port(inner, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(inner, AB) === port(mul, \Y)
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set innerAB AB
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endmatch
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match outer
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select outer->type == $add
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(outer, AB) === port(inner, \Y)
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filter outer != inner
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filter muladd_levels_compatible(outer, inner)
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set outerAB AB
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set sigC port(outer, AB == \A ? \B : \A)
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endmatch
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code walkAdder walkPort
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{
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if (muladd_holds_product(sigC))
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reject;
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if (!module->processes.empty())
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reject;
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chain.clear();
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walkAdder = inner;
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walkPort = innerAB;
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subpattern(walk);
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reject;
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}
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endcode
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subpattern walk
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arg walkAdder walkPort outer outerAB sigC
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code
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{
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if (muladd_signal_kept(port(walkAdder, \Y)))
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reject;
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if (muladd_signals_overlap(sigC, port(walkAdder, \Y)))
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reject;
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for (auto &level : chain)
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if (level.adder == walkAdder)
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reject;
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if (GetSize(chain) >= muladd_max_chain_depth)
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reject;
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}
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endcode
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code
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{
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chain.push_back({walkAdder, walkPort, port(walkAdder, walkPort)});
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}
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finally
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chain.pop_back();
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endcode
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// the product that ends the chain
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match bottom
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select bottom->type == $mul
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select muladd_is_product(bottom)
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index <SigSpec> port(bottom, \Y) === port(walkAdder, muladd_other_port(walkPort))
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semioptional
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endmatch
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code
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{
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if (bottom) {
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did_something = true;
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log("muladd pattern in %s: %s sinks past %d adder(s)\n", module, log_signal(sigC), GetSize(chain));
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muladd_rotate(outer, muladd_other_port(outerAB), chain, sigC);
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blacklist(outer);
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for (auto &level : chain)
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blacklist(level.adder);
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accept;
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}
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}
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endcode
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// else the next adder down
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match below
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if !bottom
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select below->type == $add
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select nusers(port(below, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(below, \Y) === port(walkAdder, muladd_other_port(walkPort))
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filter muladd_levels_compatible(walkAdder, below)
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set nextPort AB
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endmatch
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match belowmul
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if below
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select belowmul->type == $mul
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select nusers(port(belowmul, \Y)) == 2
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select muladd_is_product(belowmul)
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index <SigSpec> port(belowmul, \Y) === port(below, nextPort)
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endmatch
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code walkAdder walkPort
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{
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if (below == nullptr)
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reject;
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walkAdder = below;
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walkPort = nextPort;
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subpattern(walk);
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reject;
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}
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endcode
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@@ -119,7 +119,6 @@ code
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autoremove(div);
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// Log, fixup, accept
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did_something = true;
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log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div);
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mul->fixup_parameters();
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accept;
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@@ -1,49 +0,0 @@
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read_verilog <<EOT
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module top(
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input clk,
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input signed [5:0] px, py, tx, a, b,
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output reg signed [11:0] out
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);
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reg signed [5:0] tx_r;
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always @(posedge clk)
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tx_r <= tx;
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always @(posedge clk)
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out <= px * a + py * b + tx_r;
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endmodule
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module top2(
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input clk,
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input signed [15:0] pretranslate_x, pretranslate_y, translate_x, a, b,
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output reg [23:0] out
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);
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reg signed [15:0] translate_x_r;
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always @(posedge clk)
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translate_x_r <= translate_x;
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always @(posedge clk)
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out <= pretranslate_x * a + pretranslate_y * b + translate_x_r;
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endmodule
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EOT
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proc
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design -save read
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hierarchy -top top
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equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp
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clk2fflogic
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter
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design -load postopt
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cd top
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select -assert-count 2 t:SB_MAC16
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select -assert-none t:SB_MAC16 %% t:* %D
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design -load read
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hierarchy -top top2
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synth_ice40 -dsp
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cd top2
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select -assert-count 2 t:SB_MAC16
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select -assert-none t:SB_MAC16 %% t:* %D
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@@ -1,82 +0,0 @@
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read_verilog <<EOT
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module top(input signed [7:0] a, b, c, d, input signed [15:0] e, output signed [15:0] y);
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assign y = a*b + c*d + e;
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endmodule
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EOT
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prep -top top
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# both products share one adder
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select -assert-count 1 t:$mul %co2 t:$add %i
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 2 t:$mul %co2 t:$add %i
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design -reset
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read_verilog <<EOT
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module top(input [7:0] a, b, c, d, f, g, input [15:0] e, output [15:0] y);
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assign y = e + (a*b + c*d + f*g);
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endmodule
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EOT
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prep -top top
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 3 t:$mul %co2 t:$add %i
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design -reset
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# Reject patterns
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read_verilog <<EOT
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module sumfanout(input signed [7:0] a, b, c, d, input signed [15:0] e, output signed [15:0] y, z);
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wire signed [15:0] t = a*b + c*d; assign y = t + e, z = t;
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endmodule
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// the kept wire only aliases the partial sum, so the rule has to map it first
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module keptalias(input signed [7:0] a, b, c, d, input signed [15:0] e, output signed [15:0] y);
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wire signed [15:0] t = a*b + c*d;
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(* keep *) wire signed [15:0] probe; assign probe = t, y = t + e;
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endmodule
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// $add takes one signedness for both operands, so the operands cannot swap
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module signedness(input signed [7:0] x, a, b, input [7:0] c, output [15:0] y);
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wire [15:0] t = x + a*b; assign y = t + c;
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endmodule
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// the partial sum is truncated and re-extended, so the sum really would change
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module truncated(input signed [7:0] a, b, c, d, input signed [15:0] e, output signed [15:0] y);
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wire signed [9:0] t = a*b + c*d; assign y = t + e;
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endmodule
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// moving the second copy into the inner adder would feed it from its own output
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module sumtwice(input [7:0] x, a, b, output [7:0] y);
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wire [7:0] t = x + a*b; assign y = t + t;
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endmodule
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// the chain has no top, so the product would travel around it forever
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module combcycle(input signed [7:0] a, b, input signed [15:0] e, output signed [15:0] o);
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wire signed [15:0] t1, t2; assign t1 = t2 + a*b, t2 = t1 + e, o = t1;
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endmodule
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// swapping two products
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module allproducts(input signed [7:0] a, b, c, d, f, g, output signed [15:0] y);
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assign y = a*b + c*d + f*g;
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endmodule
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EOT
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opt_clean
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peepopt
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cd sumfanout; select -assert-count 1 t:$mul %co2 t:$add %i; cd ..
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cd keptalias; select -assert-count 1 t:$mul %co2 t:$add %i; cd ..
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cd signedness; select -assert-count 1 t:$mul %co2 t:$add %i; cd ..
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cd truncated; select -assert-count 1 t:$mul %co2 t:$add %i; cd ..
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cd sumtwice; select -assert-count 1 t:$mul %co2 t:$add %i; cd ..
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cd combcycle; select -assert-count 1 t:$mul %co2 t:$add %i; cd ..
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cd allproducts; select -assert-count 2 t:$mul %co2 t:$add %i; cd ..
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design -reset
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read_verilog <<EOT
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module top(input [11:0] a, c, d, input [31:0] e, output [31:0] y);
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wire [31:0] q = (a * 16'd5140) / (257 * 2);
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assign y = q + c*d + e;
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endmodule
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EOT
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hierarchy -top top
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peepopt
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clean
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select -assert-count 2 t:$mul %co2 t:$add %i
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design -reset
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