Repro option accumulation.

tests/abc_new/dup_inv.lib

@@ -0,0 +1,21 @@
+/* https://github.com/YosysHQ/yosys/issues/5445 */
+library(demo) {
+  cell(INV) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "!A"; }
+  }
+  cell(DFFRQN) {
+    area: 18;
+    ff(IQN, IQNN) { clocked_on: "CK";
+                    next_state: "!D";
+                    preset : "!RN"; }
+    pin(CK) { direction: input;
+                 clock: true; }
+    pin(D)  { direction: input; }
+    pin(RN) { direction: input; }
+    pin(QN) { direction: output;
+              function: "IQN"; }
+  }
+}

tests/abc_new/duplicate_cell_libs.ys

@@ -0,0 +1,13 @@
+# https://github.com/YosysHQ/yosys/issues/4977
+
+# same cell name in two liberty files: abc asserts, should be an error (#4977)
+read_verilog <<EOT
+module top(input a, b, output y);
+	assign y = ~(a & b);
+endmodule
+EOT
+
+hierarchy -top top
+techmap
+abc_new -liberty openroad/cm_test_cells.lib -liberty dup_inv.lib
+select -assert-none t:$_*_

tests/abc_new/twice.ys

@@ -0,0 +1,12 @@
+# abc_exe_options is only appended to: a second abc_new call (or -run staging) passes every option twice, the duplicated liberty makes abc abort
+read_verilog <<EOT
+module top(input a, b, output y);
+	assign y = a & b;
+endmodule
+EOT
+
+hierarchy -top top
+techmap
+abc_new -liberty openroad/cm_test_cells.lib
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-none t:$_*_