Merge pull request #6238 from YosysHQ/nella/shiftadd-signed-a

Materialize A sign extension in shiftadd [sc-924]
This commit is contained in:
nella
2026-09-30 13:40:11 +00:00
committed by GitHub
2 changed files with 78 additions and 0 deletions
+8
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@@ -110,6 +110,12 @@ code
reject;
}
// $shr and $shift sign-extend A to max(A_WIDTH, Y_WIDTH), so bake that in
// before reslicing A and clear A_SIGNED, or it gets applied twice
bool a_signed = shift->type.in($shr, $shift) && param(shift, \A_SIGNED).as_bool();
if (a_signed && !old_a.empty())
old_a.extend_u0(max(GetSize(old_a), GetSize(port(shift, \Y))), true);
did_something = true;
log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
module, shift, add, offset);
@@ -143,6 +149,8 @@ code
shift->setPort(\A, new_a);
shift->setParam(\A_WIDTH, GetSize(new_a));
if (a_signed)
shift->setParam(\A_SIGNED, 0);
shift->setPort(\B, new_b);
shift->setParam(\B_WIDTH, GetSize(new_b));
blacklist(add);
+70
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@@ -245,3 +245,73 @@ design -load postopt
clean
select -assert-count 1 t:$bmux
select -assert-count 0 t:$bmux t:* %D
####################
# shiftadd left an empty A on a signed $shr, which techmap turned into x (#6214)
design -reset
read_verilog <<EOT
module peepopt_shiftadd_6214 (input signed [1:0] in, output Y);
assign Y = !((in >> 2) >> (1 + in[0]));
endmodule
EOT
synth
sat -verify -prove Y 1'b1
####################
# signed $shr sign-extends A to Y_WIDTH, the narrowed A must carry that extension
design -reset
read_verilog <<EOT
module peepopt_shiftadd_signed_shr (input signed [3:0] D, input [1:0] S, output [7:0] Y);
wire signed [7:0] A = D;
assign Y = A >> (S + 1);
endmodule
EOT
prep
# wreduce narrows A below Y_WIDTH
wreduce
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 0 t:$add
####################
# A_WIDTH > Y_WIDTH needs no extension, but A_SIGNED must still be cleared
design -reset
read_rtlil <<EOT
module \t
wire width 4 input 1 signed \A
wire input 2 \S
wire width 2 output 3 \Y
wire width 3 \BS
cell $add \a
parameter \A_SIGNED 0
parameter \B_SIGNED 0
parameter \A_WIDTH 2
parameter \B_WIDTH 1
parameter \Y_WIDTH 3
connect \A 2'11
connect \B \S
connect \Y \BS
end
cell $shr \s
parameter \A_SIGNED 1
parameter \B_SIGNED 0
parameter \A_WIDTH 4
parameter \B_WIDTH 3
parameter \Y_WIDTH 2
connect \A \A
connect \B \BS
connect \Y \Y
end
end
EOT
equiv_opt -assert peepopt
design -load postopt
clean
select -assert-count 0 t:$add