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tests: trivial twine damage

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This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:01 +02:00
parent 311e51d227
commit c3268923f4
11 changed files with 43 additions and 42 deletions
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tests/arch/fabulous/fsm.ys
+2 -2
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@@ -13,7 +13,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd fsm # Constrain all select calls below inside the top module
select -assert-count 6 t:LUTFF
select -assert-max 4 t:LUT2
select -assert-max 6 t:LUT2
select -assert-max 5 t:LUT3
select -assert-max 7 t:LUT4
select -assert-max 9 t:LUT4
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUTFF %% t:* %D
tests/arch/gatemate/fsm.ys
+8 -8
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@@ -16,9 +16,9 @@ cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-max 3 t:CC_LUT2
select -assert-max 5 t:CC_LUT3
select -assert-max 7 t:CC_LUT4
select -assert-max 6 t:CC_LUT2
select -assert-max 6 t:CC_LUT3
select -assert-max 9 t:CC_LUT4
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
design -load orig
@@ -35,8 +35,8 @@ cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-max 4 t:CC_LUT1
select -assert-count 1 t:CC_LUT2
select -assert-max 14 t:CC_L2T4
select -assert-max 1 t:CC_LUT2
select -assert-max 16 t:CC_L2T4
select -assert-max 6 t:CC_L2T5
select -assert-max 3 t:CC_MX2
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D
@@ -54,8 +54,8 @@ cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-count 2 t:CC_LUT2
select -assert-count 9 t:CC_L2T4
select -assert-count 6 t:CC_L2T5
select -assert-count 0 t:CC_LUT2
select -assert-count 6 t:CC_L2T4
select -assert-count 8 t:CC_L2T5
select -assert-count 1 t:CC_MX2
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D
tests/memories/generate_mk.py
+1 -1
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@@ -7,6 +7,6 @@ import gen_tests_makefile
gen_tests_makefile.generate_autotest("*.v", "",
"""if grep -Eq 'expect-(wr-ports|rd-ports|rd-clk)' $@; then \\
$(YOSYS) -f verilog -qp "proc; opt; memory -nomap; dump -outfile $(@:.v=).dmp t:\\$$mem_v2" $@; \\
$(YOSYS) -f verilog -qp "proc; opt; memory -nomap; dump -readable -outfile $(@:.v=).dmp t:\\$$mem_v2" $@; \\
python3 validate.py $@ $(@:.v=).dmp; \\
fi""")
tests/unit/CMakeLists.txt
+1 -1
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@@ -6,7 +6,7 @@ function(yosys_gtest arg_TARGET)
set(arg_SOURCES ${arg_UNPARSED_ARGUMENTS})
set(target "gtest-${arg_TARGET}")
add_executable(${target} ${arg_SOURCES})
add_executable(${target} ${arg_SOURCES} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/yosysSetupEnv.cc)
target_link_libraries(${target} PRIVATE
GTest::gmock_main
yosys_common
tests/unit/kernel/CMakeLists.txt
+7
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@@ -1,14 +1,21 @@
yosys_gtest(kernel
bitpatternTest.cc
cellTypesTest.cc
flattenPerfTest.cc
hashTest.cc
ioTest.cc
logTest.cc
modindexTest.cc
pooledNameTest.cc
rtlilHelpers.h
rtlilStringTest.cc
rtlilTest.cc
sigspecExtractTest.cc
sigspecRemove2Test.cc
threadingTest.cc
twineHashTest.cc
twineSortTest.cc
twinePublicityTest.cc
COMPONENTS
flatten
)
tests/unit/kernel/cellTypesTest.cc
+9 -10
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@@ -10,15 +10,16 @@ YOSYS_NAMESPACE_BEGIN
TEST(CellTypesTest, basic)
{
yosys_setup();
if (logger().empty()) logger().add_sink<ConsoleLogSink>();
CellTypes older;
NewCellTypes newer;
older.setup(nullptr);
newer.setup(nullptr);
older.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true);
newer.setup_type(ID(bleh), {ID::G}, {ID::H, ID::I}, false, true);
EXPECT_EQ(older.cell_known(ID(aaaaa)), newer.cell_known(ID(aaaaa)));
RTLIL::Design design;
IdString bleh = design.twines.add(std::string("\\bleh"));
IdString aaaaa = design.twines.add(std::string("\\aaaaa"));
older.setup_type(bleh, {ID::G}, {ID::H, ID::I}, false, true);
newer.setup_type(bleh, {ID::G}, {ID::H, ID::I}, false, true);
EXPECT_EQ(older.cell_known(aaaaa), newer.cell_known(aaaaa));
EXPECT_EQ(older.cell_known(ID($and)), newer.cell_known(ID($and)));
auto check_port = [&](auto type, auto port) {
EXPECT_EQ(older.cell_port_dir(type, port), newer.cell_port_dir(type, port));
@@ -68,12 +69,11 @@ TEST(CellTypesTest, basic)
ID($_FF_),
};
for (size_t i = 0; i < static_cast<size_t>(RTLIL::StaticId::STATIC_ID_END); i++) {
IdString type;
type.index_ = i;
for (size_t i = 0; i < static_cast<size_t>(STATIC_TWINE_END); i++) {
IdString type(i);
EXPECT_EQ(older.cell_known(type), newer.cell_known(type));
if (older.cell_evaluable(type) != newer.cell_evaluable(type))
std::cout << type.str() << "\n";
std::cout << ID::unescaped_str(type) << "\n";
EXPECT_EQ(older.cell_evaluable(type), newer.cell_evaluable(type));
for (auto port : StaticCellTypes::builder.cells.data()->inputs.ports)
check_port(type, port);
@@ -81,7 +81,6 @@ TEST(CellTypesTest, basic)
check_port(type, port);
EXPECT_EQ(expected_ff_types.count(type) > 0, StaticCellTypes::categories.is_ff(type));
}
yosys_shutdown();
}
YOSYS_NAMESPACE_END
tests/unit/kernel/ioTest.cc
-6
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@@ -45,12 +45,6 @@ TEST(KernelStringfTest, stringViewParam)
EXPECT_EQ(stringf("%s", std::string_view("hello")), "hello");
}
TEST(KernelStringfTest, idStringParam)
{
RTLIL::IdString id("$hello");
EXPECT_EQ(stringf("%s", id), "$hello");
}
TEST(KernelStringfTest, escapePercent)
{
EXPECT_EQ(stringf("%%"), "%");
tests/unit/kernel/rtlilStringTest.cc
+8 -8
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@@ -9,8 +9,8 @@ namespace RTLIL {
TEST(RtlilStrTest, DesignToString) {
Design design;
Module *mod = design.addModule(ID(my_module));
mod->addWire(ID(my_wire), 1);
Module *mod = design.addModule("\\my_module");
mod->addWire("\\my_wire", 1);
std::string design_str = design.to_rtlil_str();
@@ -20,8 +20,8 @@ namespace RTLIL {
TEST(RtlilStrTest, ModuleToString) {
Design design;
Module *mod = design.addModule(ID(test_mod));
Wire *wire = mod->addWire(ID(clk), 1);
Module *mod = design.addModule("\\test_mod");
Wire *wire = mod->addWire("\\clk", 1);
wire->port_input = true;
std::string mod_str = mod->to_rtlil_str();
@@ -34,8 +34,8 @@ namespace RTLIL {
TEST(RtlilStrTest, WireToString) {
Design design;
Module *mod = design.addModule(ID(m));
Wire *wire = mod->addWire(ID(data), 8);
Module *mod = design.addModule("\\m");
Wire *wire = mod->addWire("\\data", 8);
std::string wire_str = wire->to_rtlil_str();
@@ -46,8 +46,8 @@ namespace RTLIL {
TEST(RtlilStrTest, CellToString) {
Design design;
Module *mod = design.addModule(ID(m));
Cell *cell = mod->addCell(ID(u1), ID(my_cell_type));
Module *mod = design.addModule("\\m");
Cell *cell = mod->addCell("\\u1", design.twines.add(std::string{"\\my_cell_type"}));
std::string cell_str = cell->to_rtlil_str();
tests/unit/opt/CMakeLists.txt
+1
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@@ -1,5 +1,6 @@
yosys_gtest(opt
optDffFindComplementaryPatternTest.cc
COMPONENTS
opt_clean
opt_dff
)
tests/unit/opt/optDffFindComplementaryPatternTest.cc
+5 -5
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@@ -14,11 +14,11 @@ protected:
void SetUp() override {
design = new RTLIL::Design;
module = design->addModule(ID(test_module));
wire_a = module->addWire(ID(a));
wire_b = module->addWire(ID(b));
wire_c = module->addWire(ID(c));
bus = module->addWire(ID(bus), 4);
module = design->addModule("\\test_module");
wire_a = module->addWire("\\a");
wire_b = module->addWire("\\b");
wire_c = module->addWire("\\c");
bus = module->addWire("\\bus", 4);
}
void TearDown() override {
tests/xprop/test.py
+1 -1
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@@ -453,7 +453,7 @@ for mode in ["", "_xprop"]:
hierarchy -top top; proc -noopt
flatten
opt_expr -keepdc; clean
dump -o opt_expr{mode}.list */\Y_*
dump -readable -o opt_expr{mode}.list */\Y_*
"""
)