abc_new: add test for &get error handling

2026-10-06 10:03:36 +02:00 · 2026-09-30 12:19:21 +02:00
parent 49f45cf21f
commit a51ed0614c
1 changed files with 15 additions and 0 deletions
@@ -0,0 +1,15 @@
+# https://github.com/YosysHQ/yosys/issues/6235
+# '&get' loses the mapping
+read_verilog <<EOT
+module top(input [7:0] a, b, input [2:0] s, output [7:0] y);
+	assign y = (a << s) | (b >> s);
+endmodule
+EOT
+
+hierarchy -top top
+proc
+techmap
+opt
+
+logger -expect error "ABC returned unmapped node" 1
+abc_new -liberty openroad/cm_test_cells.lib -script +&put;strash;map;&get