Port OpenROAD cut tests.

tests/abc_new/openroad/liberty_boxes.ys

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+# https://github.com/The-OpenROAD-Project/OpenROAD/blob/80443953721b0134bed51bbab17a633a575098a6/src/cut/test/side_outputs_extract.v
+
+# This test makes sure that we keep track of any outputs that aren't directly
+# on the logic cone, but are driven by cell that are. If we were to destory these
+# cells we need to make sure any pins they drive are primary outputs in ABC to
+# preserve correctness.
+read_verilog <<EOT
+module top(clk, a, b, c, d);
+	input clk;
+	input a;
+	input b;
+	output c;
+	output d;
+
+	wire flop_net;
+
+	AND2 _403_ (
+		.A(a),
+		.B(b),
+		.Y(flop_net)
+	);
+
+	DFF output_flop (
+		.CLK(clk),
+		.D(flop_net),
+		.Q(c)
+	);
+
+	DFF output_flop2 (
+		.CLK(clk),
+		.D(flop_net),
+		.Q(d)
+	);
+
+endmodule
+EOT
+
+read_liberty -lib -unit_delay cm_test_cells.lib
+read_liberty -lib -unit_delay sm_test_cells.lib
+hierarchy -top top
+abc_new -liberty cm_test_cells.lib -liberty sm_test_cells.lib
+select -assert-count 1 t:AND2
+select -assert-count 2 t:DFF
+select -assert-count 3 t:*
+check -assert

tests/abc_new/openroad/liberty_boxes_empty.ys

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+# https://github.com/The-OpenROAD-Project/OpenROAD/blob/80443953721b0134bed51bbab17a633a575098a6/src/cut/test/empty_cut_set.v
+
+# flop only, empty cut
+read_verilog <<EOT
+module top(clk, a, b);
+	input clk;
+	input a;
+	output b;
+
+	DFF output_flop (
+		.CLK(clk),
+		.D(a),
+		.Q(b)
+	);
+
+endmodule
+EOT
+
+read_liberty -lib -unit_delay cm_test_cells.lib
+read_liberty -lib -unit_delay sm_test_cells.lib
+hierarchy -top top
+abc_new -liberty cm_test_cells.lib -liberty sm_test_cells.lib
+select -assert-count 1 t:DFF
+select -assert-count 1 t:*
+check -assert

tests/abc_new/openroad/remap_netlist.ys

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+# https://github.com/The-OpenROAD-Project/OpenROAD/blob/80443953721b0134bed51bbab17a633a575098a6/src/cut/test/side_outputs_extract_logic_depth.v
+
+# This test makes sure that we keep track of any outputs that aren't directly
+# on the logic cone, but are driven by cell that are. If we were to destroy these
+# cells we need to make sure any pins they drive are primary outputs in ABC to
+# preserve correctness.
+read_verilog <<EOT
+module top(clk, a, b, c, d);
+	input clk;
+	input a;
+	input b;
+	output c;
+	output d;
+
+	wire flop_net;
+	wire inv_net;
+
+	AND2 _403_ (
+		.A(a),
+		.B(b),
+		.Y(flop_net)
+	);
+
+	INV _404_ (
+		.A(flop_net),
+		.Y(inv_net)
+	);
+
+	DFFR output_flop (
+		.CLK(clk),
+		.D(inv_net),
+		.Q(c),
+		.RST_N(1'b1)
+	);
+
+	DFFR output_flop2 (
+		.CLK(clk),
+		.D(flop_net),
+		.Q(d),
+		.RST_N(1'b1)
+	);
+
+endmodule
+EOT
+
+read_verilog cells_sim.v
+hierarchy -top top
+proc
+flatten
+opt
+hierarchy -top top
+read_liberty -lib sm_test_cells.lib
+design -save gold
+
+synth -run fine:
+select -assert-count 2 t:$_DFF_P_
+abc_new -liberty cm_test_cells.lib
+dfflibmap -liberty sm_test_cells.lib
+opt_clean
+select -assert-none t:$_*_
+select -assert-count 2 t:DFF
+check -assert
+
+read_verilog cells_sim.v
+proc
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+async2sync
+equiv_make gold gate equiv
+equiv_simple -seq 5
+equiv_induct -seq 5
+equiv_status -assert

tests/abc_new/partial_box_ports.ys

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+# box instances with unconnected ports (the unused-output instance gets dropped, not asserted)
+read_verilog <<EOT
+module top(input a, b, output y, z);
+	wire t, unused;
+	AND2 g0 (.A(a), .Y(t));
+	OR2 g1 (.A(t), .B(b), .Y(y));
+	XOR2 g2 (.A(a), .B(b), .Y(unused));
+	assign z = t | a;
+endmodule
+EOT
+
+read_liberty -lib -unit_delay openroad/cm_test_cells.lib
+hierarchy -top top
+proc
+opt
+techmap
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-count 1 c:g0
+select -assert-count 1 c:g1
+select -assert-none t:$_*_
+check -assert