Test port corner cases.

tests/abc_new/cells.genlib

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+# genlib twin of openroad/cm_test_cells.lib, same cell names
+GATE TIELO  1 Y=CONST0;
+GATE TIEHI  1 Y=CONST1;
+GATE BUF    2 Y=A;                  PIN * NONINV 1 999 1 0 1 0
+GATE INV    1 Y=!A;                 PIN * INV    1 999 1 0 1 0
+GATE NAND2  2 Y=!(A*B);             PIN * INV    1 999 1 0 1 0
+GATE NOR2   2 Y=!(A+B);             PIN * INV    1 999 1 0 1 0
+GATE XOR2   5 Y=(A*!B)+(!A*B);      PIN * UNKNOWN 1 999 1 0 1 0
+GATE MUX2   7 Y=(A*!S)+(B*S);       PIN * UNKNOWN 1 999 1 0 1 0

tests/abc_new/edge_cases.ys

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+# passthrough, port-to-port, constants, undef on outputs and cone inputs, duplicated bits, dangling logic, undriven inout
+read_verilog <<EOT
+module top(input [3:0] a, input b, unused, inout io, output [3:0] y0, y1, output z0, z1, z2, z3, z4, z5, output [1:0] w);
+	assign y0 = a;
+	assign y1 = y0;
+	assign z0 = 1'b0;
+	assign z1 = 1'b1;
+	assign z2 = 1'bx;
+	assign z3 = b;
+	assign z4 = a[1] & 1'bx;
+	assign z5 = b | 1'bx;
+	assign w = {b, b};
+	wire dangling = a[0] & b;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+design -save gold
+
+techmap
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-none t:$_*_
+check -assert
+
+read_verilog openroad/cells_sim.v
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+miter -equiv -flatten -make_assert -ignore_gold_x gold gate miter
+sat -verify -prove-asserts -show-ports miter

tests/abc_new/genlib_equiv.ys

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+# -genlib
+read_verilog <<EOT
+module top(input [3:0] a, b, input s, output [3:0] y, output z, w);
+	assign y = s ? a ^ b : a & b;
+	assign z = 1'b0;
+	assign w = |a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+design -save gold
+
+techmap
+opt
+abc_new -genlib cells.genlib
+select -assert-none t:$_*_
+select -assert-min 1 t:MUX2
+check -assert
+
+read_verilog openroad/cells_sim.v
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+miter -equiv -flatten -make_assert gold gate miter
+sat -verify -prove-asserts -show-ports miter

tests/abc_new/script_inline.ys

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+# -script +cmd,arg;cmd
+read_verilog <<EOT
+module top(input [7:0] a, b, output [7:0] y, output c);
+	assign {c, y} = a + b;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+design -save gold
+
+techmap
+opt
+logger -expect log "\+ &if -g -K 6" 1
+abc_new -liberty openroad/cm_test_cells.lib -script +&st;&if,-g,-K,6;&nf
+logger -check-expected
+select -assert-none t:$_*_
+check -assert
+
+read_verilog openroad/cells_sim.v
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+miter -equiv -flatten -make_assert gold gate miter
+sat -verify -prove-asserts -show-ports miter

tests/abc_new/wide_ports_equiv.ys

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+# bit permutations across wide ports
+read_verilog <<EOT
+module top(input [15:0] a, input s, output [15:0] y, output [7:0] z);
+	assign y = s ? {a[0], a[15:1]} : {a[7:0], a[15:8]};
+	assign z = a[15:8] ^ a[7:0];
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+design -save gold
+techmap
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-none t:$_*_
+check -assert
+read_verilog openroad/cells_sim.v
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+miter -equiv -flatten -make_assert -ignore_gold_x gold gate miter
+sat -verify -prove-asserts -show-ports miter