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18,160 Commits 135 Branches 68 Tags 55 MiB
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18160 Commits

Author SHA1 Message Date
AdvaySingh1 90aa1cc016 Checked out main passes/techmap/clockgate.cc for source attributes and removed logging 2026-02-27 12:24:31 -08:00
AdvaySingh1 ce95d7cbcf Removed notes.txt 2026-02-27 12:22:29 -08:00
Stan Lee 8ee71ddc7f bugfix 2026-02-27 12:19:14 -08:00
Stan Lee 93af5a5232 in order 2026-02-27 12:17:43 -08:00
Stan Lee c42d2c2d03 support for nested structs 2026-02-27 11:54:43 -08:00
Stan Lee d36e2f7d17 resolve accidental change 2026-02-27 11:40:13 -08:00
Stan Lee 03ce300b49 another indent 2026-02-27 11:29:31 -08:00
Stan Lee fa1267e0cb fix indents 2026-02-27 11:27:37 -08:00
Stan Lee ae3b9b74e2 ready 2026-02-27 11:25:10 -08:00
Stan Lee 48894488f1 better method for assigning fsthandles 2026-02-27 11:25:10 -08:00
Stan Lee 0aaca679ce better but not ideal 2026-02-27 11:25:10 -08:00
Stan Lee 5bdc2d3451 working implementation that i will improvee further 2026-02-27 11:25:10 -08:00
AdvaySingh1 3cee420bf9 Merge branch 'main' into sat_clkgate 2026-02-27 11:15:22 -08:00
tondapusili f46b8d2a44 silimate: add opt_timing_balance pass and tests 2026-02-27 09:13:39 -08:00
Akash Levy 0c663bef4a
Merge pull request #110 from Silimate/negopt_log_flush 
Added log flushes after each negopt pass for clearer logging
 2026-02-26 16:09:34 -08:00
Stan Lee 29a1c69f74 move log flush to better spot 2026-02-26 16:01:37 -08:00
Stan Lee b11eef4fe1 fix bug 2026-02-26 16:00:27 -08:00
tondapusili 2f276d0723 Added log flushes after each negopt pass for clearer logging 2026-02-25 12:15:46 -08:00
Akash Levy 0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr 
Added is_clock_gated attr to flops created via clockgate.cc pass
 2026-02-20 17:02:02 -08:00
Akash Levy c47dd20140
Merge pull request #108 from Silimate/icg_builtin_sim 
Added built in  cell alongside sim support for cell
 2026-02-20 17:01:20 -08:00
AdvaySingh1 ec537b189f Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:50 -08:00
AdvaySingh1 8f5b8cb46c Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
AdvaySingh1 84a03a6b9a Merge branch 'icg_builtin_sim' into sat_clkgate 2026-02-19 11:51:49 -08:00
AdvaySingh1 b29514fafc Added built in cell alongside sim support for cell 2026-02-19 11:48:35 -08:00
AdvaySingh1 d9867fc7c7 Merge branch 'main' into sat_clkgate 2026-02-19 09:43:22 -08:00
AdvaySingh1 5e58bf22e0 Changed param naming for consistancy 2026-02-19 09:42:59 -08:00
Akash Levy 723ddd74cf Improve wreduce runtime 2026-02-19 01:03:26 -08:00
Akash Levy bf4ce9d6f7 Import uniquify fix 2026-02-19 00:24:32 -08:00
Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
Akash Levy 9a30512cff
Merge pull request #107 from Silimate/clkgate_node_retention 
Added node retention
 2026-02-18 18:17:27 -08:00
AdvaySingh1 5769cdbea8 Added node retention 2026-02-18 16:05:56 -08:00
AdvaySingh1 d84e56ecac Added naming for the new icg cells 2026-02-18 16:03:34 -08:00
Akash Levy b7098e8383
Merge branch 'YosysHQ:main' into main 2026-02-18 09:44:25 -08:00
AdvaySingh1 ee896b9eee Removed sorting of similar candidate_gates for unnessessary optimization 2026-02-18 09:08:25 -08:00
Gus Smith 29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges 
kernel/celledges: cover more cell types
 2026-02-18 07:50:41 -08:00
Emil J 33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check 
blifparse: add bounds check
 2026-02-18 12:18:05 +01:00
Akash Levy 650c636d39 Fixups 2026-02-18 01:12:35 -08:00
Akash Levy 33c2c88fa4 Bump Yosys to latest from upstream 2026-02-17 23:41:39 -08:00
Akash Levy c04975b78c Remove custom mux opt_exprs 2026-02-17 20:41:29 -08:00
AdvaySingh1 6cb9fadded Removed downstream signals causing equiv_opt failures due to feedback loop 2026-02-17 16:22:59 -08:00
AdvaySingh1 90dbb91cae Changed min cone size 2026-02-17 16:22:05 -08:00
AdvaySingh1 2ab89e1146 Passing equiv_opt pass and speed boosts 2026-02-17 16:13:51 -08:00
AdvaySingh1 c8b6869e65 Removed optimizations from infer_ce.cc for profiling 2026-02-17 15:20:57 -08:00
AdvaySingh1 a8e4fccc56 Removed simulation and isValidGatingSignal function 2026-02-17 14:07:22 -08:00
AdvaySingh1 fa9e7a77d7 Removed normal clockgate pass options form sate_clockgate pass 2026-02-17 13:43:22 -08:00
AdvaySingh1 efcabb270f Added caching of simulation runs for speed 2026-02-17 13:38:32 -08:00
AdvaySingh1 dc4ca2c621 Added TODO for eliminating false paths 2026-02-17 12:42:20 -08:00
AdvaySingh1 499e83a549 Switched to using CE module. Mostly retaining SAT gates. Still needs speedup 2026-02-17 12:41:59 -08:00
AdvaySingh1 e755f6c42e Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime 2026-02-17 12:14:53 -08:00
AdvaySingh1 2212d85626 Changed configurations to match the OpenROAD project 2026-02-17 11:57:56 -08:00