mirror of https://github.com/YosysHQ/yosys.git
Import uniquify fix
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3e9a5c68b1
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bf4ce9d6f7
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@ -257,12 +257,16 @@ bool is_blackbox(Netlist *nl)
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RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
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{
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return module->uniquify(RTLIL::escape_id(obj->Name()));
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RTLIL::IdString base = RTLIL::escape_id(obj->Name());
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int &idx = uniquify_cache[base];
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return module->uniquify(base, idx);
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}
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RTLIL::IdString VerificImporter::new_verific_id_suffix(RTLIL::IdString id, const char *suffix)
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{
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return module->uniquify(stringf("%s_%s", id, suffix));
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RTLIL::IdString base = stringf("%s_%s", id, suffix);
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int &idx = uniquify_cache[base];
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return module->uniquify(base, idx);
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}
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static const RTLIL::Const extract_vhdl_boolean(std::string &val)
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@ -1549,6 +1553,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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module->name = module_name;
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design->add(module);
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uniquify_cache.clear();
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if (is_blackbox(nl)) {
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log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
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log_flush();
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@ -80,6 +80,8 @@ struct VerificImporter
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bool mode_gates, mode_keep, mode_nosva, mode_sva_continue, mode_names, mode_verific;
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bool mode_autocover, mode_fullinit;
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dict<RTLIL::IdString, int> uniquify_cache;
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int num_sva_continue = 0;
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_sva_continue, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit);
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