Version bump

This is a simple debugging aid to allow constraining the graph layout
via GraphViz rank directives. Note this is not related in any way to the
vertex 'rank' attribute used by some of the graph algorithms.

No functional change.

.clang-format

@@ -108,4 +108,3 @@ Standard:        Cpp11
 TabWidth:        8
 UseTab:          Never
 ...
-

.github/ISSUE_TEMPLATE/bug_report.md

@@ -1,6 +1,6 @@
 ---
 name: Bug report
-about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to report that something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -13,4 +13,6 @@ Can you attach an example that shows the issue?  (Must be openly licensed, ideal
 
 What 'verilator --version' are you using?  Did you try it with the git master version?
 
-Would you be willing to try to fix Verilator yourself with assistance?
+What OS and distribution are you using?
+
+May we assist you in trying to fix this in Verilator yourself?

.github/ISSUE_TEMPLATE/feature.md

@@ -1,6 +1,6 @@
 ---
 name: Feature Request
-about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -13,4 +13,4 @@ What would you like added/supported?
 
 Can you attach an example that runs on other simulators?  (Must be openly licensed, ideally in test_regress format.)
 
-May we assist you in trying to fix this yourself?
+May we assist you in trying to fix this in Verilator yourself?

.github/ISSUE_TEMPLATE/questions.md

@@ -1,6 +1,6 @@
 ---
 name: Q and A, or Other
-about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to ask a question, not related to a specific bug nor feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''

.github/workflows/build.yml

@@ -16,128 +16,129 @@ env:
   CI_COMMIT: ${{ github.sha }}
   CCACHE_COMPRESS: 1
   CCACHE_DIR: ${{ github.workspace }}/.ccache
+  CCACHE_LIMIT_MULTIPLE: 0.95
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
 
 jobs:
 
-
-  Matrix:
-    runs-on: ubuntu-latest
-    name: Generate Build matrix
-    outputs:
-      matrix: ${{ steps.generate.outputs.matrix }}
-    steps:
-    - uses: actions/checkout@v2
-    - id: generate
-      name: Run 'generate_matrix.sh'
-      run: |
-        if [ '${{ github.event_name }}' = 'pull_request' ]; then
-          matrix='[ "ubuntu-20.04" ]'
-        else
-          matrix='[ "ubuntu-16.04", "ubuntu-18.04", "ubuntu-20.04" ]'
-        fi
-        echo "::set-output name=matrix::$matrix"
-
-
-  Build:
-    needs: Matrix
+  build:
     strategy:
       fail-fast: false
       matrix:
-        os: ${{ fromJson(needs.Matrix.outputs.matrix) }}
-        debug: [ opt, dbg ]
+        os: [ubuntu-20.04, ubuntu-18.04]
         compiler:
           - { cc: clang, cxx: clang++ }
           - { cc: gcc,   cxx: g++     }
+        m32: [0, 1]
+        exclude:
+          # Build pull requests only with ubuntu-20.04 and without m32
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
+          # Build -m32 only on ubuntu-20.04
+          - {os: ubuntu-18.04, m32: 1}
     runs-on: ${{ matrix.os }}
-    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.debug }}
+    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} ${{ matrix.m32 && '| -m32' || '' }}
     env:
       CI_BUILD_STAGE_NAME: build
       CI_RUNS_ON: ${{ matrix.os }}
-      CI_MAKE_SRC_TARGET: ${{ matrix.debug }}
+      CI_M32: ${{ matrix.m32 }}
       CC: ${{ matrix.compiler.cc }}
       CXX: ${{ matrix.compiler.cxx }}
-      CACHE_KEY: build-${{ matrix.os }}-${{ matrix.compiler.cc }}-${{ matrix.debug }}
-      CCACHE_MAXSIZE: 256Mi # Per build matrix entry
+      CACHE_BASE_KEY: build-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}
+      CCACHE_MAXSIZE: 250M # Per build matrix entry (2000M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
     steps:
 
     - name: Checkout
       uses: actions/checkout@v2
+      with:
+        path: repo
 
-    - name: Cache
+    - name: Cache $CCACHE_DIR
       uses: actions/cache@v2
       env:
-        cache-name: ccache
+        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: ${{ env.CACHE_KEY }}-${{ env.cache-name }}
+        path: ${{ env.CCACHE_DIR }}
+        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+        restore-keys: |
+          ${{ env.CACHE_KEY }}-
 
     - name: Install packages for build
       run: ./ci/ci-install.bash
 
     - name: Build
-      run: |
-        ccache -z
-        ./ci/ci-script.bash
-        ccache -s
-        tar cvzf verilator-${{ matrix.os}}-${CI_COMMIT}-${{ matrix.compiler.cc }}-${{ matrix.debug }}.tgz ./bin
+      run: ./ci/ci-script.bash
 
-    - uses: actions/upload-artifact@v2
+    - name: Tar up repository
+      working-directory: ${{ github.workspace }}
+      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+    - name: Upload tar archive
+      uses: actions/upload-artifact@v2
       with:
-        path: verilator-${{ matrix.os}}-${{ env.CI_COMMIT }}-${{ matrix.compiler.cc }}-${{ matrix.debug }}.tgz
+        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
 
 
-  Test:
-    needs: [ Matrix, Build ]
+  test:
+    needs: build
     strategy:
       fail-fast: false
       matrix:
-        os: ${{ fromJson(needs.Matrix.outputs.matrix) }}
+        os: [ubuntu-20.04, ubuntu-18.04]
         compiler:
           - { cc: clang, cxx: clang++ }
           - { cc: gcc,   cxx: g++     }
-        suite:
-          - dist-vlt-0
-          - dist-vlt-1
-          - dist-vlt-2
-          - vltmt-0
-          - vltmt-1
+        m32: [0, 1]
+        suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, vltmt-0, vltmt-1]
+        exclude:
+          # Build pull requests only with ubuntu-20.04 and without m32
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
+          # Build -m32 only on ubuntu-20.04
+          - {os: ubuntu-18.04, m32: 1}
     runs-on: ${{ matrix.os }}
-    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }}
+    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }} ${{ matrix.m32 && '| -m32' || '' }}
     env:
       CI_BUILD_STAGE_NAME: test
       CI_RUNS_ON: ${{ matrix.os }}
+      CI_M32: ${{ matrix.m32 }}
       CC: ${{ matrix.compiler.cc }}
       CXX: ${{ matrix.compiler.cxx }}
-      CACHE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-${{ matrix.suite }}
-      CCACHE_MAXSIZE: 256Mi # Per build matrix entry
+      CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}-${ matrix.suite }}
+      CCACHE_MAXSIZE: 64M # Per build matrix entry (2160M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
     steps:
 
-    - name: Checkout
-      uses: actions/checkout@v2
+    - name: Download tar archive
+      uses: actions/download-artifact@v2
+      with:
+        name: ${{ env.VERILATOR_ARCHIVE }}
+        path: ${{ github.workspace }}
 
-    - name: Cache
+    - name: Unpack tar archive
+      working-directory: ${{ github.workspace }}
+      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+
+    - name: Cache $CCACHE_DIR
       uses: actions/cache@v2
       env:
-        cache-name: ccache
+        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: ${{ env.CACHE_KEY }}-${{ env.cache-name }}
+        path: ${{ env.CCACHE_DIR }}
+        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+        restore-keys: |
+          ${{ env.CACHE_KEY }}-
 
-    - uses: actions/download-artifact@v2
-
-    - name: Install Verilator and test dependencies
-      run: |
-        tar xvzf artifact/verilator-${{ matrix.os}}-${CI_COMMIT}-${{ matrix.compiler.cc }}-opt.tgz
-        tar xvzf artifact/verilator-${{ matrix.os}}-${CI_COMMIT}-${{ matrix.compiler.cc }}-dbg.tgz
-        rm -rf artifact
-        ./ci/ci-install.bash
+    - name: Install test dependencies
+      run: ./ci/ci-install.bash
 
     - name: Test
       env:
         TESTS: ${{ matrix.suite }}
-      run: |
-        ccache -z
-        ./ci/ci-script.bash
-        ccache -s
+      run: ./ci/ci-script.bash

.github/workflows/coverage.yml

@@ -11,9 +11,14 @@ on:
 env:
   CI_OS_NAME: linux
   CI_COMMIT: ${{ github.sha }}
-  CCACHE_COMPRESS: 1
-  CCACHE_DIR: ${{ github.workspace }}/.ccache
+  CI_M32: 0
   COVERAGE: 1
+  VERILATOR_ARCHIVE: verilator-coverage-${{ github.sha }}.tar.gz
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
 
 jobs:
 
@@ -23,37 +28,28 @@ jobs:
     env:
       CI_BUILD_STAGE_NAME: build
       CI_RUNS_ON: ubuntu-20.04
-      CACHE_KEY: coverage-build
-      CCACHE_MAXSIZE: 512Mi
     steps:
 
     - name: Checkout
       uses: actions/checkout@v2
-
-    - name: Cache
-      uses: actions/cache@v2
-      env:
-        cache-name: ccache
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: ${{ env.CACHE_KEY }}-${{ env.cache-name }}
+        path: repo
 
     - name: Install packages for build
-      env:
-        CI_BUILD_STAGE_NAME: build
       run: ./ci/ci-install.bash
 
     - name: Build
-      run: |
-        ccache -z
-        ./ci/ci-script.bash
-        ccache -s
-        tar cvzf verilator-${CI_COMMIT}-coverage.tgz bin src/obj*/*.o src/obj*/*.gcno
+      run: ./ci/ci-script.bash
 
-    - uses: actions/upload-artifact@v2
+    - name: Tar up repository
+      working-directory: ${{ github.workspace }}
+      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+    - name: Upload tar archive
+      uses: actions/upload-artifact@v2
       with:
-        path: verilator-${{ env.CI_COMMIT }}-coverage.tgz
+        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
 
 
   Test:
@@ -82,34 +78,22 @@ jobs:
     env:
       CI_BUILD_STAGE_NAME: test
       CI_RUNS_ON: ubuntu-20.04
-      CACHE_KEY: coverage-test-${{ matrix.test }}${{ matrix.num }}
-      CCACHE_MAXSIZE: 512Mi # Per build matrix entry
     steps:
 
-    - name: Checkout
-      uses: actions/checkout@v2
-
-    - name: Cache
-      uses: actions/cache@v2
-      env:
-        cache-name: ccache
+    - name: Download tar archive
+      uses: actions/download-artifact@v2
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: ${{ env.CACHE_KEY }}-${{ env.cache-name }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
+        path: ${{ github.workspace }}
 
-    - uses: actions/download-artifact@v2
+    - name: Unpack tar archive
+      working-directory: ${{ github.workspace }}
+      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
 
-    - name: Install Verilator and test dependencies
-      run: |
-        tar xvzf artifact/verilator-${CI_COMMIT}-coverage.tgz
-        touch src/obj*/*.o src/obj*/*.gcno
-        ./ci/ci-install.bash
+    - name: Install test dependencies
+      run: ./ci/ci-install.bash
 
     - name: Test
       env:
         TESTS: coverage-${{ matrix.test }}${{ matrix.num }}
-      run: |
-        ccache -z
-        ./ci/ci-script.bash
-        ccache -s
+      run: ./ci/ci-script.bash

.github/workflows/format.yml

@@ -16,6 +16,7 @@ jobs:
       CI_OS_NAME: linux
       CI_RUNS_ON: ubuntu-20.04
       CI_COMMIT: ${{ github.sha }}
+      CI_M32: 0
     steps:
       - name: Checkout
         uses: actions/checkout@v2
@@ -26,14 +27,14 @@ jobs:
           CI_BUILD_STAGE_NAME: build
         run: |
           bash ci/ci-install.bash &&
-          sudo apt-get install clang-10 yapf3 &&
+          sudo apt-get install clang-format-11 yapf3 &&
           git config --global user.email "[email protected]" &&
           git config --global user.name "github action"
       - name: Format code
         run: |
           autoconf &&
           ./configure &&
-          make -j 2 format CLANGFORMAT=clang-format-10 &&
+          make -j 2 format CLANGFORMAT=clang-format-11 &&
           git status
       - name: Push
         run: |

.gitignore

@@ -39,3 +39,4 @@ verilator-config-version.cmake
 **/__pycache__/*
 **/_build/*
 **/obj_dir/*
+/.vscode/

CPPLINT.cfg

@@ -0,0 +1,17 @@
+set noparent
+linelength=100
+filter=-build/c++11
+filter=-build/header_guard
+filter=-build/include_order
+filter=-build/include_subdir
+filter=-readability/inheritance
+filter=-readability/nolint
+filter=-readability/todo
+filter=-runtime/references
+filter=-whitespace/blank_line
+filter=-whitespace/empty_if_body
+filter=-whitespace/indent
+filter=-whitespace/newline
+filter=-whitespace/braces
+filter=-whitespace/parens
+filter=-whitespace/todo

Changes

@@ -8,6 +8,207 @@ The changes in each Verilator version are described below.  The
 contributors that suggested a given feature are shown in []. Thanks!
 
 
+Verilator 4.222 2022-05-02
+==========================
+
+**Minor:**
+
+* Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD]
+* Deprecate 'vluint64_t' and similar types (#3255).
+* Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD]
+* Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD]
+* Support LoongArch ISA multithreading (#3353) (#3354). [Xi Zhang]
+* Fix MSVC localtime_s (#3124).
+* Fix Bison 3.8.2 error (#3366). [elike-ypq]
+* Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD]
+* Fix tracing interfaces inside interfaces (#3309). [Kevin Millis]
+* Fix filenames with dots overwriting debug .vpp files (#3373).
+* Fix including VK_USER_OBJS in make library (#3370) (#3382). [Julien Margetts]
+* Fix hang in generate symbol references (#3391) (#3398). [Yoda Lee]
+* Fix missing #include <memory> (#3392). [Aliaksei Chapyzhenka]
+* Fix crash in recursive module inlining (#3393). [david-sawatzke]
+* Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD]
+* Fix foreach segmentation fault (#3400). [Kamil Rakoczy]
+
+
+Verilator 4.220 2022-03-12
+==========================
+
+**Minor:**
+
+* Removed the deprecated lint_off flag -msg; use -rule instead.
+* Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
+* Suppress WIDTH warning on negate using carry bit (#3295). [Peter Monsson]
+* Add trace dumpvars() call for selective runtime tracing (#3322). [Shunyao CAD]
+* Add VERILATOR_VERSION_INTEGER for determining API (#3343). [Larry Doolittle]
+* Improve various V3Combine algorithm details (#3328). [Yutetsu TAKATSUKASA]
+* Improve various V3Order algorithm details. [Geza Lore]
+* Fix macOS arm64 build (#3285) (#3291). [Guokai Chen]
+* Fix signed number operation (#3294) (#3308). [Raynard Qiao]
+* Fix FST traces to include vector range (#3296) (#3297). [Jamie Iles]
+* Fix skipping public enum values with four-state values (#3303).
+* Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman]
+* Fix class stringification on wide arrays (#3312). [Iru Cai]
+* Fix $fscanf etc to return -1 on EOF (#3313). [Jose Tejada]
+* Fix public function arguments that are arrayed (#3316). [pawel256]
+* Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka]
+* Fix crash in recursive module inlining (#3324). [Larry Doolittle]
+* Fix VL_RESTORER behavior on passing a lvalue reference (#3326). [HungMingWu]
+* Fix compile error with --trace-fst --sc (#3332). [leavinel]
+* Fix cast to array types (#3333). [Todd Strader]
+* Fix Vdeeptemp error with --threads and --compiler clang (#3338). [Per Karlsson]
+
+
+Verilator 4.218 2022-01-17
+==========================
+
+**Major:**
+
+* Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type.
+  In general this should be backward compatible, but may lead to some
+  wrapper code needing changes.
+* Option --cdc is deprecated and is planned for removal,
+  file a bug if this is still being used.
+
+**Minor:**
+
+* Support class static members (#2233).
+* Support force/release (#2431) (#2593). [Shunyao CAD]
+* Add 'forceable' attribute to allow forcing from C++. (#3272). [Geza Lore, Shunyao CAD]
+* Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim]
+* Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman]
+* Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD]
+* Support FST tracing in hierarchical Verilation (#3251). [Yutetsu TAKATSUKASA]
+* Use C++11 standard types for MacOS portability (#3254) (#3257). [Adrien Le Masle]
+* Fix make support for BSD ar (#2999) (#3256). [Julie Schwartz]
+* Fix bad ending address on $readmem (#3205). [Julie Schwartz]
+* Fix MSWIN compile error (#2681). [Unai Martinez-Corral]
+* Fix break under foreach loop (#3230).
+* Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235). [Adrien Le Masle]
+* Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle]
+* Fix associative array first method as statement (#3228). [Adrien Le Masle]
+* Fix associative array foreach loop (#3229).
+* Fix $fclose not accepting expressions (#3237). [Julie Schwartz]
+* Fix $random not updating seed (#3238). [Julie Schwartz]
+* Fix top level param overwrite when package has same param (#3241) (#3247). [Adrien Le Masle]
+* Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz]
+* Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD]
+* Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA]
+* Fix GCC 11 compile error (#3273). [HungMingWu]
+
+
+Verilator 4.216 2021-12-05
+==========================
+
+**Major:**
+
+* Add --lib-create, similar to --protect-lib but without protections.
+* Support tracing through --hierarchical/--lib-create libraries (#3200).
+
+**Minor:**
+
+* Internal code cleanups and improvements. [Geza Lore]
+* Improve --thread verilation-time performance.
+* Support task name in $display %m (#3211). [Julie Schwartz]
+* Make 'bit', 'logic' and 'time' types unsigned by default. [Geza Lore]
+* Optimize $random concatenates/selects (#3114).
+* Fix array method names with parenthesis (#3181) (#3183). [Teng Huang]
+* Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA]
+* Fix wrong bit op tree optimization (#3185). [Yutetsu TAKATSUKASA]
+* Fix some SliceSels not being constants (#3186) (#3218). [Michaël Lefebvre]
+* Fix nested generate if genblk naming (#3189). [yanx21]
+* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
+* Fix display of signed without format (#3204). [Julie Schwartz]
+* Fix display of empty string constant (#3207) (#3215). [Julie Schwartz]
+* Fix incorrect width after and-or optimization (#3208). [Julie Schwartz]
+* Fix $fopen etc on integer arrays (#3214). [adrienlemasle]
+* Fix $size on dynamic strings (#3216).
+* Fix %0 format on $value$plusargs (#3217).
+* Fix timescale portability on Arm64 (#3222).
+
+
+Verilator 4.214 2021-10-17
+==========================
+
+**Major:**
+
+* Add profile-guided optmization of mtasks (#3150).
+
+**Minor:**
+
+* Verilator_gantt has removed the ASCII graphics, use the VCD output instead.
+* Verilator_gantt now shows the predicted mtask times, eval times, and additional statistics.
+* Verilator_gantt data files now include processor information, to allow later processing.
+* Support displaying x and z in $display task (#3107) (#3109). [Iru Cai]
+* Fix verilator_profcfunc profile accounting (#3115).
+* Fix display has no time units on class function (#3116). [Damien Pretet]
+* Fix removing if statement with side effect in condition (#3131). [Alexander Grobman]
+* Fix --waiver-output for multiline warnings (#2429) (#3141). [Keith Colbert]
+* Fix internal error on bad widths (#3140) (#3145). [Zhanglei Wang]
+* Fix crash on clang 12/13 (#3148). [Kouping Hsu]
+* Fix cygwin compile error due to missing -std=gnu++14 (#3149). [Sun Kim]
+* Fix $urandom_range when the range is 0 ... UINT_MAX (#3161). [Iru Cai]
+* Fix constructor-parameter argument comma-separation in C++ (#3162). [Matthew Ballance]
+* Fix missing install of vl_file_copy/vl_hier_graph (#3165). [Popolon]
+* Fix calling new with arguments in same class (#3166). [Matthew Ballance]
+* Fix false EOFNEWLINE warning when DOS carriage returns present (#3171).
+
+
+Verilator 4.212 2021-09-01
+==========================
+
+**Minor:**
+
+* Fix re-evaluation of logic dependent on state set in DPI exports (#3091). [Geza Lore]
+* Support unpacked array localparams in tasks/functions (#3078). [Geza Lore]
+* Support timeunit/timeprecision in $unit.
+* Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski]
+* Add --instr-count-dpi to tune assumed DPI import cost for multithreaded
+  model scheduling. Default value changed to 200 (#3068). [Yinan Xu]
+* Output files are split based on the set of headers required
+  in order to aid incremental compilation via ccache (#3071). [Geza Lore]
+* Parameter values are now emitted as 'static constexpr' instead of enum.
+  C++ direct references to parameters might require updating (#3077). [Geza Lore]
+* Refactored Verilated include files; include verilated.h not verilated_heavy.h.
+* Add header guards on Dpi.h generated files (#2979). [Tood Strader]
+* Add XML ccall, constpool, initarray, and if/while begins (#3080). [Steven Hugg]
+* Add error when constant function under a generate (#3103). [Don Owen]
+* Fix -G to treat simple integer literals as signed (#3060). [Anikin1610]
+* Fix emitted string array initializers (#2895). [Iztok Jeras]
+* Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt]
+* Fix internal error on wide -x-initial unique (#3106). [Alexandre Joannou]
+* Fix traces to show array instances with brackets (#3092) (#3095). [Pieter Kapsenberg]
+
+
+Verilator 4.210 2021-07-07
+==========================
+
+**Major:**
+
+* Generated code is now emitted as global functions rather than methods. '$c'
+  contents might need to be updated, see the docs (#3006). [Geza Lore]
+* The generated model class instantiated by the user is now an interface
+  object and no longer the TOP module instance.  User code with direct
+  C++ member access to model internals, including verilator public_flat
+  items will likely need to be updated. See the manual for instructions:
+  https://verilator.org/guide/latest/connecting.html#porting-from-pre-4-210
+  (#3036). [Geza Lore]
+
+**Minor:**
+
+* Add --prof-c to pass profiling to compiler (#3059). [Alexander Grobman]
+* Optimize a lot more model variables into function locals (#3027). [Geza Lore]
+* Support middle-of-design nested topmodules (#3026). [Dan Petrisko]
+* Remove deprecated --no-relative-cfuncs option (#3024). [Geza Lore]
+* Remove deprecated --inhibit-sim option (#3035). [Geza Lore]
+* Merge const static data globally into a new constant pool (#3013). [Geza Lore]
+* Allow configure override of AR program (#2999). [ahouska]
+* In XML, show pinIndex information (#2877). [errae233]
+* Fix error on unsupported recursive functions (#2957). [Trefor Southwell]
+* Fix type parameter specialization when struct names are same (#3055). [7FM]
+* Improve speed of table optimization (-OA) pass. [Geza Lore]
+
+
 Verilator 4.204 2021-06-12
 ==========================
 
@@ -3650,7 +3851,7 @@ Verilator 0.0 1994-07-08
 Copyright
 =========
 
-Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

MANIFEST.SKIP

@@ -1,76 +0,0 @@
-\.ccache/
-\.clang-format
-\.clang-tidy
-\.git/
-\.git$
-\.github/
-\.svn/
-\.(bak|old)/
-\.(bak|old)$
-\.tar\.
-.*\.tgz
-.*\.log
-\..*\.swp
-.*\.tmp
-.*\.tidy
-.*\.tex
-.*\.key
-.*\.vcd
-.*\.1
-\.codacy\.yml
-\.travis\.yml
-/_build/
-/build/
-/obj_dbg/
-/obj_dir/
-/obj_dist/
-/obj_iv/
-/obj_ms/
-/obj_nc/
-/obj_opt/
-/obj_vcs/
-/obj_vlt/
-/obj_vltmt/
-INCA_libs/
-/cov_work/
-/logs/
-^Makefile$
-README.html
-bin/verilator_bin.*
-bin/verilator_coverage_bin.*
-docs/.*\.html$
-docs/_build/
-docs/clang-format.txt$
-docs/doxygen-doc/.*
-docs/spelling.txt
-examples/xml_py/copied/
-examples/xml_py/graph.*
-sonar-project.properties
-src/Makefile$
-src/Makefile_obj$
-include/verilated.mk$
-test_regress/.gdbinit$
-test_regress/transcript
-codecov.yml
-config.cache$
-config.status$
-verilator\.log
-verilator\.tex
-verilator-config.cmake$
-verilator-config-version.cmake$
-verilator.pc$
-verilator_bin.*
-verilator_coverage_bin.*
-.vcsmx_rebuild$
-ncverilog.history
-autom4te\.cache/
-nodist/
-ci/
-/simv$
-/simv.daidir/
-/vc_hdrs.h$
-/csrc/
-obj_dir.*
-TAGS
-gmon.out
-.*~

Makefile.in

@@ -7,7 +7,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -118,98 +118,6 @@ INFOS = verilator.html verilator.pdf
 
 INFOS_OLD = README README.html README.pdf
 
-# Files that can be generated, but should be up to date for a distribution.
-DISTDEP = info Makefile
-
-DISTFILES1 = $(INFOS) .gitignore \
-	*.in *.ac \
-	Artistic \
-	Changes \
-	LICENSE \
-	MANIFEST.SKIP \
-	README.rst \
-	verilator-config.cmake.in \
-	verilator-config-version.cmake.in \
-	bin/verilator \
-	bin/verilator_ccache_report \
-	bin/verilator_coverage \
-	bin/verilator_difftree \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	docs/.gitignore \
-	docs/CONTRIBUTING.rst \
-	docs/CONTRIBUTORS \
-	docs/Makefile \
-	docs/_static/*.png \
-	docs/_static/css/* \
-	docs/bin/* \
-	docs/gen/* \
-	docs/guide/*.py \
-	docs/guide/*.rst \
-	docs/guide/figures/* \
-	docs/install.rst \
-	docs/internals.rst \
-	docs/internals.rst \
-	docs/verilated.dox \
-	docs/xml.rst \
-	install-sh configure *.pod \
-	include/*.[chv]* \
-	include/*.in \
-	include/.*ignore \
-	include/gtkwave/*.[chv]* \
-	include/vltstd/*.[chv]* \
-	.*attributes */.*attributes  */*/.*attributes \
-	src/.*ignore src/*.in src/*.cpp src/*.[chly] \
-	src/astgen src/bisonpre src/*fix src/cppcheck_filtered \
-	src/config_rev \
-	src/vlcovgen src/mkinstalldirs \
-	src/.gdbinit \
-	src/*.pl src/*.pod \
-	examples/*/.*ignore examples/*/Makefile* \
-	examples/*/*.[chv]* examples/*/vl_* \
-	examples/*/CMakeLists.txt \
-
-DISTFILES2 = \
-	test_*/.*ignore test_*/Makefile* test_*/*.cpp \
-	test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \
-	test_regress/*.pl \
-	test_regress/Makefile \
-	test_regress/Makefile_obj \
-	test_regress/input.vc \
-	test_regress/CMakeLists.txt \
-	test_regress/t/t*/*.sv* \
-	test_regress/t/t*/*.v* \
-	test_regress/t/t*/*/*.sv* \
-	test_regress/t/t*/*/*.v* \
-	test_regress/t/t*/*.cpp \
-	test_regress/t/t*/CMakeLists.txt \
-	test_regress/t/*.cpp \
-	test_regress/t/*.h \
-	test_regress/t/*.dat \
-	test_regress/t/*.mem \
-	test_regress/t/*.out \
-	test_regress/t/*.pl \
-	test_regress/t/*.pf \
-	test_regress/t/*.v* \
-
-INST_PROJ_FILES = \
-	bin/verilator \
-	bin/verilator_ccache_report \
-	bin/verilator_coverage \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	include/verilated.mk \
-	include/*.[chv]* \
-	include/gtkwave/*.[chv]* \
-	include/vltstd/*.[chv]* \
-
-INST_PROJ_BIN_FILES = \
-	bin/verilator_bin$(EXEEXT) \
-	bin/verilator_bin_dbg$(EXEEXT) \
-	bin/verilator_coverage_bin_dbg$(EXEEXT) \
-
 EXAMPLES_FIRST = \
 	examples/make_hello_c \
 	examples/make_hello_sc \
@@ -217,7 +125,7 @@ EXAMPLES_FIRST = \
 EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*)))
 
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_MAN_FILES = verilator.1 verilator_coverage.1 verilator_gantt.1 verilator_profcfunc.1
+VL_INST_MAN_FILES = verilator.1 verilator_coverage.1
 
 default: all
 all: all_nomsg msg_test
@@ -230,7 +138,7 @@ all_nomsg: verilator_exe $(VL_INST_MAN_FILES)
 verilator_exe verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT):
 	@echo ------------------------------------------------------------
 	@echo "making verilator in src"
-	$(MAKE) -C src $(OBJCACHE_JOBS) $(CI_MAKE_SRC_TARGET)
+	$(MAKE) -C src $(OBJCACHE_JOBS)
 
 .PHONY:msg_test
 msg_test: all_nomsg
@@ -299,8 +207,10 @@ VL_INST_INC_SRCDIR_FILES = \
 	include/vltstd/*.[chv]* \
 
 VL_INST_DATA_SRCDIR_FILES = \
-	examples/*/*.[chv]*  examples/*/Makefile* \
-	examples/*/CMakeLists.txt
+	examples/*/*.[chv]* \
+	examples/*/CMakeLists.txt \
+	examples/*/Makefile* \
+	examples/*/vl_* \
 
 installbin:
 	$(MKINSTALLDIRS) $(DESTDIR)$(bindir)
@@ -386,44 +296,7 @@ uninstall:
 install: all_nomsg install-all
 install-all: installbin installman installdata install-msg
 
-install-here: installman ftp
-
-ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
-DISTNAMEREV = $(shell sed -e '/DTVERSION/!d' -e 's/.*verilator_\([^"]*\).*/\1/' -e q ${srcdir}/src/config_rev.h)
-
-VERILATOR_CAD_DIR = $(CAD_DIR)/verilator/$(DISTNAMEREV)/$(DIRPROJECT_ARCH)
-INST_PROJ_CVS = cp_if_cvs_diff
-
-install-cadtools: dist
-	@echo "Install-project to $(CAD_DIR)"
-	strip bin/verilator_bin*
-	strip bin/verilator_coverage_bin*
-	$(MAKE) install-cadtools-quick
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/man/man1
-	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_DATA) $$p $(VERILATOR_CAD_DIR)/man/man1/$$p; \
-	done
-	$(INST_PROJ_CVS) $(DISTNAME).tgz $(VERILATOR_CAD_DIR)/verilator.tgz
-	rm $(DISTNAME).tgz
-
-install-cadtools-quick:
-ifeq ($(CFG_WITH_DEFENV),yes)
-	@echo "%Error: Reconfigure with './configure --disable-defenv' to avoid hardcoded paths."
-	false
-endif
-	@echo "Install-cadtools-quick (no strip) to $(VERILATOR_CAD_DIR)"
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/include/gtkwave
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/include/vltstd
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/bin
-	for p in $(INST_PROJ_FILES) ; do \
-	  $(INST_PROJ_CVS) $$p $(VERILATOR_CAD_DIR)/$$p; \
-	done
-	for p in $(INST_PROJ_BIN_FILES) ; do \
-	  $(INST_PROJ_CVS) $$p $(VERILATOR_CAD_DIR)/$$p; \
-	done
-
-# VERILATOR_AUTHOR_SITE
-endif
+install-here: installman info
 
 # Use --xml flag to see the cppcheck code to use for suppression
 CPPCHECK_CPP = $(wildcard \
@@ -470,17 +343,20 @@ analyzer-include:
 
 format: clang-format yapf format-pl-exec
 
-CLANGFORMAT = clang-format
+CLANGFORMAT = clang-format-11
 CLANGFORMAT_FLAGS = -i
 CLANGFORMAT_FILES = $(CPPCHECK_CPP) $(CPPCHECK_H) $(CPPCHECK_YL) test_regress/t/*.c* test_regress/t/*.h
 
 clang-format:
-	@$(CLANGFORMAT) --version | egrep 10.0 > /dev/null \
-		|| echo "*** You are not using clang-format 10.0, indents may differ from master's ***"
+	@$(CLANGFORMAT) --version | egrep 11.0 > /dev/null \
+		|| echo "*** You are not using clang-format 11.0, indents may differ from master's ***"
 	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
 
 PY_PROGRAMS = \
 	bin/verilator_ccache_report \
+	bin/verilator_difftree \
+	bin/verilator_gantt \
+	bin/verilator_profcfunc \
 	examples/xml_py/vl_file_copy \
 	examples/xml_py/vl_hier_graph \
 	docs/guide/conf.py \
@@ -492,6 +368,7 @@ PY_PROGRAMS = \
 	src/cppcheck_filtered \
 	src/flexfix \
 	src/vlcovgen \
+	test_regress/t/*.pf \
 	nodist/code_coverage \
 	nodist/dot_importer \
 	nodist/fuzzer/actual_fail \
@@ -523,9 +400,6 @@ lint-py:
 format-pl-exec:
 	-chmod a+x test_regress/t/*.pl
 
-
-ftp: info
-
 install-msg:
 	@echo
 	@echo "Installed binaries to $(DESTDIR)$(bindir)/verilator"
@@ -596,15 +470,6 @@ TAGS:	$(TAGFILES)
 doxygen:
 	$(MAKE) -C docs doxygen
 
-######################################################################
-# Test targets
-
-dist-file-list:
-	@echo "begin-dist-file-list:";  # Scripts look for this
-	@echo $(wildcard $(DISTFILES1))
-	@echo $(wildcard $(DISTFILES2))
-	@echo "end-dist-file-list:";  # Scripts look for this
-
 ######################################################################
 # Distributions
 
@@ -612,36 +477,16 @@ DISTTITLE := Verilator $(word 1,$(PACKAGE_VERSION))
 DISTNAME := verilator-$(word 1,$(PACKAGE_VERSION))
 DISTDATEPRE := $(word 2,$(PACKAGE_VERSION))
 DISTDATE := $(subst /,-,$(DISTDATEPRE))
-
 DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME)))
 
 tag:
 	svnorcvs tag $(DISTTAGNAME)
 
-# Don't depend on DISTFILES because there's no rule for "standards.info*".
-dist: $(DISTDEP) maintainer-copy
-	-rm -fr $(DISTNAME)
-	for file in $(DISTFILES1); do \
-	  mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \
-	  ln $$file $(DISTNAME)/$$file \
-	  || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \
-	done; true;
-	for file in $(DISTFILES2); do \
-	  mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \
-	  ln $$file $(DISTNAME)/$$file \
-	  || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \
-	done; true;
-	chmod -R a+r $(DISTNAME)
-	tar chf $(DISTNAME).tar $(DISTNAME)
-	gzip --force --best $(DISTNAME).tar
-	mv $(DISTNAME).tar.gz $(DISTNAME).tgz
-	rm -fr $(DISTNAME)
-
 maintainer-diff:
 	svnorcvs diff $(DISTTAGNAME)
 
 preexist:
 	svnorcvs nexists $(DISTTAGNAME)
 
-maintainer-dist: preexist dist tag
-	svnorcvs release $(DISTNAME).tgz
+maintainer-dist: preexist tag
+	svnorcvs release $(DISTTAGNAME)

README.rst

@@ -5,6 +5,8 @@
     :target: https://www.gnu.org/licenses/lgpl-3.0]
 .. image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
     :target: https://opensource.org/licenses/Artistic-2.0
+.. image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
+    :target: https://repology.org/project/verilator/versions
 .. image:: https://api.codacy.com/project/badge/Grade/fa78caa433c84a4ab9049c43e9debc6f
     :target: https://www.codacy.com/gh/verilator/verilator
 .. image:: https://codecov.io/gh/verilator/verilator/branch/master/graph/badge.svg
@@ -12,6 +14,7 @@
 .. image:: https://github.com/verilator/verilator/workflows/build/badge.svg
     :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
 
+
 Welcome to Verilator
 ====================
 
@@ -70,7 +73,7 @@ for you.
 Performance
 ===========
 
-Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather,
+Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
 Verilator compiles your code into a much faster optimized and optionally
 thread-partitioned model, which is in turn wrapped inside a C++/SystemC
 module. The results are a compiled Verilog model that executes even on a
@@ -134,7 +137,7 @@ Related Projects
 Open License
 ============
 
-Verilator is Copyright 2003-2021 by Wilson Snyder. (Report bugs to
+Verilator is Copyright 2003-2022 by Wilson Snyder. (Report bugs to
 `Verilator Issues <https://verilator.org/issues>`_.)
 
 Verilator is free software; you can redistribute it and/or modify it under

bin/verilator

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -34,11 +34,11 @@ my $opt_quiet_exit;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # Insert debugging options up front
-push @ARGV, (split ' ',$ENV{VERILATOR_TEST_FLAGS}||"");
+push @ARGV, (split ' ', $ENV{VERILATOR_TEST_FLAGS} || "");
 
 # We sneak a look at the flags so we can do some pre-environment checks
 # All flags will hit verilator...
@@ -46,7 +46,7 @@ foreach my $sw (@ARGV) {
     push @Opt_Verilator_Sw, $sw;
 }
 
-Getopt::Long::config("no_auto_abbrev","pass_through");
+Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions(
           # Major operating modes
           "help"        => \&usage,
@@ -60,7 +60,7 @@ if (! GetOptions(
           # Additional parameters
           "<>"          => sub {},      # Ignored
     )) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 if ($opt_gdbbt && !gdb_works()) {
@@ -73,12 +73,12 @@ if ($opt_gdbbt && !gdb_works()) {
 # Starting with that, escape all special chars for the shell;
 # The shell will undo the escapes and the verilator binary should
 # then see exactly the contents of @Opt_Verilator_Sw.
-my @quoted_sw = map {sh_escape($_)} @Opt_Verilator_Sw;
+my @quoted_sw = map { sh_escape($_) } @Opt_Verilator_Sw;
 if ($opt_gdb) {
     # Generic GDB interactive
     run (aslr_off()
-         .($ENV{VERILATOR_GDB}||"gdb")
-         ." ".verilator_bin()
+         . ($ENV{VERILATOR_GDB} || "gdb")
+         . " " . verilator_bin()
          # Note, uncomment to set breakpoints before running:
          #  ." -ex 'break main'"
 
@@ -87,42 +87,41 @@ if ($opt_gdb) {
          # escapes as you would expect in a double-quoted string.
          # That's not true for a single-quoted string, where \'
          # actually terminates the string -- not what we want!
-         ." -ex \"run ".join(' ', @quoted_sw)."\""
-         ." -ex 'set width 0'"
-         ." -ex 'bt'");
+         . " -ex \"run " . join(' ', @quoted_sw) . "\""
+         . " -ex 'set width 0'"
+         . " -ex 'bt'");
 } elsif ($opt_rr) {
     # Record with rr
     run (aslr_off()
-         ."rr record ".verilator_bin()
-         ." ".join(' ', @quoted_sw));
+         . "rr record " . verilator_bin()
+         . " " . join(' ', @quoted_sw));
 } elsif ($opt_gdbbt && $Debug) {
     # Run under GDB to get gdbbt
     run (aslr_off()
-         ."gdb"
-         ." ".verilator_bin()
-         ." --batch --quiet --return-child-result"
-         ." -ex \"run ".join(' ', @quoted_sw)."\""
-         ." -ex 'set width 0'"
-         ." -ex 'bt' -ex 'quit'");
+         . "gdb"
+         . " " . verilator_bin()
+         . " --batch --quiet --return-child-result"
+         . " -ex \"run " . join(' ', @quoted_sw)."\""
+         . " -ex 'set width 0'"
+         . " -ex 'bt' -ex 'quit'");
 } elsif ($Debug) {
     # Debug
-    run(aslr_off()
-        .verilator_bin()." ".join(' ',@quoted_sw));
+    run(aslr_off() . verilator_bin() . " " . join(' ', @quoted_sw));
 } else {
     # Normal, non gdb
-    run(verilator_bin()." ".join(' ',@quoted_sw));
+    run(verilator_bin() . " " . join(' ', @quoted_sw));
 }
 
 #----------------------------------------------------------------------
 
 sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
+    pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT);
 }
 
 sub debug {
     shift;
     my $level = shift;
-    $Debug = $level||3;
+    $Debug = $level || 3;
 }
 
 #######################################################################
@@ -163,13 +162,13 @@ sub verilator_bin {
 sub gdb_works {
     $! = undef;  # Cleanup -x
     system("gdb /bin/echo"
-           ." --batch-silent --quiet --return-child-result"
-           ." -ex 'run -n'"  # `echo -n`
-           ." -ex 'set width 0'"
-           ." -ex 'bt'"
-           ." -ex 'quit'");
+           . " --batch-silent --quiet --return-child-result"
+           . " -ex 'run -n'"  # `echo -n`
+           . " -ex 'set width 0'"
+           . " -ex 'bt'"
+           . " -ex 'quit'");
     my $status = $?;
-    return $status==0;
+    return $status == 0;
 }
 
 sub aslr_off {
@@ -185,7 +184,7 @@ sub run {
     # Run command, check errors
     my $command = shift;
     $! = undef;  # Cleanup -x
-    print "\t$command\n" if $Debug>=3;
+    print "\t$command\n" if $Debug >= 3;
     system($command);
     my $status = $?;
     if ($status) {
@@ -193,7 +192,7 @@ sub run {
             warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
         }
         if ($Debug) {  # For easy rerunning
-            warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
+            warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n";
             warn "%Error: $command\n";
         }
         if ($status & 127) {
@@ -201,13 +200,13 @@ sub run {
                 || ($status & 127) == 8  # SIGFPA
                 || ($status & 127) == 11) {  # SIGSEGV
                 warn "%Error: Verilator internal fault, sorry. "
-                    ."Suggest trying --debug --gdbbt\n" if !$Debug;
+                    . "Suggest trying --debug --gdbbt\n" if !$Debug;
             } elsif (($status & 127) == 6) {  # SIGABRT
                 warn "%Error: Verilator aborted. "
-                    ."Suggest trying --debug --gdbbt\n" if !$Debug;
+                    . "Suggest trying --debug --gdbbt\n" if !$Debug;
             } else {
                 warn "%Error: Verilator threw signal $status. "
-                    ."Suggest trying --debug --gdbbt\n" if !$Debug;
+                    . "Suggest trying --debug --gdbbt\n" if !$Debug;
             }
         }
         if (!$opt_quiet_exit && ($status != 256 || $Debug)) {  # i.e. not normal exit(1)
@@ -332,11 +331,12 @@ detailed descriptions of these arguments.
     --gate-stmts <value>        Tune gate optimizer depth
     --if-depth <value>          Tune IFDEPTH warning
      +incdir+<dir>              Directory to search for includes
-    --inhibit-sim               Create function to turn off sim
     --inline-mult <value>       Tune module inlining
+    --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
      -LDFLAGS <flags>           Linker pre-object arguments for makefile
     --l2-name <value>           Verilog scope name of the top module
     --language <lang>           Default language standard to parse
+    --lib-create <name>         Create a DPI library
      +libext+<ext>+[ext]...     Extensions for finding modules
     --lint-only                 Lint, but do not make output
      -MAKEFLAGS <flags>         Arguments to pass to make during --build
@@ -344,10 +344,11 @@ detailed descriptions of these arguments.
     --MMD                       Create .d dependency files
     --MP                        Create phony dependency targets
     --Mdir <directory>          Name of output object directory
+    --no-merge-const-pool       Disable merging of different types in const pool
     --mod-prefix <topname>      Name to prepend to lower classes
     --no-clk <signal-name>      Prevent marking specified signal as clock
     --no-decoration             Disable comments and symbol decorations
-    --no-pins64                 Don't use vluint64_t's for 33-64 bit sigs
+    --no-pins64                 Don't use uint64_t's for 33-64 bit sigs
     --no-skip-identical         Disable skipping identical output
      +notimingchecks            Ignored
      -O0                        Disable optimizations
@@ -367,8 +368,10 @@ detailed descriptions of these arguments.
     --pipe-filter <command>     Filter all input through a script
     --pp-comments               Show preprocessor comments with -E
     --prefix <topname>          Name of top level class
+    --prof-c                    Compile C++ code with profiling
     --prof-cfuncs               Name functions for profiling
-    --prof-threads              Enable generating gantt chart data for threads
+    --prof-exec                 Enable generating execution profile for gantt chart
+    --prof-pgo                  Enable generating profiling data for PGO
     --protect-key <key>         Key for symbol protection
     --protect-ids               Hash identifier names for obscurity
     --protect-lib <name>        Create a DPI protected library
@@ -378,7 +381,6 @@ detailed descriptions of these arguments.
      -pvalue+<name>=<value>     Overwrite toplevel parameter
     --quiet-exit                Don't print the command on failure
     --relative-includes         Resolve includes relative to current file
-    --no-relative-cfuncs        Disallow 'this->' in generated functions
     --reloop-limit              Minimum iterations for forming loops
     --report-unoptflat          Extra diagnostics for UNOPTFLAT
     --rr                        Run Verilator and record with rr
@@ -444,9 +446,10 @@ description of these arguments.
      +verilator+error+limit+<value>    Set error limit
      +verilator+help                   Display help
      +verilator+noassert               Disable assert checking
-     +verilator+prof+threads+file+<filename>  Set profile filename
-     +verilator+prof+threads+start+<value>    Set profile starting point
-     +verilator+prof+threads+window+<value>   Set profile duration
+     +verilator+prof+exec+file+<filename>  Set execution profile filename
+     +verilator+prof+exec+start+<value>    Set execution profile starting point
+     +verilator+prof+exec+window+<value>   Set execution profile duration
+     +verilator+prof+vlt+file+<filename>   Set PGO profile filename
      +verilator+rand+reset+<value>     Set random reset technique
      +verilator+seed+<value>           Set random seed
      +verilator+V                      Verbose version and config
@@ -457,7 +460,7 @@ description of these arguments.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.

bin/verilator_ccache_report

@@ -14,7 +14,7 @@ parser = argparse.ArgumentParser(
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Report ccache behavior of a Verilated model build.""",
     epilog=
-    """Copyright 2002-2021 by Wilson Snyder. This program is free software; you
+    """Copyright 2002-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -88,6 +88,7 @@ else:
         args.o.write("{:{width}}| {}s\n".format(k,
                                                 v.total_seconds(),
                                                 width=wnames))
-        if i > 4: break
+        if i > 4:
+            break
 
 args.o.write("#" * 80 + "\n")

bin/verilator_coverage

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -30,7 +30,7 @@ $Debug = 0;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # We sneak a look at the flags so we can do some pre-environment checks
@@ -40,7 +40,7 @@ foreach my $sw (@ARGV) {
     push @Opt_Verilator_Sw, $sw;
 }
 
-Getopt::Long::config("no_auto_abbrev","pass_through");
+Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions (
           # Major operating modes
           "help"        => \&usage,
@@ -49,23 +49,23 @@ if (! GetOptions (
           # Additional parameters
           "<>"          => sub {},      # Ignored
     )) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # Normal, non gdb
 run(verilator_coverage_bin()
-    ." ".join(' ',@Opt_Verilator_Sw));
+    . " " . join(' ', @Opt_Verilator_Sw));
 
 #----------------------------------------------------------------------
 
 sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
+    pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT);
 }
 
 sub debug {
     shift;
     my $level = shift;
-    $Debug = $level||3;
+    $Debug = $level || 3;
 }
 
 #######################################################################
@@ -107,7 +107,7 @@ sub run {
     # Run command, check errors
     my $command = shift;
     $! = undef;  # Cleanup -x
-    print "\t$command\n" if $Debug>=3;
+    print "\t$command\n" if $Debug >= 3;
     system($command);
     my $status = $?;
     if ($status) {
@@ -115,11 +115,11 @@ sub run {
             warn "%Error: verilator_coverage: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
         }
         if ($Debug) {  # For easy rerunning
-            warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
+            warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n";
             warn "%Error: $command\n";
         }
         if ($status & 127) {
-            if (($status & 127) == 8 || ($status & 127) == 11) { # SIGFPA or SIGSEGV
+            if (($status & 127) == 8 || ($status & 127) == 11) {  # SIGFPA or SIGSEGV
                 warn "%Error: Verilator_coverage internal fault, sorry.\n" if !$Debug;
             } elsif (($status & 127) == 6) {  # SIGABRT
                 warn "%Error: Verilator_coverage aborted.\n" if !$Debug;
@@ -187,7 +187,7 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

bin/verilator_difftree

@@ -1,233 +1,139 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116
 ######################################################################
 
-use warnings;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-use strict;
-use vars qw($Debug);
+import argparse
+import collections
+import glob
+import os.path
+import re
+import sys
 
-#======================================================================
-# main
 
-$Debug = 0;
-my $Opt_A;
-my $Opt_B;
-my $Opt_Lineno = 1;
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          "<>"          => \&parameter,
-          "lineno!"     => \$Opt_Lineno,
-    )) {
-    die "%Error: Bad usage, try 'verilator_difftree --help'\n";
-}
+def diff(a, b):
 
-defined $Opt_A or die "%Error: No old diff filename\n";
-defined $Opt_B or die "%Error: No new diff filename\n";
+    if not os.path.exists(a):
+        sys.exit("%Error: No old diff filename found: " + a)
+    if not os.path.exists(b):
+        sys.exit("%Error: No new diff filename found: " + b)
 
--e $Opt_A or die "%Error: No old diff filename found: $Opt_A\n";
--e $Opt_B or die "%Error: No new diff filename found: $Opt_B\n";
+    if os.path.isdir(a) and os.path.isdir(b):
+        diff_dir(a, b)
+    elif os.path.isfile(a) and os.path.isfile(b):
+        diff_file(a, b)
+    else:
+        sys.exit("%Error: Mix of files and dirs")
 
-if (-d $Opt_A && -d $Opt_B) {
-    diff_dir($Opt_A, $Opt_B);
-} elsif (-f $Opt_A && -f $Opt_B) {
-    diff_file($Opt_A, $Opt_B);
-} else {
-    die "%Error: Mix of files and dirs\n";
-}
 
-sub diff_dir {
-    my $a = shift;
-    my $b = shift;
+def diff_dir(a, b):
     # Diff all files under two directories
-    my %files;
+    files = collections.defaultdict(lambda: {})
 
-    foreach my $fn (glob("$a/*.tree")) {
-        (my $base = $fn) =~ s!.*/!!;
-        $files{$base}{a} = $fn;
-    }
-    foreach my $fn (glob("$b/*.tree")) {
-        (my $base = $fn) =~ s!.*/!!;
-        $files{$base}{b} = $fn;
-    }
-    my $any;
-    foreach my $base (sort (keys %files)) {
-        my $a = $files{$base}{a};
-        my $b = $files{$base}{b};
-        next if !$a || !$b;
-        print "="x70,"\n";
-        print "= $a <-> $b\n";
-        diff_file($a,$b);
-        $any = 1;
-    }
-    $any or warn("%Warning: No .tree files found that have similar base names:\n    "
-                 .join("\n    ", sort keys %files),"\n");
-}
+    for fn in glob.glob(a + "/*.tree"):
+        base = re.sub(r'.*/', '', fn)
+        files[base]['a'] = fn
+    for fn in glob.glob(b + "/*.tree"):
+        base = re.sub(r'.*/', '', fn)
+        files[base]['b'] = fn
 
-sub diff_file {
-    my $a = shift;
-    my $b = shift;
+    anyfile = False
+    for base in sorted(files.keys()):
+        if (not 'a' in files[base]) or (not 'b' in files[base]):
+            continue
+        a = files[base]['a']
+        b = files[base]['b']
+        print("=" * 70)
+        print("= %s <-> %s" % (a, b))
+        diff_file(a, b)
+        anyfile = True
+    if not anyfile:
+        sys.stderr.write(
+            "%Warning: No .tree files found that have similar base names\n")
+
+
+def diff_file(a, b):
     # Compare the two tree files
-    (my $short_a = $a) =~ s/[^a-zA-Z0-9.]+/_/g;
-    (my $short_b = $b) =~ s/[^a-zA-Z0-9.]+/_/g;
-    my $tmp_a = "/tmp/${$}_${short_a}.a";
-    my $tmp_b = "/tmp/${$}_${short_b}.b";
+    short_a = re.sub(r'[^a-zA-Z0-9.]+', '_', a)
+    short_b = re.sub(r'[^a-zA-Z0-9.]+', '_', b)
+    tmp_a = "/tmp/%s_%s.a" % (os.getpid(), short_a)
+    tmp_b = "/tmp/%s_%s.b" % (os.getpid(), short_b)
 
-    my $vera = version_from($a);
-    my $verb = version_from($b);
-    my $verCvt = (($vera < 0x3900 && $verb >= 0x3900)
-                  || ($vera >= 0x3900 && $verb < 0x3900));
+    # Version conversion deprecated, but for future...
+    # vera = version_from(a)
+    # verb = version_from(b)
+    # verCvt = ((vera < 0x3900 and verb >= 0x3900)
+    #            or (vera >= 0x3900 and verb < 0x3900))
 
-    filter($a, $tmp_a, $verCvt);
-    filter($b, $tmp_b, $verCvt);
-    system("diff -u $tmp_a $tmp_b");
-    unlink $tmp_a;
-    unlink $tmp_b;
-}
+    filterf(a, tmp_a)
+    filterf(b, tmp_b)
+    os.system("diff -u " + tmp_a + " " + tmp_b)
+    os.unlink(tmp_a)
+    os.unlink(tmp_b)
 
-sub version_from {
-    my $fn = shift;
+
+def version_from(filename):
     # Return dump format
-    my $f1 = IO::File->new ($fn) or die "%Error: $! $fn,";
-    while (defined (my $line=$f1->getline())) {
-        last if $. > 10;
-        return hex $1 if $line =~ /\(format (0x[0-9.]+)\)/;
-    }
-    return 1.0;
-}
+    with open(filename) as fh:
+        lineno = 0
+        for line in fh:
+            if lineno > 10:
+                break
+            match = re.search(r'format (0x[0-9.]+)', line)
+            if match:
+                return hex(match.group(1))
+    return 1.0
 
-sub filter {
-    my $fn1 = shift;
-    my $fn2 = shift;
-    my $verCvt = shift;
+
+def filterf(fn1, fn2):
     # Remove hex numbers before diffing
-    my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,";
-    my $f2 = IO::File->new ($fn2,"w") or die "%Error: $! $fn2,";
-    while (defined (my $line=$f1->getline())) {
-      same_line:
-        next if $line =~ / This=/;
-        $line =~ s/0x[a-f0-9]+/0x/g;
-        $line =~ s/<e[0-9]+\#?>/<e>/g;
-        $line =~ s/{[a-z]*\d+}/{}/g if !$Opt_Lineno;
-        if ($verCvt) {
-            next if $line =~ /^     NETLIST/;
-            if ($line =~ /: ([A-Z]+) /) {
-                my $type = $1;
-                next if $type =~ 'DTYPE';
-                if ($type eq 'TYPETABLE' || $type eq 'RANGE') {
-                    $line =~ /^(\s+\S+:) /; my $prefix = $1;
-                    while (defined ($line=$f1->getline())) {
-                        next if $line =~ /^\s+[a-z]/;  # Table body
-                        next if $line =~ /^${prefix}[0-9]:/;
-                        goto same_line;
-                    }
-                    next;
-                }
-            }
-        }
-        print $f2 $line;
-    }
-    $f1->close;
-    $f2->close;
-}
+    with open(fn1) as fh1:
+        with open(fn2, "w") as fh2:
+            for line in fh1:
+                if re.search(r' This=', line):
+                    continue
+                line = re.sub(r'0x[a-f0-9]+', '0x', line)
+                line = re.sub(r'<e[0-9]+\#?>', '<e>', line)
+                if not Args.no_lineno:
+                    line = re.sub(r'{[a-z]*\d+}', '{}', line)
+                fh2.write(line)
 
-#----------------------------------------------------------------------
 
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
+######################################################################
+######################################################################
 
-sub debug {
-    $Debug = 1;
-}
-
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_A) {
-        $Opt_A = $param;
-    } elsif (!defined $Opt_B) {
-        $Opt_B = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
-
-#######################################################################
-
-sub run {
-    # Run a system command, check errors
-    my $command = shift;
-    print "\t$command\n";
-    system "$command";
-    my $status = $?;
-    ($status == 0) or die "%Error: Command Failed $command, $status, stopped";
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_difftree - Compare two Verilator debugging trees
-
-=head1 SYNOPSIS
-
-  verilator_difftree .../a/a.tree  .../b/a.tree
-  verilator_difftree .../a         .../b
-
-=head1 DESCRIPTION
-
-Verilator_difftree is used for debugging Verilator tree output files.  It
-performs a diff between two files, or all files common between two
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Compare two Verilator debugging trees""",
+    epilog=
+    """Verilator_difftree is used for debugging Verilator tree output files.
+It performs a diff between two files, or all files common between two
 directories, ignoring irrelevant pointer differences.
 
-=head1 ARGUMENTS
+For documentation see
+https://verilator.org/guide/latest/exe_verilator_difftree.html
 
-=over 4
-
-=item --help
-
-Displays this message and program version and exits.
-
-=item --nolineno
-
-Do not show differences in line numbering.
-
-=back
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2005-2021 by Wilson Snyder. This program is free software; you
+Copyright 2005-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 AUTHORS
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('--no-lineno',
+                    action='store_false',
+                    help='do not show differences in line numbering')
+parser.add_argument('filea', help='input file a to diff')
+parser.add_argument('fileb', help='input file b to diff')
 
-Wilson Snyder <[email protected]>
-
-=head1 SEE ALSO
-
-C<verilator>
-
-and L<https://verilator.org/verilator_doc.html> for detailed documentation.
-
-=cut
+Args = parser.parse_args()
+diff(Args.filea, Args.fileb)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_difftree  {$V4D,$V4}/test_regress/obj_dir/t_EXAMPLE/V*_03_*.tree"
-### End:
+# Local Variables:
+# compile-command: "./verilator_difftree ../test_regress/t/t_difftree.{a,b}.tree"
+# End:

bin/verilator_includer

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 # DESCRIPTION: Print include statements for each ARGV
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,11 +10,11 @@
 
 require 5.005;
 use warnings;
-print "// DESCR"."IPTION: Generated by verilator_includer via makefile\n";
+print "// DESCR" . "IPTION: Generated by verilator_includer via makefile\n";
 foreach my $param (@ARGV) {
     if ($param =~ /^-D([^=]+)=(.*)/) {
-        print "#define $1 $2\n"
+        print "#define $1 $2\n";
     } else {
-        print "#include \"$param\"\n"
+        print "#include \"$param\"\n";
     }
 }

bin/verilator_profcfunc

@@ -1,248 +1,204 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116,R0914,R0912,R0915,eval-used
 ######################################################################
 
-require 5.006_001;
-use warnings;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-eval { use Data::Dumper;  $Data::Dumper::Indent = 1; }; # Debug, ok if missing
-use strict;
-use vars qw($Debug);
+import argparse
+import collections
+import re
+# from pprint import pprint
 
-#======================================================================
+######################################################################
 
 
-#======================================================================
-# main
+def profcfunc(filename):
+    funcs = {}
 
-$Debug = 0;
-my $Opt_File;
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          "<>"          => \&parameter,
-    )) {
-    die "%Error: Bad usage, try 'verilator_profcfunc --help'\n";
-}
+    with open(filename) as fh:
 
-defined $Opt_File or die "%Error: No filename given\n";
+        for line in fh:
+            #                  %time      cumesec   selfsec     calls     {stuff}   name
+            match = re.match(
+                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                line)
+            if match:
+                pct = float(match.group(1))
+                sec = float(match.group(2))
+                calls = float(match.group(3))
+                func = match.group(4)
+                if func not in funcs:
+                    funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
+                funcs[func]['pct'] += pct
+                funcs[func]['sec'] += sec
+                funcs[func]['calls'] += calls
+                continue
 
-profcfunc($Opt_File);
-
-#----------------------------------------------------------------------
-
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
-
-sub debug {
-    $Debug = 1;
-}
-
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_File) {
-        $Opt_File = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
-
-#######################################################################
-
-sub profcfunc {
-    my $filename = shift;
-    # Remove hex numbers before diffing
-    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
-
-    my %funcs;
-
-    while (defined (my $line=$fh->getline())) {
-        #                  %time      cumesec   selfsec     calls     {stuff}   name
-        if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
-            my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
-            $funcs{$func}{pct} += $pct;
-            $funcs{$func}{sec} += $sec;
-            $funcs{$func}{calls} += $calls;
-        }
-        # Older gprofs have no call column for single-call functions
-        #                  %time      cumesec   selfsec      {stuff}   name
-        elsif ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
-            my $pct=$1; my $sec=$2; my $calls=1; my $func=$3;
-            $funcs{$func}{pct} += $pct;
-            $funcs{$func}{sec} += $sec;
-            $funcs{$func}{calls} += $calls;
-        }
-    }
-    $fh->close;
+            # Older gprofs have no call column for single-call functions
+            #                  %time      cumesec   selfsec      {stuff}   name
+            match = re.match(
+                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                line)
+            if match:
+                pct = float(match.group(1))
+                sec = float(match.group(2))
+                calls = 1
+                func = match.group(3)
+                if func not in funcs:
+                    funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
+                funcs[func]['pct'] += pct
+                funcs[func]['sec'] += sec
+                funcs[func]['calls'] += calls
+                continue
 
     # Find modules
-    my %pointer_mods;
-    my %verilated_mods;
-    foreach my $func (keys %funcs) {
-        if ($func =~ /(.*)::_eval\(([a-zA-Z_0-9]+__Syms).*\)$/) {
-            $verilated_mods{$1} = qr/^$1/;
-            $pointer_mods{$2} = $1;
-        }
-    }
-    #print Dumper(\%pointer_mods, \%verilated_mods);
+    verilated_mods = {}
+    for func in funcs:
+        match = re.search(r'(.*)::eval(_step)?\(', func)
+        if match:
+            prefix = match.group(1)
+            if Args.debug:
+                print("-got _eval %s   prefix=%s" % (func, prefix))
+            verilated_mods[prefix] = re.compile(r'^' + prefix)
+    # pprint(verilated_mods)
 
-    # Resort by Verilog name
-    my %vfuncs;
-    my %groups;
-    foreach my $func (keys %funcs) {
-        my $pct = $funcs{$func}{pct};
-        my $vfunc = $func;
-        my $design;
+    # Sort by Verilog name
+    vfuncs = {}
+    groups = {}
+    groups['type'] = collections.defaultdict(lambda: 0)
+    groups['design'] = collections.defaultdict(lambda: 0)
+    groups['module'] = collections.defaultdict(lambda: 0)
 
-        if ($func =~ /\(([a-zA-Z_0-9]+__Syms)/) {
-            $design = $pointer_mods{$1};
-        }
+    for func in funcs:
+        pct = funcs[func]['pct']
+        vfunc = func
 
-        foreach my $vde (keys %verilated_mods) {
-            last if $design;
-            if ($func =~ /$verilated_mods{$vde}/) {
-                $design=$vde;
-                last;
-            }
-        }
+        funcarg = re.sub(r'^.*\(', '', func)
 
-        if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(/) {
-            $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
-            $groups{type}{"Verilog Blocks under $design"} += $pct;
-            $groups{design}{$design} += $pct;
-            $groups{module}{$1} += $pct;
-        } else {
-            if ($design) {
-                $vfunc = sprintf("VCommon   %s", $func);
-                $groups{type}{"Common code under $design"} += $pct;
-                $groups{design}{$design} += $pct;
-                $groups{module}{$design." common code"} += $pct;
-            } elsif ($func =~ /^VL_[A-Z0-9_]+/
-                     || $func =~ /^_?vl_[a-zA-Z0-9_]+/
-                     || $func =~ /^verilated/i) {
-                $vfunc = sprintf("VLib      %s", $func);
-                $groups{type}{'VLib'} += $pct;
-                $groups{design}{'VLib'} += $pct;
-                $groups{module}{'VLib'} += $pct;
-            } elsif ($func =~ /^_mcount_private/) {
-                $vfunc = sprintf("Prof      %s", $func);
-                $groups{type}{'Prof'} += $pct;
-                $groups{design}{'Prof'} += $pct;
-                $groups{module}{'Prof'} += $pct;
-            } else {
-                $vfunc = sprintf("C++       %s", $func);
-                $groups{type}{'C++'} += $pct;
-                $groups{design}{'C++'} += $pct;
-                $groups{module}{'C++'} += $pct;
-            }
-        }
-        $vfuncs{$vfunc} = $funcs{$func};
-    }
+        design = None
+        for vde in verilated_mods:
+            if verilated_mods[vde].match(func) or verilated_mods[vde].match(
+                    funcarg):
+                design = vde
+                break
+
+        vdesign = "-"
+
+        prof_match = re.search(r'__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(', vfunc)
+        if design and prof_match:
+            linefunc = prof_match.group(1)
+            lineno = int(prof_match.group(2))
+            vfunc = "VBlock    %s:%d" % (linefunc, lineno)
+            vdesign = design
+            groups['type']["Verilog Blocks under " + design] += pct
+            groups['design'][design] += pct
+            groups['module'][linefunc] += pct
+        elif design:
+            vfunc = "VCommon   " + func
+            vdesign = design
+            groups['type']["Common code under " + design] += pct
+            groups['design'][design] += pct
+            groups['module'][design + " common code"] += pct
+        elif re.match(r'(VL_[A-Z0-9_]+|_?vl_[a-zA-Z0-9_]+|Verilated)', vfunc):
+            vfunc = "VLib      " + func
+            groups['type']['VLib'] += pct
+            groups['design']['VLib'] += pct
+            groups['module']['VLib'] += pct
+        elif re.match(r'^_mcount_private', vfunc):
+            vfunc = "Prof      " + func
+            groups['type']['Prof'] += pct
+            groups['design']['Prof'] += pct
+            groups['module']['Prof'] += pct
+        else:
+            vfunc = "C++       " + func
+            groups['type']['C++'] += pct
+            groups['design']['C++'] += pct
+            groups['module']['C++'] += pct
+
+        if vfunc not in vfuncs:
+            vfuncs[vfunc] = funcs[func]
+            vfuncs[vfunc]['design'] = vdesign
+        else:
+            vfuncs[vfunc]['pct'] += funcs[func]['pct']
+            vfuncs[vfunc]['calls'] += funcs[func]['calls']
+            vfuncs[vfunc]['sec'] += funcs[func]['sec']
+
+    for ftype in ['type', 'design', 'module']:
+        missing = 100
+        for item in groups[ftype].keys():
+            missing -= groups[ftype][item]
+        groups[ftype]["\377Unaccounted for/rounding error"] = missing
+
+        print("Overall summary by %s:" % ftype)
+        print("  %-6s  %s" % ("% time", ftype))
+        for what in sorted(groups[ftype].keys()):
+            # \377 used to establish sort order
+            pwhat = re.sub(r'^\377', '', what)
+            print("  %6.2f  %s" % (groups[ftype][what], pwhat))
+        print()
+
+    design_width = 1
+    for func in vfuncs:
+        if design_width < len(vfuncs[func]['design']):
+            design_width = len(vfuncs[func]['design'])
+
+    print("Verilog code profile:")
+    print("   These are split into three categories:")
+    print("      C++:     Time in non-Verilated C++ code")
+    print("      Prof:    Time in profile overhead")
+    print("      VBlock:  Time attributable to a block in a" +
+          " Verilog file and line")
+    print("      VCommon: Time in a Verilated module," +
+          " due to all parts of the design")
+    print("      VLib:    Time in Verilated common libraries," +
+          " called by the Verilated code")
+    print()
+
+    print("  %   cumulative   self              ")
+    print((" time   seconds   seconds      calls   %-" + str(design_width) +
+           "s  type      filename and line number") % "design")
+
+    cume = 0
+    for func in sorted(vfuncs.keys(),
+                       key=lambda f: vfuncs[f]['sec'],
+                       reverse=True):
+        cume += vfuncs[func]['sec']
+        print(("%6.2f %9.2f %8.2f %10d   %-" + str(design_width) + "s  %s") %
+              (vfuncs[func]['pct'], cume, vfuncs[func]['sec'],
+               vfuncs[func]['calls'], vfuncs[func]['design'], func))
 
 
-    foreach my $type (qw(type design module)) {
-        my $missing = 100;
-        foreach (sort (keys %{$groups{$type}})) {
-            $missing -= $groups{$type}{$_};
-        }
-        if ($missing) {
-            $groups{$type}{"\377Unaccounted for/rounding error"} = $missing;
-        }
+######################################################################
+######################################################################
 
-        print("Overall summary by $type:\n");
-        printf("  %-6s  %s\n","% time",$type);
-        foreach my $what (sort (keys %{$groups{$type}})) {
-            (my $pwhat = $what) =~ s/^\377//;  # Just used to establish sort order
-            printf("  %6.2f  %s\n", $groups{$type}{$what}, $pwhat);
-        }
-        print("\n");
-    }
-
-    print("Verilog code profile:\n");
-    print("   These are split into three categories:\n");
-    print("      C++:     Time in non-Verilated C++ code\n");
-    print("      Prof:    Time in profile overhead\n");
-    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
-    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
-    print("      VLib:    Time in Verilated common libraries, called by the Verilated code\n");
-    print("\n");
-
-    print("  %   cumulative   self              \n");
-    print(" time   seconds   seconds    calls   type      filename and line number\n");
-
-    my $cume = 0;
-    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
-                            || $a cmp $b}
-                      (keys %vfuncs)) {
-        $cume += $vfuncs{$func}{sec};
-        printf +("%6.2f %9.2f %8.2f %8d   %s\n",
-                 $vfuncs{$func}{pct},
-                 $cume, $vfuncs{$func}{sec},
-                 $vfuncs{$func}{calls},
-                 $func);
-    }
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_profcfunc - Read gprof report created with --prof-cfuncs
-
-=head1 SYNOPSIS
-
-  verilator --prof-cfuncs ....
-  gcc --ggdb -pg ....
-  {run executable}
-  gprof
-  verilator_profcfuncs gprof.out
-
-=head1 DESCRIPTION
-
-Verilator_profcfunc reads a profile report created by gprof.  The names of
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Read gprof report created with --prof-cfuncs""",
+    epilog=
+    """Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of time, etc,
 in each Verilog block.
 
 For documentation see
-L<https://verilator.org/guide/latest/exe_verilator_profcfuncs.html>.
+https://verilator.org/guide/latest/exe_verilator_profcfunc.html
 
-=head1 ARGUMENT SUMMARY
-
-    <filename>  Input file (gprof.out)
-    --help      Display this help
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2007-2021 by Wilson Snyder. This program is free software; you
+Copyright 2002-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 SEE ALSO
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('filename', help='input gprof output to process')
 
-C<verilator>
-
-and L<https://verilator.org/guide/latest/exe_verilator_profcfuncs.html> for
-detailed documentation.
-
-=cut
+Args = parser.parse_args()
+profcfunc(Args.filename)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_profcfunc  $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree"
-### End:
+# Local Variables:
+# compile-command: "./verilator_profcfunc ../test_regress/t/t_profcfunc.gprof"
+# End:

ci/ci-install.bash

@@ -23,6 +23,12 @@ fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
+if [ "$CI_M32" = "0" ]; then
+  unset CI_M32
+elif [ "$CI_M32" != "1" ]; then
+  fatal "\$CI_M32 must be '0' or '1'";
+fi
+
 if [ "$CI_OS_NAME" = "linux" ]; then
   MAKE=make
 elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -36,7 +42,7 @@ fi
 install-vcddiff() {
   TMP_DIR="$(mktemp -d)"
   git clone https://github.com/veripool/vcddiff "$TMP_DIR"
-  git -C "${TMP_DIR}" checkout 5112f88b7ba8818dce9dfb72619e64a1fc19542c
+  git -C "${TMP_DIR}" checkout e5664be5fe39d353bf3fcb50aa05214ab7ed4ac4
   "$MAKE" -C "${TMP_DIR}"
   sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin
 }
@@ -55,7 +61,7 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
     if [ "$COVERAGE" = 1 ]; then
       yes yes | sudo cpan -fi Parallel::Forker
     fi
-    if [ "$M32" = 1 ]; then
+    if [ "$CI_M32" = 1 ]; then
       sudo apt-get install gcc-multilib g++-multilib
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -82,7 +88,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
       sudo apt-get install libsystemc-dev
     fi
-    if [ "$M32" = 1 ]; then
+    if [ "$CI_M32" = 1 ]; then
       sudo apt-get install lib32z1-dev gcc-multilib g++-multilib
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -101,9 +107,6 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
   fi
   yes yes | sudo cpan -M $CI_CPAN_REPO -fi Parallel::Forker
   install-vcddiff
-
-  autoconf
-  ./configure --enable-longtests --enable-ccwarn
 else
   ##############################################################################
   # Unknown build stage

ci/ci-script.bash

@@ -21,6 +21,12 @@ fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
+if [ "$CI_M32" = "0" ]; then
+  unset CI_M32
+elif [ "$CI_M32" != "1" ]; then
+  fatal "\$CI_M32 must be '0' or '1'";
+fi
+
 if [ "$CI_OS_NAME" = "linux" ]; then
   export MAKE=make
   NPROC=$(nproc)
@@ -40,8 +46,10 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
 
   if [ "$COVERAGE" != 1 ]; then
     autoconf
-    ./configure --enable-longtests --enable-ccwarn
+    ./configure --enable-longtests --enable-ccwarn ${CI_M32:+--enable-m32}
+    ccache -z
     "$MAKE" -j "$NPROC" -k
+    ccache -s
     if [ "$CI_OS_NAME" = "osx" ]; then
       file bin/verilator_bin
       file bin/verilator_bin_dbg
@@ -61,6 +69,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
 
   if [ "$CI_OS_NAME" = "osx" ]; then
     export VERILATOR_TEST_NO_GDB=1  # Pain to get GDB to work on OS X
+    # TODO below may no longer be requried as configure checks for -pg
     export VERILATOR_TEST_NO_GPROF=1  # Apple Clang has no -pg
     # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd
     file bin/verilator_bin
@@ -76,13 +85,15 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     "$MAKE" -j "$NPROC" -k
   elif [ "$CI_OS_NAME" = "freebsd" ]; then
     export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run
+    # TODO below may no longer be requried as configure checks for -pg
     export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable
   fi
 
   # Run sanitize on Ubuntu 20.04 only
-  [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && sanitize='--sanitize' || sanitize=''
+  [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && [ "$CI_M32" = "" ] && sanitize='--sanitize' || sanitize=''
 
   # Run the specified test
+  ccache -z
   case $TESTS in
     dist-vlt-0)
       "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=0/3
@@ -169,6 +180,8 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
       fatal "Unknown test: $TESTS"
       ;;
   esac
+  ccache -s
+
   # Upload coverage data
   if [[ $TESTS == coverage-* ]]; then
     bash <(cat ci/coverage-upload.sh) -f nodist/obj_dir/coverage/app_total.info

codecov.yml

@@ -1,6 +1,6 @@
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2020-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.

configure.ac

@@ -1,20 +1,20 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you
+# Copyright 2003-2022 by Wilson Snyder. Verilator is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[4.204 2021-06-12],
+AC_INIT([Verilator],[4.222 2022-05-02],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 # When releasing, also update header of Changes file
 # and commit using "devel release" or "Version bump" message
 # Then 'make maintainer-dist'
 
-AC_CONFIG_HEADER(src/config_build.h)
+AC_CONFIG_HEADERS(src/config_build.h)
 AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)
 
 # Version
@@ -22,6 +22,8 @@ AC_MSG_RESULT([configuring for $PACKAGE_STRING])
 PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'`
 AC_SUBST(PACKAGE_VERSION_NUMBER)
 AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number])
+VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']`
+AC_SUBST(VERILATOR_VERSION_INTEGER)
 
 # Ignore automake flags passed by Ubuntu builds
 AC_ARG_ENABLE([dependency-tracking],
@@ -35,7 +37,7 @@ AC_ARG_ENABLE([silent-rules],
 AC_MSG_CHECKING(whether to perform partial static linking of Verilator binary)
 AC_ARG_ENABLE([partial-static],
               [AS_HELP_STRING([--disable-partial-static],
-                              [By default, for Verilation peformance, Verilator
+                              [By default, for Verilation performance, Verilator
                                is linked against some of its dependencies
                                statically. Use this to link the Verilator binary
                                fully dynamically.])],
@@ -52,7 +54,7 @@ AC_MSG_CHECKING(whether to use tcmalloc)
 AC_ARG_ENABLE([tcmalloc],
               [AS_HELP_STRING([--enable-tcmalloc],
                               [Use libtcmalloc_minimal for faster dynamic memory
-                               management in Verilator binary@<:@default=check@:>@])],
+                               management in Verilator binary @<:@default=check@:>@])],
               [case "${enableval}" in
                 yes) CFG_WITH_TCMALLOC=yes ;;
                 no)  CFG_WITH_TCMALLOC=no ;;
@@ -61,6 +63,34 @@ AC_ARG_ENABLE([tcmalloc],
               [CFG_WITH_TCMALLOC=check;])
 AC_MSG_RESULT($CFG_WITH_TCMALLOC)
 
+# Flag to enable -m32 build
+AC_MSG_CHECKING(whether to use -m32)
+AC_ARG_ENABLE([m32],
+              [AS_HELP_STRING([--enable-m32],
+                              [Use -m32 for all compilation and link,
+                               including Verialtor and generated models.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_M32=yes ;;
+                no)  CFG_ENABLE_M32=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-m32]) ;;
+               esac],
+               CFG_ENABLE_M32=no)
+AC_MSG_RESULT($CFG_ENABLE_M32)
+
+# Flag to enable coverage build
+AC_MSG_CHECKING(whether to build for coverage collection)
+AC_ARG_ENABLE([coverage],
+              [AS_HELP_STRING([--enable-coverage],
+                              [Build Verilator for code coverage collection.
+                               For developers only.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_COVERAGE=yes ;;
+                no)  CFG_ENABLE_COVERAGE=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-coverage]) ;;
+               esac],
+               CFG_ENABLE_COVERAGE=no)
+AC_MSG_RESULT($CFG_ENABLE_COVERAGE)
+
 # Special Substitutions - CFG_WITH_DEFENV
 AC_MSG_CHECKING(whether to use hardcoded paths)
 AC_ARG_ENABLE([defenv],
@@ -115,10 +145,10 @@ AC_SUBST(CFG_WITH_LONGTESTS)
 AC_MSG_RESULT($CFG_WITH_LONGTESTS)
 
 # Compiler flags (ensure they are not empty to avoid configure defaults)
-CFLAGS+=" "
-CPPFLAGS+=" "
-CXXFLAGS+=" "
-LDFLAGS+=" "
+CFLAGS="$CFLAGS "
+CPPFLAGS="$CPPFLAGS "
+CXXFLAGS="$CXXFLAGS "
+LDFLAGS="$LDFLAGS "
 
 # Checks for programs.
 AC_PROG_CC
@@ -135,6 +165,11 @@ AC_RUN_IFELSE(
     AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]),
     AC_MSG_RESULT(yes))
 
+AC_CHECK_PROG(AR,ar,ar)
+if test "x$AR" = "x" ; then
+   AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it])
+fi
+
 AC_PATH_PROG(PERL,perl)
 if test "x$PERL" = "x" ; then
    AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
@@ -211,24 +246,34 @@ AC_DEFUN([_MY_CXX_CHECK_FLAG],
     CXXFLAGS="$ACO_SAVE_CXXFLAGS"
    ])
 
+AC_DEFUN([_MY_CXX_CHECK_IFELSE],
+   [# _MY_CXX_CHECK_IFELSE(option,action-if-supported,action-if-not-supported)
+    # Check if compiler supports specific option. If it does,
+    # do action-if-supported, otherwise do action-if-not-supported
+    _MY_CXX_CHECK_FLAG($1)
+    if test "$_my_result" = "yes" ; then
+      true
+      $2
+    else
+      true
+      $3
+    fi
+   ])
+
 AC_DEFUN([_MY_CXX_CHECK_SET],
-   [# _MY_CXX_CHECK_SET(variable,flag) -- Check if compiler supports specific options
-    # If it does, set variable to flag, only if not previously set
+   [# _MY_CXX_CHECK_SET(variable,option)
+    # Check if compiler supports specific option. If it does,
+    # set variable to option, only if not previously set.
     if test "$$1" = ""; then
-       _MY_CXX_CHECK_FLAG($2)
-       if test "$_my_result" = "yes" ; then
-          $1="$2"
-       fi
+       _MY_CXX_CHECK_IFELSE($2, $1="$2")
     fi
    ])
 
 AC_DEFUN([_MY_CXX_CHECK_OPT],
-   [# _MY_CXX_CHECK_OPT(flag) -- Check if compiler supports specific options
-    # If it does, append flag to variable
-    _MY_CXX_CHECK_FLAG($2)
-    if test "$_my_result" = "yes" ; then
-       $1="$$1 $2"
-    fi
+   [# _MY_CXX_CHECK_OPT(variable,option)
+    # Check if compiler supports specific option. If it does,
+    # append option to variable
+    _MY_CXX_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
 AC_DEFUN([_MY_LDLIBS_CHECK_FLAG],
@@ -270,35 +315,52 @@ AC_DEFUN([_MY_LDLIBS_CHECK_OPT],
     _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
+# When using -m32. Check this first as later checks may fail with the -m32 flag.
+if test "$CFG_ENABLE_M32" = "yes"; then
+  _MY_CXX_CHECK_IFELSE(
+    -m32,
+    [CXX="$CXX -m32"],
+    [AC_MSG_ERROR([--enable-m32 was given but compiler does not support -m32])])
+fi
+
+# Similarly, add the coverage flags early as they influence later checks.
+if test "$CFG_ENABLE_COVERAGE" = "yes"; then
+  _MY_CXX_CHECK_OPT(CXX,--coverage)
+  # Otherwise inline may not show as uncovered
+  #  If we use this then e.g. verilated.h functions properly show up
+  #  if unused.
+  #  However, VerilatedSerialize::write then changes from covered
+  #  to uncovered (in G++ 9.3.0) even with all inlining turned off.
+  #  Having false negative coverage is more effort then missing negatives.
+  #  Also this seems to explode the runtime (since a lot more data).
+  #  _MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions)
+  # Otherwise static may not show as uncovered
+  _MY_CXX_CHECK_OPT(CXX,-fkeep-static-functions)
+  # Exceptions can pollute the branch coverage data
+  _MY_CXX_CHECK_OPT(CXX,-fno-exceptions)
+  # Define-out some impossible stuff
+  _MY_CXX_CHECK_OPT(CXX,-DVL_GCOV)
+fi
+
+# Compiler flags to enable profiling
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PROFILE,-pg)
+AC_SUBST(CFG_CXXFLAGS_PROFILE)
+
 # Flag to select newest language standard supported
 # Macros work such that first option that passes is the one we take
-# Currently enabled gnu++14/c++14 due to packaged SystemC dependency
-# gnu++17 is the newest that Verilator supports
-# std++03 is the oldest that Verilator supports
+# Currently enabled c++14 due to packaged SystemC dependency
+# c++14 is the newest that Verilator is regressed to support
+# c++11 is the oldest that Verilator supports
+# gnu is requried for Cygwin to compile verilated.h successfully
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++03)
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20)
+#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++03)
 AC_SUBST(CFG_CXXFLAGS_STD_NEWEST)
-# And likewise oldest standard (same list above, backwards)
-# This is used for internal testing
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++03)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++14)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++17)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++20)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++03)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++14)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++17)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++20)
-AC_SUBST(CFG_CXXFLAGS_STD_OLDEST)
 
 # Flags for compiling Verilator internals including parser, and Verilated files
 # These turn on extra warnings and are only used with 'configure --enable-ccwarn'
@@ -322,6 +384,18 @@ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-parentheses-equality)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-unused)
 AC_SUBST(CFG_CXXFLAGS_PARSER)
 
+# Flags for compiling the debug version of Verilator (in addition to above CFG_CXXFLAGS_SRC)
+if test "$CFG_ENABLE_COVERAGE" = "no"; then # Do not optimize for the coverage build
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-Og)
+fi
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-ggdb)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-gz)
+AC_SUBST(CFG_CXXFLAGS_DEBUG)
+
+# Flags for linking the debug version of Verilator (in addition to above CFG_LDFLAGS_SRC)
+_MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_DEBUG,-gz)
+AC_SUBST(CFG_LDFLAGS_DEBUG)
+
 # Flags for Verilated makefile
 # For example, -Wno-div-by-zero isn't in 4.1.2
 # Random code often does / 0.  Unfortunately VL_DIV_I(0,0) will warn

docs/CONTRIBUTORS

@@ -3,37 +3,48 @@ under the Developer Certificate of Origin (https://developercertificate.org/).
 
 Please see the Verilator manual for 200+ additional contributors. Thanks to all.
 
+Adrien Le Masle
 Ahmed El-Mahmoudy
 Alex Chadwick
 Àlex Torregrosa
+Aliaksei Chapyzhenka
 Ameya Vikram Singh
 Andreas Kuster
 Chris Randall
+Chuxuan Wang
 Conor McCullough
 Dan Petrisko
+Daniel Bates
 David Horton
 David Metz
 David Stanford
 David Turner
+Drew Ranck
 Drew Taussig
 Driss Hafdi
 Edgar E. Iglesias
 Eric Rippey
 Fan Shupei
+Felix Yan
 Garrett Smith
 Geza Lore
 Gianfranco Costamagna
 Glen Gibb
 Graham Rushton
+Guokai Chen
 Harald Heckmann
 Howard Su
 Huang Rui
+HungMingWu
 HyungKi Jeong
+Iru Cai
+Ivan Vnučec
 Iztok Jeras
 James Hanlon
 James Hutchinson
 James Pallister
 Jamey Hicks
+Jamie Iles
 Jan Van Winkel
 Jean Berniolles
 Jeremy Bennett
@@ -41,12 +52,16 @@ John Coiner
 John Demme
 Jonathan Drolet
 Josh Redford
+Julie Schwartz
 Julien Margetts
 Kaleb Barrett
+Kamil Rakoczy
 Kanad Kanhere
+Keith Colbert
 Kevin Kiningham
 Krzysztof Bieganski
 Kuba Ober
+Larry Doolittle
 Ludwig Rogiers
 Lukasz Dalek
 Maarten De Braekeleer
@@ -58,6 +73,7 @@ Marshal Qiao
 Martin Schmidt
 Matthew Ballance
 Michael Killough
+Michaël Lefebvre
 Mike Popoloski
 Miodrag Milanović
 Morten Borup Petersen
@@ -74,6 +90,7 @@ Pieter Kapsenberg
 Piotr Binkowski
 Qingyao Sun
 Rafal Kapuscik
+Raynard Qiao
 Richard Myers
 Rupert Swarbrick
 Samuel Riedel
@@ -82,6 +99,8 @@ Sebastien Van Cauwenberghe
 Sergi Granell
 Stefan Wallentowitz
 Stephen Henry
+Steven Hugg
+Teng Huang
 Tim Snyder
 Tobias Rosenkranz
 Tobias Wölfel
@@ -94,7 +113,10 @@ Vassilis Papaefstathiou
 Veripool API Bot
 Victor Besyakov
 Wilson Snyder
+Xi Zhang
+Yoda Lee
 Yossi Nivin
 Yuri Victorovich
 Yutetsu TAKATSUKASA
 Yves Mathieu
+Zhanglei Wang

docs/Makefile

@@ -5,7 +5,7 @@
 #
 # Code available from: https://verilator.org
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.

docs/_static/css/vlt_sphinx.css

@@ -1,16 +1,25 @@
-/*Verilator blue #008fd7; set in html*/
+/* Verilator blue #008fd7; set in html */
+
 .wy-side-nav-search > div.version {
-    color: #111;
+  color: #111;
 }
-.fa-github::before, .icon-github::before {
-    content: "";
+
+.fa-github::before,
+.icon-github::before {
+  content: "";
 }
-.fa-home::before, .icon-home::before {
-    content: "";
+
+.fa-home::before,
+.icon-home::before {
+  content: "";
 }
-.fa-arrow-circle-right::before, .icon-circle-arrow-right::before {
-    content: "";
+
+.fa-arrow-circle-right::before,
+.icon-circle-arrow-right::before {
+  content: "";
 }
-.fa-arrow-circle-left::before, .icon-circle-arrow-left::before {
-    content: "";
+
+.fa-arrow-circle-left::before,
+.icon-circle-arrow-left::before {
+  content: "";
 }

docs/bin/vl_sphinx_extract

@@ -40,7 +40,7 @@ parser = argparse.ArgumentParser(
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Read a file and extract documentation data.""",
     epilog=
-    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+    """ Copyright 2021-2022 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

docs/bin/vl_sphinx_fix

@@ -55,7 +55,7 @@ parser = argparse.ArgumentParser(
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Post-process Sphinx HTML.""",
     epilog=
-    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+    """ Copyright 2021-2022 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

docs/gen/ex_DIDNOTCONVERGE_faulty.rst

@@ -0,0 +1,6 @@
+.. comment: generated by t_lint_didnotconverge_bad
+.. code-block:: sv
+   :linenos:
+
+      always_comb b = ~a;
+      always_comb a = b;

docs/gen/ex_DIDNOTCONVERGE_msg.rst

@@ -0,0 +1,7 @@
+.. comment: generated by t_lint_didnotconverge_bad
+.. code-block::
+
+   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request
+   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request_1
+   -V{t#,#}        CHANGE: t/t_lint_didnotconverge_bad.v:14: a
+   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge

docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_didnotconverge_nodbg_bad
+.. code-block::
+
+   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge

docs/gen/ex_STMTDLY_faulty.rst

@@ -0,0 +1,5 @@
+.. comment: generated by t_lint_stmtdly_bad
+.. code-block:: sv
+   :emphasize-lines: 1
+
+         #100 $finish;  //<--- Warning

docs/gen/ex_STMTDLY_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_stmtdly_bad
+.. code-block::
+
+   %Warning-STMTDLY: example.v:1:8 Unsupported: Ignoring delay on this delayed statement.

docs/guide/changes.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ****************

docs/guide/conf.py

@@ -1,4 +1,4 @@
-# pylint: disable=C0103,C0114,C0116,E0402,W0622
+# pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
 #
 # Configuration file for Verilator's Sphinx documentation builder.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -36,7 +36,7 @@ def setup(app):
 # -- Project information
 
 project = 'Verilator'
-copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
+copyright = '2022 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
 author = 'Wilson Snyder'
 
 # The master toctree document.

docs/guide/connecting.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Connecting:
@@ -7,22 +7,86 @@
 Connecting to Verilated Models
 ******************************
 
+Structure of the Verilated Model
+================================
+
+Verilator outputs a :file:`{prefix}.h` header file which defines a class
+named :code:`{prefix}` which represents the generated model the user is
+supposed to instantiate.  This model class defines the interface of the
+Verilated model.
+
+Verilator will additionally create a :file:`{prefix}.cpp` file, together
+with additional .h and .cpp files for internals.  See the :file:`examples`
+directory in the kit for examples.  See :ref:`Files Read/Written` for
+information on all the files Verilator might output.
+
+The output of Verilator will contain a :file:`{prefix}.mk` file that may be
+used with Make to build a :file:`{prefix}__ALL.a` library with all required
+objects in it.
+
+The generated model class file manages all internal state required by the
+model, and exposes the following interface that allows interaction with the
+model:
+
+* Top level IO ports are exposed as references to the appropriate internal
+  equivalents.
+
+* Public top level module instances are exposed as pointers to allow access
+  to :code:`/* verilator public */` items.
+
+* The root of the design hierarchy (as in SystemVerilog :code:`$root`) is
+  exposed via the :code:`rootp` member pointer to allow access to model
+  internals, including :code:`/* verilator public_flat */` items.
+
+
+.. _Porting from pre 4.210:
+
+Model interface changes in version 4.210
+------------------------------------------
+
+Starting from version 4.210, the model class is an interface object.
+
+Up until Verilator version 4.204 inclusive, the generated model class was
+also the instance of the top level instance in the design hierarchy (what
+you would refer to with :code:`$root` in SystemVerilog).  This meant that
+all internal variables that were implemented by Verilator in the root scope
+were accessible as members of the model class itself.  Note there were often
+many such variable due to module inlining, including :code:`/* verilator
+public_flat */` items.
+
+This means that user code that accesses internal signals in the model
+(likely including :code:`/* verilator public_flat */` signals, as they are
+often inlined into the root scope) will need to be updated as follows:
+
+* No change required for accessing top level IO signals. These are directly
+  accessible in the model class via references.
+
+* No change required for accessing :code:`/* verilator public */` items.
+  These are directly accessible via sub-module pointers in the model class.
+
+* Accessing any other internal members, including
+  :code:`/* verilator public_flat */` items requires the following changes:
+
+  * Additionally include :file:`{prefix}___024root.h`. This header defines
+    type of the :code:`rootp` pointer within the model class. Note the
+    :code:`__024` substring is the Verilator escape sequence for the
+    :code:`$` character, i.e.: :code:`rootp` points to the Verilated
+    SystemVerilog :code:`$root` scope.
+
+  * Replace :code:`modelp->internal->member->lookup` references with
+    :code:`modelp->rootp->internal->member->lookup` references, which
+    contain one additional indirection via the :code:`rootp` pointer.
+
+
 .. _Connecting to C++:
 
 Connecting to C++
 =================
 
-Verilator creates a :file:`{prefix}.h` and :file:`{prefix}.cpp` file for
-the top level module, together with additional .h and .cpp files for
-internals. See the :file:`examples` directory in the kit for examples.  See
-:ref:`Files Read/Written` for information on all the files it writes.
-
-After the model is created, there will be a :file:`{prefix}.mk` file that
-may be used with Make to produce a :file:`{prefix}__ALL.a` file with all
-required objects in it.
-
-The user must write a C++ wrapper and main loop for the simulation, to link
-with the Verilated model.  Here is a simple example:
+In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
+simple C++ class.  The user must write a C++ wrapper and main loop for the
+simulation, which instantiates the model class, and link with the Verilated
+model.  Here is a simple example:
 
 .. code-block:: C++
 
@@ -30,9 +94,9 @@ with the Verilated model.  Here is a simple example:
          #include <iostream>             // Need std::cout
          #include "Vtop.h"               // From Verilating "top.v"
 
-         Vtop *top;                      // Instantiation of module
+         Vtop *top;                      // Instantiation of model
 
-         vluint64_t main_time = 0;       // Current simulation time
+         uint64_t main_time = 0;       // Current simulation time
          // This is a 64-bit integer to reduce wrap over issues and
          // allow modulus.  This is in units of the timeprecision
          // used in Verilog (or from --timescale-override)
@@ -45,7 +109,7 @@ with the Verilated model.  Here is a simple example:
          int main(int argc, char** argv) {
              Verilated::commandArgs(argc, argv);   // Remember args
 
-             top = new Vtop;             // Create instance
+             top = new Vtop;             // Create model
 
              top->reset_l = 0;           // Set some inputs
 
@@ -70,27 +134,28 @@ with the Verilated model.  Here is a simple example:
          }
 
 
-Note signals are read and written as member variables of the model.  You
-call the :code:`eval()` method to evaluate the model.  When the simulation
-is complete call the :code:`final()` method to execute any SystemVerilog
-final blocks, and complete any assertions. See :ref:`Evaluation Loop`.
+Note top level IO signals are read and written as members of the model.  You
+call the :code:`eval()` method to evaluate the model.  When the simulation is
+complete call the :code:`final()` method to execute any SystemVerilog final
+blocks, and complete any assertions. See :ref:`Evaluation Loop`.
 
 
 Connecting to SystemC
 =====================
 
-Verilator will convert the top level module to a SC_MODULE.  This module
-will attach directly into a SystemC netlist as an instantiation.
+In SystemC output mode (:vlopt:`--sc`), the Verilator generated model class
+is a SystemC SC_MODULE.  This module will attach directly into a SystemC
+netlist as an instantiation.
 
 The SC_MODULE gets the same pinout as the Verilog module, with the
 following type conversions: Pins of a single bit become bool.  Pins 2-32
 bits wide become uint32_t's.  Pins 33-64 bits wide become sc_bv's or
-vluint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
+uint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
 become sc_bv's.  (Uints simulate the fastest so are used where possible.)
 
-Lower modules are not pure SystemC code.  This is a feature, as using the
-SystemC pin interconnect scheme everywhere would reduce performance by an
-order of magnitude.
+Model internals, including lower level sub-modules are not pure SystemC
+code.  This is a feature, as using the SystemC pin interconnect scheme
+everywhere would reduce performance by an order of magnitude.
 
 
 Direct Programming Interface (DPI)
@@ -135,7 +200,7 @@ DPI System Task/Functions
 -------------------------
 
 Verilator extends the DPI format to allow using the same scheme to
-efficiently add system functions.  Simply use a dollar-sign prefixed system
+efficiently add system functions.  Use a dollar-sign prefixed system
 function name for the import, but note it must be escaped.
 
 .. code-block:: sv
@@ -192,7 +257,9 @@ with respect to that top level module, then the scope could be set with
 
      #include "svdpi.h"
      ...
-     svSetScope(svGetScopeFromName("TOP.dut"));
+     const svScope scope = svGetScopeFromName("TOP.dut");
+     assert(scope);  // Check for nullptr if scope not found
+     svSetScope(scope);
 
 (Remember that Verilator adds a "TOP" to the top of the module hierarchy.)
 
@@ -357,12 +424,12 @@ accesses the above signal "readme" would be:
 
 .. code-block:: bash
 
-     cat >sim_main.cpp <<'<<EOF'
+     cat >sim_main.cpp <<'EOF'
        #include "Vour.h"
        #include "verilated.h"
        #include "verilated_vpi.h"  // Required to get definitions
 
-       vluint64_t main_time = 0;   // See comments in first example
+       uint64_t main_time = 0;   // See comments in first example
        double sc_time_stamp() { return main_time; }
 
        void read_and_check() {
@@ -441,7 +508,7 @@ structure.  If a ``VerilatedContext`` is not created prior to creating a
 model, a default global one is created automatically.
 
 The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
-shown above, simply call VerilatedContext methods using the default global
+shown above, call VerilatedContext methods using the default global
 VerilatedContext.  (Technically they operate on the last one used by a
 given thread.)  If you are using multiple simulation contexts you should
 not use the Verilated:: methods, and instead always use VerilatedContext

docs/guide/contributing.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************************

docs/guide/contributors.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ************************
@@ -13,7 +13,8 @@ When possible, please instead report bugs at `Verilator Issues
 
 Primary author is Wilson Snyder <[email protected]>.
 
-Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu.
+Major concepts by Paul Wasson, Duane Galbi, John Coiner, Geza Lore, Yutetsu
+Takatsukasa, and Jie Xu.
 
 
 Contributors
@@ -22,14 +23,14 @@ Contributors
 Many people have provided ideas and other assistance with Verilator.
 
 Verilator is receiving major development support from the `CHIPS Alliance
-<https://chipsalliance.org>`_.
+<https://chipsalliance.org>`_ and `Shunyao CAD <https://shunyaocad.com>`_.
 
 Previous major corporate sponsors of Verilator, by providing significant
 contributions of time or funds included include: Atmel Corporation, Cavium
 Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
 Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
 Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
-and SiCortex Inc.
+SiCortex Inc, and Shunyao CAD.
 
 The people who have contributed major functionality are: Byron Bradley,
 Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd

docs/guide/copyright.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********
@@ -8,7 +8,7 @@ Copyright
 The latest version of Verilator is available from `https://verilator.org
 <https://verilator.org>`_.
 
-Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

docs/guide/deprecations.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Deprecations
@@ -9,20 +9,24 @@ The following deprecated items are scheduled for future removal:
 C++11 compiler support
   Verilator currently requires C++11 or newer compilers.  Verilator will
   require C++14 or newer compilers for both compiling Verilator and
-  compiling Verilated models no sooner than January 2022.
+  compiling Verilated models no sooner than January 2023.
 
-No-Relative-Cfuncs Option
-  The :vlopt:`--no-relative-cfuncs` option is not be required by any C++11
-  compliant compiler and is planned for removal no sooner than July 2021.
+Verilated_heavy.h
+  The legacy "verilated_heavy.h" include was replaced with just including
+  "verilated.h". Verilated_heavy.h is planned for removal no sooner than
+  July 2022.
 
-Inhibit-Sim Option
-  The :vlopt:`--inhibit-sim` option is planned for removal no sooner than
-  July 2021.
+Option `--cdc`
+  The experimental `--cdc` option is believed to be generally unused and is
+  planned for removal no sooner than January 2023.
 
-Configuration File -msg
-  The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule"
-  option.  "-msg" is planned for removal no sooner than January 2021.
+Option `--prof-threads`
+  The `--prof-threads` option has been superseded by the `--prof-exec` and
+  `--prof-pgo` options and is planned for removal no sooner than April 2023.
 
-XML locations
-  The XML "fl" attribute has been replaced with the "loc" attribute.  "fl"
-  is planned for removal no sooner than January 2021.
+Verilated model options `+verilator+prof+threads+*`
+  The `+verilator+prof+threads+start`, `+verilator+prof+threads+window` and
+  `+verilator+prof+threads+file` options have been superseded by the
+  `+verilator+prof+exec+start`, `+verilator+prof+exec+window` and
+  `+verilator+prof+exec+file` options respectively and are planned for removal
+  no sooner than April 2023.

docs/guide/environment.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Environment

docs/guide/example_cc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example C++ Execution:

docs/guide/example_common_install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 First you need Verilator installed, see :ref:`Installation`. In brief, if

docs/guide/example_dist.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Examples in the Distribution:

docs/guide/example_sc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example SystemC Execution:

docs/guide/examples.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Examples:

docs/guide/exe_sim.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Simulation Runtime Arguments:
@@ -38,30 +38,48 @@ Summary:
 
    Display help and exit.
 
-.. option:: +verilator+prof+threads+file+<filename>
+.. option:: +verilator+prof+exec+file+<filename>
 
-   When a model was Verilated using :vlopt:`--prof-threads`, sets the
+   When a model was Verilated using :vlopt:`--prof-exec`, sets the
    simulation runtime filename to dump to.  Defaults to
-   :file:`profile_threads.dat`.
+   :file:`profile_exec.dat`.
 
-.. option:: +verilator+prof+threads+start+<value>
+.. option:: +verilator+prof+exec+start+<value>
 
-   When a model was Verilated using :vlopt:`--prof-threads`, the simulation
+   When a model was Verilated using :vlopt:`--prof-exec`, the simulation
    runtime will wait until $time is at this value (expressed in units of
    the time precision), then start the profiling warmup, then
    capturing. Generally this should be set to some time that is well within
    the normal operation of the simulation, i.e. outside of reset. If 0, the
    dump is disabled. Defaults to 1.
 
-.. option:: +verilator+prof+threads+window+<value>
+.. option:: +verilator+prof+exec+window+<value>
 
-   When a model was Verilated using :vlopt:`--prof-threads`, after $time
-   reaches :vlopt:`+verilator+prof+threads+start+\<value\>`, Verilator will
+   When a model was Verilated using :vlopt:`--prof-exec`, after $time
+   reaches :vlopt:`+verilator+prof+exec+start+\<value\>`, Verilator will
    warm up the profiling for this number of eval() calls, then will capture
    the profiling of this number of eval() calls.  Defaults to 2, which
    makes sense for a single-clock-domain module where it's typical to want
    to capture one posedge eval() and one negedge eval().
 
+.. option:: +verilator+prof+threads+file+<filename>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+file+\<filename\>`
+
+.. option:: +verilator+prof+threads+start+<value>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+start+\<value\>`
+
+.. option:: +verilator+prof+threads+window+<value>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\<filename\>`
+
+.. option:: +verilator+prof+vlt+file+<filename>
+
+   When a model was Verilated using :vlopt:`--prof-pgo`, sets the
+   profile-guided optimization data runtime filename to dump to.  Defaults
+   to :file:`profile.vlt`.
+
 .. option:: +verilator+rand+reset+<value>
 
    When a model was Verilated using :vlopt:`--x-initial unique

docs/guide/exe_verilator.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator Arguments
@@ -99,10 +99,10 @@ Summary:
 .. option:: --bbox-sys
 
    Black box any unknown $system task or function calls.  System tasks will
-   simply become no-operations, and system functions will be replaced with
-   unsized zero.  Arguments to such functions will be parsed, but not
-   otherwise checked.  This prevents errors when linting in the presence of
-   company specific PLI calls.
+   become no-operations, and system functions will be replaced with unsized
+   zero.  Arguments to such functions will be parsed, but not otherwise
+   checked.  This prevents errors when linting in the presence of company
+   specific PLI calls.
 
    Using this argument will likely cause incorrect simulation.
 
@@ -158,41 +158,26 @@ Summary:
 
 .. option:: --clk <signal-name>
 
-   Sometimes it is quite difficult for Verilator to distinguish clock
-   signals from other data signals. Occasionally the clock signals can end
-   up in the checking list of signals which determines if further
-   evaluation is needed. This will heavily degrade the performance of a
-   Verilated model.
-
    With :vlopt:`--clk`, the specified signal-name is taken as a root clock
-   into the model, then Verilator will mark the signal as clocker and
-   propagate the clocker attribute automatically to other signals derived
-   from that. In this way, Verilator will try to avoid taking the clocker
-   signal into checking list.
+   into the model; Verilator will mark the signal as clocker and
+   propagate the clocker attribute automatically to other signals downstream in
+   that clock tree.
 
-   Note signal-name is specified by the RTL hierarchy path. For example,
-   v.foo.bar.  If the signal is the input to top-module, the directly the
-   signal name. If you find it difficult to find the exact name, try to use
-   a :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the
+   The provided signal-name is specified using a RTL hierarchy path. For
+   example, v.foo.bar.  If the signal is the input to top-module, then
+   directly provide the signal name. Alternatively, use a
+   :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the
    signal directly.
 
-   If clock signals are assigned to vectors and then later used
-   individually, Verilator will attempt to decompose the vector and connect
-   the single-bit clock signals directly.  This should be transparent to
-   the user.
+   If clock signals are assigned to vectors and then later used as
+   individual bits, Verilator will attempt to decompose the vector and
+   connect the single-bit clock signals.
 
-.. option:: --make <build-tool>
-
-   Generates a script for the specified build tool.
-
-   Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake.
-   Both can be specified together.  If no build tool is specified, gmake is
-   assumed.  The executable of gmake can be configured via environment
-   variable "MAKE".
-
-   When using :vlopt:`--build` Verilator takes over the responsibility of
-   building the model library/executable.  For this reason :option:`--make`
-   cannot be specified when using :vlopt:`--build`.
+   The clocker attribute is useful in cases where Verilator does not
+   properly distinguish clock signals from other data signals. Using
+   clocker will cause the signal indicated to be considered a clock, and
+   remove it from the combinatorial logic reevaluation checking code. This
+   may greatly improve performance.
 
 .. option:: --compiler <compiler-name>
 
@@ -527,14 +512,6 @@ Summary:
 
    See :vlopt:`-y`.
 
-.. option:: --inhibit-sim
-
-   Rarely needed and deprecated.  Create a :code:`inhibitSim(bool)`
-   function to enable and disable evaluation.  This allows an upper level
-   testbench to disable modules that are not important in a given
-   simulation, without needing to recompile or change the SystemC modules
-   instantiated.
-
 .. option:: --inline-mult <value>
 
    Tune the inlining of modules.  The default value of 2000 specifies that up
@@ -544,6 +521,14 @@ Summary:
    times, but potentially faster simulation speed.  This setting is ignored
    for very small modules; they will always be inlined, if allowed.
 
+.. option:: --instr-count-dpi <value>
+
+   Assumed dynamic instruction count of the average DPI import. This is used
+   by the partitioning algorithm when creating a multithread model. The
+   default value is 200. Adjusting this to an appropriate value can yield
+   performance improvements in multithreaded models. Ignored when creating a
+   single threaded model.
+
 .. option:: -j [<value>]
 
    Specify the level of parallelism for :vlopt:`--build`. The <value> must
@@ -590,6 +575,23 @@ Summary:
    "+libext+" is fairly standard across Verilog tools.  Defaults to
    ".v+.sv".
 
+.. option:: --lib-create <name>
+
+   Produces C++, Verilog wrappers and a Makefile which can in turn produce
+   a DPI library which can be used by Verilator or other simulators along
+   with the corresponding Verilog wrapper.  The Makefile will build both a
+   static and dynamic version of the library named :file:`lib<name>.a` and
+   :file:`lib<name>.so` respectively.  This is done because some simulators
+   require a dynamic library, but the static library is arguably easier to
+   use if possible.  :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`.
+
+   When using :vlopt:`--lib-create` it is advised to also use
+   :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the
+   model has a time resolution that is always compatible with the time
+   precision of the upper instantiating module.
+
+   See also :vlopt:`--protect-lib`.
+
 .. option:: --lint-only
 
    Check the files for lint violations only, do not create any other
@@ -601,6 +603,19 @@ Summary:
    If the design is not to be completely Verilated see also the
    :vlopt:`--bbox-sys` and :vlopt:`--bbox-unsup` options.
 
+.. option:: --make <build-tool>
+
+   Generates a script for the specified build tool.
+
+   Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake.
+   Both can be specified together.  If no build tool is specified, gmake is
+   assumed.  The executable of gmake can be configured via environment
+   variable "MAKE".
+
+   When using :vlopt:`--build` Verilator takes over the responsibility of
+   building the model library/executable.  For this reason :option:`--make`
+   cannot be specified when using :vlopt:`--build`.
+
 .. option:: -MAKEFLAGS <string>
 
    When using :vlopt:`--build`, add the specified argument to the invoked
@@ -633,6 +648,13 @@ Summary:
    The directory is created if it does not exist and the parent directories
    exist; otherwise manually create the Mdir before calling Verilator.
 
+.. option:: --no-merge-const-pool
+
+   Rarely needed.  In order to minimize cache footprint, values of different
+   data type, that are yet emitted identically in C++ are merged in the
+   constant pool.  This option disables this and causes every constant pool
+   entry with a distinct data type to be emitted separately.
+
 .. option:: --mod-prefix <topname>
 
    Specifies the name to prepend to all lower level classes.  Defaults to
@@ -654,10 +676,6 @@ Summary:
 
    Backward compatible alias for :vlopt:`--pins-bv 33 <--pins-bv>`.
 
-.. option:: --no-relative-cfuncs
-
-   Deprecated.
-
 .. option:: --no-skip-identical =item --skip-identical
 
    Rarely needed.  Disables or enables skipping execution of Verilator if
@@ -750,7 +768,7 @@ Summary:
 .. option:: --pins-bv <width>
 
    Specifies SystemC inputs/outputs of greater than or equal to <width>
-   bits wide should use sc_bv's instead of uint32/vluint64_t's.  The
+   bits wide should use sc_bv's instead of uint32/uint64_t's.  The
    default is "--pins-bv 65", and the value must be less than or equal
    to 65.  Versions before Verilator 3.671 defaulted to "--pins-bv 33".
    The more sc_bv is used, the worse for performance.  Use the
@@ -808,6 +826,13 @@ Summary:
    prepended to the name of the :vlopt:`--top` option, or V prepended to
    the first Verilog filename passed on the command line.
 
+.. option:: --prof-c
+
+   When compiling the C++ code, enable the compiler's profiling flag
+   (e.g. :code:`g++ -pg`). See :ref:`Profiling`.
+
+   Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`.
+
 .. option:: --prof-cfuncs
 
    Modify the created C++ functions to support profiling.  The functions
@@ -818,10 +843,21 @@ Summary:
    came from.  This allows gprof or oprofile reports to be correlated with
    the original Verilog source statements. See :ref:`Profiling`.
 
+   Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`.
+
+.. option:: --prof-exec
+
+   Enable collection of execution trace, that can be convered into a gantt
+   chart with verilator_gantt See :ref:`Execution Profiling`.
+
+.. option:: --prof-pgo
+
+   Enable collection of profiling data for profile guided verilation. Currently
+   this is only useful with :vlopt:`--threads`. See :ref:`Thread PGO`.
+
 .. option:: --prof-threads
 
-   Enable gantt chart data collection for threaded builds. See :ref:`Thread
-   Profiling`.
+   Deprecated. Same as --prof-exec and --prof-pgo together.
 
 .. option:: --protect-key <key>
 
@@ -857,29 +893,20 @@ Summary:
 
    Using DPI imports/exports is allowed and generally relatively safe in
    terms of information disclosed, which is limited to the DPI function
-   prototyptes.  Use of the VPI is not recommended as many design details
+   prototypes.  Use of the VPI is not recommended as many design details
    may be exposed, and an INSECURE warning will be issued.
 
 .. option:: --protect-lib <name>
 
-   Produces C++, Verilog wrappers and a Makefile which can in turn produce
-   a DPI library which can be used by Verilator or other simulators along
-   with the corresponding Verilog wrapper.  The Makefile will build both a
-   static and dynamic version of the library named :file:`lib<name>.a` and
-   :file:`lib<name>.so` respectively.  This is done because some simulators
-   require a dynamic library, but the static library is arguably easier to
-   use if possible.  :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`.
+   Produces a DPI library similar to :vlopt:`--lib-create`, but hides
+   internal design details.  :vlopt:`--protect-lib` implies
+   :vlopt:`--protect-ids`, and :vlopt:`--lib-create`.
 
    This allows for the secure delivery of sensitive IP without the need for
    encrypted RTL (i.e. IEEE P1735).  See :file:`examples/make_protect_lib`
    in the distribution for a demonstration of how to build and use the DPI
    library.
 
-   When using :vlopt:`--protect-lib` it is advised to also use
-   :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the
-   model has a time resolution that is always compatible with the time
-   precision of the upper instantiating module.
-
 .. option:: --private
 
    Opposite of :vlopt:`--public`.  Is the default; this option exists for
@@ -1040,6 +1067,8 @@ Summary:
      Verilator assumes DPI pure imports are threadsafe, but non-pure DPI
      imports are not.
 
+   See also :vlopt:`--instr-count-dpi` option.
+
 .. option:: --threads-max-mtasks <value>
 
    Rarely needed.  When using :vlopt:`--threads`, specify the number of
@@ -1153,9 +1182,9 @@ Summary:
 
 .. option:: --trace-underscore
 
-   Enable tracing of signals that start with an underscore. Normally, these
-   signals are not output during tracing.  See also
-   :vlopt:`--coverage-underscore` option.
+   Enable tracing of signals or modules that start with an
+   underscore. Normally, these signals are not output during tracing.  See
+   also :vlopt:`--coverage-underscore` option.
 
 .. option:: -U<var>
 
@@ -1344,9 +1373,10 @@ Summary:
    .. note::
 
       This option applies only to values which are explicitly written as X
-      in the Verilog source code. Initial values of clocks are set to 0
-      unless `--x-initial-edge` is specified. Initial values of all other
-      state holding variables are controlled with `--x-initial`.
+      in modules (not classes) in the Verilog source code. Initial values
+      of clocks are set to 0 unless `--x-initial-edge` is
+      specified. Initial values of all other state holding variables are
+      controlled with `--x-initial`.
 
 .. option:: --x-initial 0
 
@@ -1492,9 +1522,9 @@ The grammar of configuration commands is as follows:
 
 .. option:: no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
 
-   Indicate the signal is used as clock or not. This information is used by
-   Verilator to mark the signal as clocker and propagate the clocker
-   attribute automatically to derived signals. See :vlopt:`--clk`.
+   Indicates that the signal is used as clock or not. This information is
+   used by Verilator to mark the signal and any derived signals as
+   clocker.  See :vlopt:`--clk`.
 
    Same as :option:`/*verilator&32;clocker*/` metacomment.
 
@@ -1508,6 +1538,14 @@ The grammar of configuration commands is as follows:
 
    Same as :option:`/*verilator&32;coverage_block_off*/` metacomment.
 
+.. option:: forceable -module "<modulename>" -var "<signame>"
+
+   Generate public `<signame>__VforceEn` and `<signame>__VforceVal` signals
+   that can be used to force/release a signal from C++ code. The force control
+   signals are created as :option:`public_flat` signals.
+
+   Same as :option:`/*verilator&32;forceable*/` metacomment.
+
 .. option:: full_case -file "<filename>" -lines <lineno>
 
 .. option:: parallel_case -file "<filename>" -lines <lineno>
@@ -1598,12 +1636,18 @@ The grammar of configuration commands is as follows:
    :option:`/*verilator&32;public_flat*/`, etc, metacomments. See
    e.g. :ref:`VPI Example`.
 
+.. option:: profile_data -mtask "<mtask_hash>" -cost <cost_value>
+
+   Feeds profile-guided optimization data into the Verilator algorithms in
+   order to improve model runtime performance.  This option is not expected
+   to be used by users directly.  See :ref:`Thread PGO`.
+
 .. option:: sc_bv -module "<modulename>" [-task "<taskname>"] -var "<signame>"
 
 .. option:: sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>"
 
    Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool,
-   vluint32_t or vluint64_t.  Same as :option:`/*verilator&32;sc_bv*/`
+   uint32_t or uint64_t.  Same as :option:`/*verilator&32;sc_bv*/`
    metacomment.
 
 .. option:: sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"

docs/guide/exe_verilator_coverage.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_coverage
@@ -67,7 +67,7 @@ which have low coverage are written to the output directory.
 
 Specifies if the coverage point does not include the count number of
 coverage hits, then the coverage point will be considered above the
-threashold, and the coverage report will put a "%" to indicate the coverage
+threshold, and the coverage report will put a "%" to indicate the coverage
 is not sufficient.  Defaults to 10.
 
 .. option:: --help

docs/guide/exe_verilator_gantt.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_gantt
@@ -10,42 +10,60 @@ starts and ends, and showing when each thread is busy or idle.
 
 For an overview of use of verilator_gantt, see :ref:`Profiling`.
 
-Gantt Chart Contents
---------------------
+Gantt Chart VCD
+---------------
 
-The generated Gantt chart has time on the X-axis. Times shown are to the
-scale printed, i.e. a certain about of time for each character width.  The
-Y-axis shows threads, each thread's execution is shown on one line.  That
-line shows "[" at the position in time when it executes.
+Verilated_gantt creates a value change dump (VCD) format dump file which
+may be viewed in a waveform viewer (e.g. C<GTKWave>):
 
-Following the "[" is the CPU number the task executed on, followed by zero
-or more "-" to make the width of the characters match the scaled execution
-time, followed by a "]".  If the scale is too small, the CPU number and
-mtask number will not be printed.  If the scale is very small, a "&"
-indicates multiple mtasks started at that time position.
+.. figure:: figures/fig_gantt_min.png
+
+   Example verilator_gantt output, as viewed with GTKWave.
+
+The viewed waveform chart has time on the X-axis, with one unit for each
+time tick of the system's high-performance counter.
 
-Also creates a value change dump (VCD) format dump file which may be viewed
-in a waveform viewer (e.g. C<GTKWave>).  See below.
 
 Gantt Chart VCD Signals
 -----------------------
 
-In waveforms there are the following signals. Most signals the "decimal"
-format will remove the leading zeros and make the traces easier to read.
+In waveforms there are the following signals. In GTKWave, using a data
+format of "decimal" will remove the leading zeros and make the traces
+easier to read.
 
-parallelism
+evals
+  Increments each time when eval_step was measured to be active.  This
+  allow visualization of how much time eval_step was active.
+
+eval_loop
+  Increments each time when the evaluation loop within eval_step was
+  measured to be active.  For best performance there is only a single
+  evaluation loop within each eval_step call, that is the eval_loop
+  waveform looks identical to the evals waveform.
+
+measured_parallelism
   The number of mtasks active at this time, for best performance this will
-  match the thread count. You may want to use an "analog step" format to
+  match the thread count. In GTKWave, use a data format of "analog step" to
   view this signal.
 
+predicted_parallelism
+  The number of mtasks Verilator predicted would be active at this time,
+  for best performance this will match the thread count. In GTKWave, use a
+  data format of "analog step" to view this signal.
+
 cpu#_thread
-  For the given CPU number, the thread number executing.
+  For the given CPU number, the thread number measured to be executing.
 
 mtask#_cpu
-  For the given mtask id, the CPU it is executing on.
+  For the given mtask id, the CPU it was measured to execute on.
 
 thread#_mtask
-  For the given thread number, the mtask id executing.
+  For the given thread number, the mtask id it was executing.
+
+predicted_thread#_mtask
+  For the given thread number, the mtask id Verilator predicted would be
+  executing.
+
 
 verilator_gantt Arguments
 -------------------------
@@ -54,19 +72,12 @@ verilator_gantt Arguments
 
 .. option:: <filename>
 
-The filename to read data from, defaults to "profile_threads.dat".
+The filename to read data from, defaults to "profile_exec.dat".
 
 .. option:: --help
 
 Displays a help summary, the program version, and exits.
 
-.. option:: --scale <n>
-
-Sets the number of time units per character on the X-axis of the generated
-Gantt chart.  (On x86, time units are rdtsc ticks.)  Defaults to 0, which
-will automatically compute a reasonable scale where no two mtasks need to
-fit into same character width's worth of scaled time.
-
 .. option:: --no-vcd
 
 Disables creating a .vcd file.

docs/guide/exe_verilator_profcfunc.rst

@@ -1,20 +1,24 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-verilator_profcfuncs
-====================
+verilator_profcfunc
+===================
 
 Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of time, etc, in
 each Verilog block.
 
-For an overview of use of verilator_profcfuncs, see :ref:`Profiling`.
+Due to rounding errors in gprof reports, the input report's percentages may
+not total to 100%.  In the verilator_profcfunc report this will get
+reported as a rounding error.
 
-verilator_profcfuncs Arguments
-------------------------------
+For an overview of use of verilator_profcfunc, see :ref:`Profiling`.
 
-.. program:: verilator_profcfuncs
+verilator_profcfunc Arguments
+-----------------------------
+
+.. program:: verilator_profcfunc
 
 .. option:: <filename>
 

docs/guide/executables.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********************************
@@ -15,5 +15,5 @@ options to each executable.
    exe_verilator.rst
    exe_verilator_coverage.rst
    exe_verilator_gantt.rst
-   exe_verilator_profcfuncs.rst
+   exe_verilator_profcfunc.rst
    exe_sim.rst

docs/guide/extensions.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************
@@ -33,7 +33,12 @@ or "`ifdef`"'s may break other tools.
    that returns up to a 32-bit number (without a trailing ;). This can be
    used to call C++ functions from your Verilog code.
 
-   String arguments will be put directly into the output C++ code.
+   String arguments will be put directly into the output C++ code, except
+   the word 'this' (i.e.: the object pointer) might be replaced with a
+   different pointer as Verilator might implement logic with non-member
+   functions. For this reason, any references to class members must be made
+   via an explicit 'this->' pointer dereference.
+
    Expression arguments will have the code to evaluate the expression
    inserted.  Thus to call a C++ function, :code:`$c("func(",a,")")` will
    result in :code:`func(a)` in the output C++ code.  For input arguments,
@@ -43,6 +48,14 @@ or "`ifdef`"'s may break other tools.
    Verilog functions where the variable is flattened out, and also enable
    other optimizations.
 
+   Verilator does not use any text inside the quotes for
+   ordering/scheduling.  If you need the $c to be called at a specific
+   time, e.g. when a variable changes, then the $c must be under an
+   appropriate sensitivity statement, e.g. :code:`always @(posedge clk)
+   $c("func()")` to call it on every edge, or e.g. :code:`always @*
+   c("func(",a,")")` to call it when :code:`a` changes (the latter working
+   because :code:`a` is outside the quotes).
+
    If you will be reading or writing any Verilog variables inside the C++
    functions, the Verilog signals must be declared with
    :option:`/*verilator&32;public*/` metacomments.
@@ -171,10 +184,9 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;no_clocker*/
 
-   Used after a signal declaration to indicate the signal is used as clock
-   or not. This information is used by Verilator to mark the signal as
-   clocker and propagate the clocker attribute automatically to derived
-   signals. See :vlopt:`--clk`.
+   Specifies that the signal is used as clock or not. This information is
+   used by Verilator to mark the signal and any derived signals as
+   clocker.  See :vlopt:`--clk`.
 
    Same as :option:`clocker` and :option:`no_clocker` in configuration
    files.
@@ -197,6 +209,20 @@ or "`ifdef`"'s may break other tools.
    (if appropriate :vlopt:`--coverage` flags are passed) after being
    disabled earlier with :option:`/*verilator&32;coverage_off*/`.
 
+.. option:: /*verilator&32;forceable*/
+
+   Specifies that the signal (net or variable) should be made forceable from
+   C++ code by generating public `<signame>__VforceEn` and
+   `<signame>__VforceVal` signals The force control signals are created as
+   :option:`public_flat` signals.
+
+   To force a marked signal from C++, set the corresponding `__VforceVal`
+   variable to the desired value, and the `__VforceEn` signal to the bitmask
+   indicating which bits of the signal to force. To force all bits of the
+   target signal, set `__VforceEn` to all ones. To release the signal (or part
+   thereof), set appropriate bits of the `__VforceEn` signal to zero.
+
+   Same as :option:`forceable` in configuration  files.
 
 .. _verilator_hier_block:
 
@@ -419,7 +445,7 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;sc_bv*/
 
    Used after a port declaration.  It sets the port to be of
-   :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t.
+   :code:`sc_bv<{width}>` type, instead of bool, uint32_t or uint64_t.
    This may be useful if the port width is parameterized and the
    instantiating C++ code wants to always have a sc_bv so it can accept any
    width.  In general you should avoid using this attribute when not
@@ -477,6 +503,13 @@ or "`ifdef`"'s may break other tools.
    Verilator) text that should be passed through to the XML output as a tag,
    for use by downstream applications.
 
+.. option:: /*verilator&32;trace_init_task*/
+
+   Attached to a DPI import to indicate that function should be called when
+   initializing tracing. This attribute is indented only to be used
+   internally in code that Verilator generates when :vlopt:`--lib-create`
+   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`.
+
 .. option:: /*verilator&32;tracing_off*/
 
    Disable waveform tracing for all future signals that are declared in

docs/guide/faq.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ******************************
@@ -35,15 +35,17 @@ simulators.
 Does Verilator run under Windows?
 """""""""""""""""""""""""""""""""
 
-Yes, using Cygwin.  Verilated output also compiles under Microsoft Visual
-C++, but this is not tested every release.
+Yes, ideally run Ubuntu under Windows Subsystem for Linux (WSL2).
+Alternatively use Cygwin, though this tends to be slower and is not
+regularly tested.  Verilated output also compiles under Microsoft Visual
+C++, but this is also not regularly tested.
 
 
 Can you provide binaries?
 """""""""""""""""""""""""
 
 You can install Verilator via the system package manager (apt, yum, etc.)
-on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and
+on many Linux distributions, including Debian, Ubuntu, SuSE, Red Hat, and
 others.  These packages are provided by the Linux distributions and
 generally will lag the version of the mainline Verilator repository.  If no
 binary package is available for your distribution, how about you set one
@@ -132,7 +134,8 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
           ...
           Verilated::traceEverOn(true);
           VerilatedVcdC* tfp = new VerilatedVcdC;
-          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
+          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy (or see below)
+          // tfp->dumpvars(1, "t");  // trace 1 level under "t"
           tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
           ...
           while (contextp->time() < sim_time && !contextp->gotFinish()) {
@@ -351,8 +354,8 @@ also use the "import DPI" SystemVerilog feature to call C code (see the
 chapter above).  There is also limited VPI access to public signals.
 
 If you want something more complex, since Verilator emits standard C++
-code, you can simply write your own C++ routines that can access and modify
-signal values without needing any PLI interface code, and call it with
+code, you can write your own C++ routines that can access and modify signal
+values without needing any PLI interface code, and call it with
 $c("{any_c++_statement}").
 
 See the :ref:`Connecting` section.
@@ -442,7 +445,7 @@ the signal, as you would any other member variable.
 Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
 64-bit unsigned long longs (uint64_t) that fits the width of the signal.
-Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for
+Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
 1 to 64 bits, and the compiler will properly up-convert smaller entities.
 Note even signed ports are declared as unsigned; you must sign extend
 yourself to the appropriate signal width.
@@ -479,7 +482,7 @@ by your code or you'll get strange results.
 Should a module be in Verilog or SystemC?
 """""""""""""""""""""""""""""""""""""""""
 
-Sometimes there is a block that just interconnects instances, and have a
+Sometimes there is a block that only interconnects instances, and have a
 choice as to if you write it in Verilog or SystemC.  Everything else being
 equal, best performance is when Verilator sees all of the design.  So, look
 at the hierarchy of your design, labeling instances as to if they are

docs/guide/files.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *****
@@ -54,32 +54,38 @@ For --cc/--sc, it creates:
      - Arguments for hierarchical Verilation (from --make gmake)
    * - *{prefix}*\ _hierCMakeArgs.f
      - Arguments for hierarchical Verilation (from --make cmake)
-   * - *{prefix}*\ .cpp
-     - Top level C++ file
-   * - *{prefix}{__n}*\ .cpp
-     - Additional top C++ files (from --output-split)
    * - *{prefix}*\ .h
-     - Top level header
-   * - *{prefix}*\ __Slow\ *{__n}*\ .cpp
+     - Model header
+   * - *{prefix}*\ .cpp
+     - Model C++ file
+   * - *{prefix}*\ ___024root.h
+     - Top level (SystemVerilog $root) internal header file
+   * - *{prefix}*\ ___024root.cpp
+     - Top level (SystemVerilog $root) internal C++ file
+   * - *{prefix}*___024root*{__n}*\ .cpp
+     - Additional top level internal C++ files (from --output-split)
+   * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
      - Infrequent cold routines
-   * - *{prefix}*\ __Dpi.cpp
-     - DPI import and export wrappers (from --dpi)
+   * - *{prefix}*\ ___024root__Trace{__n}*\ .cpp
+     - Wave file generation code (from --trace)
+   * - *{prefix}*\ ___024root__Trace__Slow{__n}*\ .cpp
+     - Wave file generation code (from --trace)
    * - *{prefix}*\ __Dpi.h
      - DPI import and export declarations (from --dpi)
+   * - *{prefix}*\ __Dpi.cpp
+     - Global DPI export wrappers (from --dpi)
+   * - *{prefix}*\ __Dpi_Export\ *{__n}*\ .cpp
+     - DPI export wrappers scoped to this particular model (from --dpi)
    * - *{prefix}*\ __Inlines.h
      - Inline support functions
-   * - *{prefix}*\ __Syms.cpp
-     - Global symbol table C++
    * - *{prefix}*\ __Syms.h
      - Global symbol table header
-   * - *{prefix}*\ __Trace{__n}*\ .cpp
-     - Wave file generation code (from --trace)
-   * - *{prefix}*\ __Trace__Slow{__n}*\ .cpp
-     - Wave file generation code (from --trace)
-   * - *{prefix}{each_verilog_module}*\ .cpp
-     - Lower level internal C++ files
+   * - *{prefix}*\ __Syms.cpp
+     - Global symbol table C++
    * - *{prefix}{each_verilog_module}*\ .h
      - Lower level internal header files
+   * - *{prefix}{each_verilog_module}*\ .cpp
+     - Lower level internal C++ files
    * - *{prefix}{each_verilog_module}{__n}*\ .cpp
      - Additional lower C++ files (from --output-split)
 
@@ -114,7 +120,7 @@ In certain debug and other modes, it also creates:
      - Debugging graph files (from --debug)
    * - *{prefix}{misc}*\ .tree
      - Debugging files (from --debug)
-   * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp
+   * - {mod_prefix}_{each_verilog_base_filename}*\ .vpp
      - Pre-processed verilog (from --debug)
 
 After running Make, the C++ compiler may produce the following:
@@ -139,3 +145,23 @@ After running Make, the C++ compiler may produce the following:
      - Intermediate dependencies
    * - *{prefix}{misc}*\ .o
      - Intermediate objects
+
+The Verilated executable may produce the following:
+
+.. list-table::
+
+   * - coverage.dat
+     - Code coverage output, and default input filename for :command:`verilator_coverage`
+   * - gmon.out
+     - GCC/clang code profiler output, often fed into :command:`verilator_profcfunc`
+   * - profile.vlt
+     - --prof-pgo data file for :ref:`Thread PGO`
+   * - profile_exec.dat
+     - --prof-exec data file for :command:`verilator_gantt`
+
+Verilator_gantt may produce the following:
+
+.. list-table::
+
+   * - profile_exec.vcd
+     - Gantt report waveform output

docs/guide/index.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ######################

docs/guide/install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Installation:
@@ -23,6 +23,8 @@ package:
 
    apt-get install verilator   # On Ubuntu
 
+For other distributions refer to `Repology Verilator Distro Packages
+<https://repology.org/project/verilator>`__.
 
 .. _Git Install:
 
@@ -44,21 +46,20 @@ In brief, to install from git:
    #sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
 
    git clone https://github.com/verilator/verilator   # Only first time
-   ## Note the URL above is not a page you can see with a browser, it's for git only
 
    # Every time you need to build:
    unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
    unset VERILATOR_ROOT  # For bash
    cd verilator
-   git pull        # Make sure git repository is up-to-date
-   git tag         # See what versions exist
+   git pull         # Make sure git repository is up-to-date
+   git tag          # See what versions exist
    #git checkout master      # Use development branch (e.g. recent bug fixes)
    #git checkout stable      # Use most recent stable release
    #git checkout v{version}  # Switch to specified release version
 
-   autoconf        # Create ./configure script
-   ./configure     # Configure and create Makefile
-   make -j         # Build Verilator itself
+   autoconf         # Create ./configure script
+   ./configure      # Configure and create Makefile
+   make -j `nproc`  # Build Verilator itself (if error, try just 'make')
    sudo make install
 
 
@@ -76,11 +77,11 @@ OS Requirements
 ---------------
 
 Verilator is developed and has primary testing on Ubuntu, with additional
-testing on FreeBSD and Apple OS-X. Versions have also built on Redhat
-Linux, HPUX and Solaris. It should run with minor porting on any
-GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and
-Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator
-itself) compiles under all the options above, plus using MSVC++.
+testing on FreeBSD and Apple OS-X. Versions have also built on Red Hat
+Linux, and other flavors of GNU/Linux-ish platforms. Verilator also works
+on Windows Subsystem for Linux (WSL2), Windows under Cygwin, and Windows
+under MinGW (gcc -mno-cygwin). Verilated output (not Verilator itself)
+compiles under all the options above, plus using MSVC++.
 
 
 Install Prerequisites
@@ -116,7 +117,7 @@ Those developing Verilator itself may also want these (see internals.rst):
 
 ::
 
-   sudo apt-get install gdb graphviz cmake clang clang-format gprof lcov
+   sudo apt-get install gdb graphviz cmake clang clang-format-11 gprof lcov
    sudo pip3 install sphinx sphinx_rtd_theme breathe
    cpan install Pod::Perldoc
    cpan install Parallel::Forker
@@ -286,7 +287,7 @@ Compile Verilator:
 
 ::
 
-   make -j
+   make -j `nproc`  # Or if error on `nproc`, the number of CPUs in system
 
 
 Test

docs/guide/languages.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ***************
@@ -92,7 +92,7 @@ appropriate code to detect failing cases at simulation runtime and print an
 
 Verilator likewise also asserts any "unique" or "priority" SystemVerilog
 keywords on case statement, as well as "unique" on if statements.  However,
-"priority if" is currently simply ignored.
+"priority if" is currently ignored.
 
 
 .. _Language Limitations:
@@ -136,7 +136,7 @@ ___05F (5F is the hex code of an underscore.)
 Bind
 ----
 
-sVerilator only supports bind to a target module name, not to an
+Verilator only supports bind to a target module name, not to an
 instance path.
 
 
@@ -174,9 +174,9 @@ Structures and Unions
 ---------------------
 
 Presently Verilator only supports packed structs and packed unions.  Rand
-and randc tags on members are simply ignored.  All structures and unions
-are represented as a single vector, which means that generating one member
-of a structure from blocking, and another from non-blocking assignments is
+and randc tags on members are ignored.  All structures and unions are
+represented as a single vector, which means that generating one member of a
+structure from blocking, and another from non-blocking assignments is
 unsupported.
 
 
@@ -336,6 +336,24 @@ Verilator does not support SEREs yet.  All assertion and coverage
 statements must be simple expressions that complete in one cycle.
 
 
+Force statement
+---------------
+
+Verilator supports the procedural `force` (and corresponding `release`)
+statement. The behavior of the `force` statement however does not entirely
+comply with the IEEE 1800 SystemVerilog standard. According to the standard,
+when a procedural statement of the form `force a = b;` is executed, the
+simulation should behave as if from that point onwards, a continuous
+assignment `assign a = b;` have been added to override the drivers of `a`.
+More specifically: the value of `a` should be updated, whenever the value of
+`b` changes, all the way until a `release a;` statement is executed.
+Verilator instead evaluates the current value of `b` at the time the `force`
+statement is executed, and forces `a` to that value, without updating it
+until a new `force` or `release` statement is encountered that applies to
+`a`. This non-standard behavior is nevertheless consistent with some other
+simulators.
+
+
 Encrypted Verilog
 -----------------
 

docs/guide/overview.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ********

docs/guide/simulating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Simulating:
@@ -26,7 +26,8 @@ risk of reset bugs in trade for performance; see the above documentation
 for these options.
 
 If using Verilated multithreaded, use ``numactl`` to ensure you are using
-non-conflicting hardware resources. See :ref:`Multithreading`.
+non-conflicting hardware resources. See :ref:`Multithreading`. Also
+consider using profile-guided optimization, see :ref:`Thread PGO`.
 
 Minor Verilog code changes can also give big wins.  You should not have any
 UNOPTFLAT warnings from Verilator.  Fixing these warnings can result in
@@ -93,9 +94,7 @@ cases, for example regressions, it is usually worth spending extra
 compilation time to reduce total CPU time.
 
 If you will be running many simulations on a single model, you can
-investigate profile guided optimization. With GCC, using GCC's
-"-fprofile-arcs", then GCC's "-fbranch-probabilities" will yield another
-15% or so.
+investigate profile guided optimization. See :ref:`Compiler PGO`.
 
 Modern compilers also support link-time optimization (LTO), which can help
 especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in
@@ -230,7 +229,7 @@ coverage point insertions into the model and collect the coverage data.
 
 To get the coverage data from the model, in the user wrapper code,
 typically at the end once a test passes, call
-:code:`Verilated::coveragep()->write` with an argument of the filename for
+:code:`Verilated::threadContextp()->coveragep()->write` with an argument of the filename for
 the coverage data file to write coverage data to (typically
 "logs/coverage.dat").
 
@@ -272,8 +271,6 @@ profiled C++ code functions.
 To use profiling:
 
 #. Use Verilator's :vlopt:`--prof-cfuncs`.
-#. Use Verilator's :vlopt:`-CFLAGS "-g -pg" <-CFLAGS>` to pass the
-   profiling flags through to GCC/Clang.
 #. Build and run the simulation model.
 #. The model will create gmon.out.
 #. Run :command:`gprof` to see where in the C++ code the time is spent.
@@ -282,23 +279,25 @@ To use profiling:
    is being spent.
 
 
-.. _Thread Profiling:
+.. _Execution Profiling:
 
-Thread Profiling
-================
+Execution Profiling
+===================
 
-When using multithreaded mode (:vlopt:`--threads`), it is useful to see
-statistics and visualize how well the multiple CPUs are being utilized.
+For performance optimization, it is useful to see statistics and visualize how
+execution time is distributed in a verilated model.
 
-With the :vlopt:`--prof-threads` option, Verilator will:
+With the :vlopt:`--prof-exec` option, Verilator will:
 
-* Add code to the Verilated model to record the start and end time of each
-  macro-task across a number of calls to eval. (What is a macro-task?  See
-  the Verilator internals document (:file:`docs/internals.rst` in the
-  distribution.)
+* Add code to the Verilated model to record execution flow.
 
 * Add code to save profiling data in non-human-friendly form to the file
-  specified with :vlopt:`+verilator+prof+threads+file+\<filename\>`.
+  specified with :vlopt:`+verilator+prof+exec+file+\<filename\>`.
+
+* In multi-threaded models, add code to record the start and end time of each
+  macro-task across a number of calls to eval. (What is a macro-task?  See the
+  Verilator internals document (:file:`docs/internals.rst` in the
+  distribution.)
 
 The :command:`verilator_gantt` program may then be run to transform the
 saved profiling file into a nicer visual format and produce some related
@@ -308,7 +307,7 @@ statistics.
 
    Example verilator_gantt output, as viewed with GTKWave.
 
-   The parallelism shows the number of CPUs being used at a given moment.
+   The measured_parallelism shows the number of CPUs being used at a given moment.
 
    The cpu_thread section shows which thread is executing on each of the physical CPUs.
 
@@ -316,6 +315,7 @@ statistics.
 
 For more information see :command:`verilator_gantt`.
 
+
 .. _Profiling ccache efficiency:
 
 Profiling ccache efficiency
@@ -379,3 +379,121 @@ For example:
          os >> main_time;
          os >> *topp;
      }
+
+
+Profile-Guided Optimization
+===========================
+
+Profile-guided optimization is the technique where profiling data is
+collected by running your simulation executable, then this information is
+used to guide the next Verilation or compilation.
+
+There are two forms of profile-guided optimizations.  Unfortunately for
+best results they must each be performed from the highest level code to the
+lowest, which means performing them separately and in this order:
+
+* :ref:`Thread PGO`
+* :ref:`Compiler PGO`
+
+Other forms of PGO may be supported in the future, such as clock and reset
+toggle rate PGO, branch prediction PGO, statement execution time PGO, or
+others as they prove beneficial.
+
+
+.. _Thread PGO:
+
+Thread Profile-Guided Optimization
+----------------------------------
+
+Verilator supports profile-guided optimization (verilation) of multi-threaded
+models (Thread PGO) to improve performance.
+
+When using multithreading, Verilator computes how long macro tasks take and
+tries to balance those across threads.  (What is a macro-task?  See the
+Verilator internals document (:file:`docs/internals.rst` in the
+distribution.)  If the estimations are incorrect, the threads will not be
+balanced, leading to decreased performance.  Thread PGO allows collecting
+profiling data to replace the estimates and better optimize these
+decisions.
+
+To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option. This
+will code to the verilated model to save profiling data for profile-guided
+optimization.
+
+Run the model executable. When the executable exits, it will create a
+profile.vlt file.
+
+Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option,
+and adding the profile.vlt generated earlier to the command line.
+
+Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
+profile data file (profile.vlt) can be placed on the verilator command line
+directly without any prefix.
+
+If results from multiple simulations are to be used in generating the
+optimization, multiple simulation's profile.vlt may be concatenated
+externally, or each of the files may be fed as separate command line
+options into Verilator.  Verilator will sum the profile results, so a
+longer running test will have proportionally more weight for optimization
+than a shorter running test.
+
+If you provide any profile feedback data to Verilator, and it cannot use
+it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
+scheduled using estimated costs.  This usually indicates that the profile
+data was generated from different Verilog source code than Verilator is
+currently running against. Therefore, repeat the data collection phase to
+create new profiling data, then rerun Verilator with the same input source
+files and that new profiling data.
+
+
+.. _Compiler PGO:
+
+Compiler Profile-Guided Optimization
+------------------------------------
+
+GCC and Clang support compiler profile-guided optimization (PGO). This
+optimizes any C/C++ program including Verilated code.  Using compiler PGO
+typically yields improvements of 5-15% on both single-threaded and
+multi-threaded models.
+
+To use compiler PGO with GCC or Clang, please see the appropriate compiler
+documentation.  The process in GCC 10 was as follows:
+
+1. Compile the Verilated model with the compiler's "-fprofile-generate"
+   flag:
+
+   .. code-block:: bash
+
+      verilator [whatever_flags] --make \
+          -CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate
+
+   or, if calling make yourself, add -fprofile-generate appropriately to your
+   Makefile.
+
+2. Run your simulation. This will create \*.gcda file(s) in the same
+   directory as the source files.
+
+3. Recompile the model with -fprofile-use. The compiler will read the
+   \*.gcda file(s).
+
+   For GCC:
+
+   .. code-block:: bash
+
+      verilator [whatever_flags] --build \
+          -CFLAGS "-fprofile-use -fprofile-correction"
+
+   For Clang:
+
+   .. code-block:: bash
+
+      llvm-profdata merge -output default.profdata *.profraw
+      verilator [whatever_flags] --build \
+          -CFLAGS "-fprofile-use -fprofile-correction"
+
+   or, if calling make yourself, add these CFLAGS switches appropriately to
+   your Makefile.
+
+Clang and GCC also support -fauto-profile which uses sample-based
+feedback-directed optimization.  See the appropriate compiler
+documentation.

docs/guide/verilating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 **********
@@ -68,12 +68,11 @@ multi-core SoC.
 
 Verilator is run in hierarchical mode on the whole SoC.  Verilator will
 make two models, one for the CPU hierarchy block, and one for the SoC.  The
-Verialted code for the SoC will automatically call the CPU Verilated model.
+Verilated code for the SoC will automatically call the CPU Verilated model.
 
-The current hierarchical Verilation is based on protect-lib. Each hierarchy
-block is Verilated to a protect-lib. User modules of the hierarchy blocks
-will see a tiny wrapper generated by protect-lib instead of the actual
-design.
+The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
+hierarchy block is Verilated into a library. User modules of the hierarchy
+blocks will see a tiny wrapper generated by :vlopt:`--lib-create`.
 
 
 Usage
@@ -216,6 +215,12 @@ be done by a "main thread". In most cases the eval thread and main thread
 are the same thread (i.e. the user's top C++ testbench runs on a single
 thread), but this is not required.
 
+When making frequent use of DPI imported functions in a multi-threaded
+model, it may be beneficial to performance to adjust the
+:vlopt:`--instr-count-dpi` option based on some experimentation. This
+influences the partitioning of the model by adjusting the assumed execution
+time of DPI imports.
+
 The :vlopt:`--trace-threads` options can be used to produce trace dumps
 using multiple threads. If :vlopt:`--trace-threads` is set without
 :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
@@ -260,7 +265,7 @@ This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
 (presumably on socket 0) optimizing performance.  Of course this must be
 adjusted if you want another simulator using e.g. socket 1, or if you
 Verilated with a different number of threads.  To see what CPUs are
-actually used, use :vlopt:`--prof-threads`.
+actually used, use :vlopt:`--prof-exec`.
 
 
 Multithreaded Verilog and Library Support

docs/guide/warnings.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************
@@ -12,7 +12,7 @@ Disabling Warnings
 Warnings may be disabled in multiple ways:
 
 #. Disable the warning in the source code.  When the warning is printed it
-   will include a warning code.  Simply surround the offending line with a
+   will include a warning code.  Surround the offending line with a
    :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/`
    metacomment pair:
 
@@ -130,9 +130,10 @@ List Of Warnings
 
 .. option:: BADSTDPRAGMA
 
-   Error that a pragma is badly formed, when that pragma is defined by IEEE1800-2017.
-   For example, an empty `pragma line, or an incorrect specified '`pragma protect'.
-   Note that 3rd party pragmas not defined by IEEE1800-2017 are ignored.
+   Error that a pragma is badly formed, when that pragma is defined by IEEE
+   1800-2017.  For example, an empty pragma line, or an incorrect specified
+   'pragma protect'.  Note that 3rd party pragmas not defined by IEEE
+   1800-2017 are ignored.
 
 
 .. option:: BLKANDNBLK
@@ -161,7 +162,7 @@ List Of Warnings
          always @(posedge clk)  foo[0] <= ...
          always_comb foo[1] = ...
 
-   Simply use a different register for the flop:
+   Instead use a different register for the flop:
 
    .. code-block:: sv
 
@@ -283,7 +284,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that it is simply better style to use casez, and "?" in place of
+   Warns that it is better style to use casez, and "?" in place of
    "x"'s.  See
    `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf
    <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>`_
@@ -446,7 +447,7 @@ List Of Warnings
               p0();
          endmodule
 
-   Other tools with similar warnings: Veriable's forbid_defparam_rule.
+   Other tools with similar warnings: Verible's forbid_defparam_rule.
 
 
 .. option:: DEPRECATED
@@ -481,39 +482,44 @@ List Of Warnings
 
    Faulty example:
 
-   .. code-block:: sv
+   .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_faulty.rst
 
-         always_comb b = ~a;
-         always_comb a = b
+   Results in at runtime (not when Verilated):
 
-   This code will toggle forever, and thus to prevent an infinite loop, the
-   executable will give the didn't converge error.
+   .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst
 
-   To debug this, first review any UNOPTFLAT warnings that were ignored.
-   Though typically it is safe to ignore UNOPTFLAT (at a performance cost),
-   at the time of issuing a UNOPTFLAT Verilator did not know if the logic
-   would eventually converge and assumed it would.
+   This is because the signals keep toggling even with out time
+   passing. Thus to prevent an infinite loop, the Verilated executable
+   gives the DIDNOTCONVERGE error.
+
+   To debug this, first review any UNOPT or UNOPTFLAT warnings that were
+   ignored.  Though typically it is safe to ignore UNOPTFLAT (at a
+   performance cost), at the time of issuing a UNOPTFLAT Verilator did not
+   know if the logic would eventually converge and assumed it would.
 
    Next, run Verilator with :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG
    <--prof-cfuncs>`.  Rerun the test.  Now just before the convergence
    error you should see additional output similar to this:
 
-   .. code-block::
+   .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_msg.rst
 
-         CHANGE: filename.v:1: b
-         CHANGE: filename.v:2: a
-
-   This means that signal b and signal a keep changing, inspect the code
-   that modifies these signals.  Note if many signals are getting printed
-   then most likely all of them are oscillating.  It may also be that
-   e.g. "a" may be oscillating, then "a" feeds signal "c" which then is
-   also reported as oscillating.
+   The CHANGE line means that on the given filename and line number that
+   drove a signal, the signal 'a' kept changing. Inspect the code that
+   modifies these signals.  Note if many signals are getting printed then
+   most likely all of them are oscillating.  It may also be that e.g. "a"
+   may be oscillating, then "a" feeds signal "c" which then is also
+   reported as oscillating.
 
    One way DIDNOTCONVERGE may occur is flops are built out of gate
-   primitives.  error. Verilator does not support building flops or latches
-   out of gate primitives, and any such code must change to use behavioral
+   primitives. Verilator does not support building flops or latches out of
+   gate primitives, and any such code must change to use behavioral
    constructs (e.g. always_ff and always_latch).
 
+   Another way DIDNOTCONVERGE may occur is if # delays are used to generate
+   clocks.  Verilator ignores the delays and gives an :option:`ASSIGNDLY`
+   or :option:`STMTDLY` warning.  If these were suppressed, due to the
+   absence of the delay, the code may now oscillate.
+
    Finally, rare, more difficult cases can be debugged like a C++ program;
    either enter :command:`gdb` and use its tracing facilities, or edit the
    generated C++ code to add appropriate prints to see what is going on.
@@ -522,7 +528,7 @@ List Of Warnings
 .. option:: ENDCAPSULATED
 
    Warns that a class member is declared is local or protected, but is
-   being accessed from outside that class (if local) or a derrived class
+   being accessed from outside that class (if local) or a derived class
    (if protected).
 
    Ignoring this warning will only suppress the lint check, it will
@@ -572,7 +578,7 @@ List Of Warnings
    must end in newline, as otherwise for example :command:`cat` with the
    file as an argument may produce undesirable results.
 
-   Repair by adding a newline to the end of the file.
+   Repair by appending a newline to the end of the file.
 
    Disabled by default as this is a code style warning; it will simulate
    correctly.
@@ -792,8 +798,8 @@ List Of Warnings
    .. TODO better example
 
    Warns that a module has multiple definitions.  Generally this indicates
-   a coding error, or a mistake in a library file and it's good practice to
-   have one module per file (and only put each file once on the command
+   a coding error, or a mistake in a library file, and it's good practice
+   to have one module per file (and only put each file once on the command
    line) to avoid these issues.  For some gate level netlists duplicates
    are sometimes unavoidable, and MODDUP should be disabled.
 
@@ -918,7 +924,7 @@ List Of Warnings
    simulate correctly.
 
    Other tools with similar warnings: Icarus Verilog's portbind, "warning:
-   Instantiating module ... with dangling impot port (...)". Slang's
+   Instantiating module ... with dangling input port (...)". Slang's
    unconnected-port, "port '...' has no connection".
 
 
@@ -1005,9 +1011,25 @@ List Of Warnings
    a var/reg must be used as the target of procedural assignments.
 
 
+.. option:: PROFOUTOFDATE
+
+   Warns that threads were scheduled using estimated costs, despite the
+   fact that data was provided from profile-guided optimization (see
+   :ref:`Thread PGO`) as fed into Verilator using the
+   :option:`profile_data` configuration file option.  This usually
+   indicates that the profile data was generated from different Verilog
+   source code than Verilator is currently running against.
+
+   It is recommended to create new profiling data, then rerun Verilator
+   with the same input source files and that new profiling data.
+
+   Ignoring this warning may only slow simulations, it will simulate
+   correctly.
+
+
 .. option:: PROTECTED
 
-   Warning that a '`pragma protected' section was encountered. The code
+   Warning that a 'pragma protected' section was encountered. The code
    inside the protected region will be partly checked for correctness, but is
    otherwise ignored.
 
@@ -1183,9 +1205,25 @@ List Of Warnings
 
    Faulty example:
 
-   .. code-block:: sv
+   .. include:: ../../docs/gen/ex_STMTDLY_faulty.rst
 
-         #100 $finish;  //<--- Warning
+   Results in:
+
+   .. include:: ../../docs/gen/ex_STMTDLY_msg.rst
+
+   This is a warning because Verilator does not support delayed statements.
+   It will ignore all such delays.  In many cases ignoring a delay might be
+   harmless, but if the delayed statement is, as in this example, used to
+   cause some important action at a later time, it might be an important
+   difference.
+
+   Some possible workarounds:
+
+   * Move the delayed statement into the C++ wrapper file, where the
+     stimulus and clock generation can be done in C++.
+
+   * Convert the statement into a FSM, or other statement that tests
+     against $time.
 
 
 .. option:: SYMRSVDWORD
@@ -1353,7 +1391,9 @@ List Of Warnings
 
    Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by
    synthesis which analyzes interconnection per-bit, but is circular to
-   simulation which analyzes per-bus:
+   simulation which analyzes per-bus.
+
+   Faulty example:
 
    .. code-block:: sv
 
@@ -1466,9 +1506,16 @@ List Of Warnings
    Error that a construct might be legal according to IEEE but is not
    currently supported by Verilator.
 
+   A typical workaround is to recode the construct into a simpler and more
+   common alternative language construct.
+
+   Alternatively, check if the construct is supported by other tools, and
+   if so please consider submitting a github pull request against the
+   Verilator sources to implement the missing unsupported feature.
+
    This error may be ignored with :vlopt:`--bbox-unsup`, however this will
-   make the design simulate incorrectly; see the details under
-   :vlopt:`--bbox-unsup`.
+   make the design simulate incorrectly and is only intended for lint
+   usage; see the details under :vlopt:`--bbox-unsup`.
 
 
 .. option:: UNUSED
@@ -1598,7 +1645,7 @@ List Of Warnings
    * A part select has a different size then needed to index into the
      packed or unpacked array (etc).
 
-   Verilator for attempts to track the minimum width of unsized constants
+   Verilator attempts to track the minimum width of unsized constants
    and will suppress the warning when the minimum width is appropriate to
    fit the required size.
 
@@ -1607,11 +1654,13 @@ List Of Warnings
 
    The recommendation is to fix these issues by:
 
-   * Resizing the variable or constant.  E.g. :code:`2'd2` instead of :code:`3'd2`.
+   * Resizing the variable or constant to match the needed size for the
+     expression.  E.g. :code:`2'd2` instead of :code:`3'd2`.
 
-   * Using :code:`'0` or :code:`'1`.
+   * Using :code:`'0` or :code:`'1` which automatically resize in an
+     expression.
 
-   * Using part select to narrow a variable. E.g. :code:`too_wide[1:0]`.
+   * Using part selects to narrow a variable. E.g. :code:`too_wide[1:0]`.
 
    * Using concatenate to widen a variable. E.g. :code:`{1'b1, too_narrow}`.
 

docs/internals.rst

@@ -114,11 +114,11 @@ By convention, each function/method uses the variable ``nodep`` as a
 pointer to the ``AstNode`` currently being processed.
 
 
-``AstNVisitor``
+``VNVisitor``
 ^^^^^^^^^^^^^^^
 
 The passes are implemented by AST visitor classes. These are implemented by
-subclasses of the abstract class, ``AstNVisitor``. Each pass creates an
+subclasses of the abstract class, ``VNVisitor``. Each pass creates an
 instance of the visitor class, which in turn implements a method to perform
 the pass.
 
@@ -268,11 +268,11 @@ Estimating Logic Costs
 
 To compute the cost of any given path through the graph, Verilator
 estimates an execution cost for each task. Each macro-task has an execution
-cost which is simply the sum of its tasks' costs. We assume that
-communication overhead and synchronization overhead are zero, so the cost
-of any given path through the graph is simply the sum of macro-task
-execution costs. Sarkar does almost the same thing, except that he has
-nonzero estimates for synchronization costs.
+cost which is the sum of its tasks' costs. We assume that communication
+overhead and synchronization overhead are zero, so the cost of any given
+path through the graph is the sum of macro-task execution costs. Sarkar
+does almost the same thing, except that he has nonzero estimates for
+synchronization costs.
 
 Verilator's cost estimates are assigned by ``InstrCountCostVisitor``.  This
 class is perhaps the most fragile piece of the multithread
@@ -301,7 +301,7 @@ prerequisites on other threads have finished.
 
 The synchronization cost is cheap if the prereqs are done. If they're not,
 fragmentation (idle CPU cores waiting) is possible. This is the major
-source of overhead in this approach. The ``--prof-threads`` switch and the
+source of overhead in this approach. The ``--prof-exec`` switch and the
 ``verilator_gantt`` script can visualize the time lost to such
 fragmentation.
 
@@ -405,6 +405,9 @@ routines in the sources to rely more heavily on randomness, and
 generally try harder not to keep input nodes together when we have the
 option to scramble things.
 
+Profile-guided optimization make this a bit better, by adjusting mtask
+scheduling, but this does not yet guide the packing into mtasks.
+
 
 Performance Regression
 """"""""""""""""""""""
@@ -502,7 +505,7 @@ Some of the code implementing passes is extremely repetitive, and must be
 implemented for each sub-class of ``AstNode``. However, while repetitive,
 there is more variability than can be handled in C++ macros.
 
-In Verilator this is implemented by using a Perl script, ``astgen`` to
+In Verilator this is implemented by using a script, ``astgen`` to
 pre-process the C++ code. For example in ``V3Const.cpp`` this is used to
 implement the ``visit()`` functions for each binary operation using the
 ``TREEOP`` macro.
@@ -520,10 +523,10 @@ optimization passes. This allows separation of the pass algorithm from the
 AST on which it operates. Wikipedia provides an introduction to the concept
 at https://en.wikipedia.org/wiki/Visitor_pattern.
 
-As noted above, all visitors are derived classes of ``AstNVisitor``. All
+As noted above, all visitors are derived classes of ``VNVisitor``. All
 derived classes of ``AstNode`` implement the ``accept`` method, which takes
-as argument a reference to an instance or a ``AstNVisitor`` derived class
-and applies the visit method of the ``AstNVisitor`` to the invoking AstNode
+as argument a reference to an instance or a ``VNVisitor`` derived class
+and applies the visit method of the ``VNVisitor`` to the invoking AstNode
 instance (i.e. ``this``).
 
 One possible difficulty is that a call to ``accept`` may perform an edit
@@ -601,8 +604,8 @@ There are three ways data is passed between visitor functions.
 Iterators
 ---------
 
-``AstNVisitor`` provides a set of iterators to facilitate walking over
-the tree. Each operates on the current ``AstNVisitor`` class (as this)
+``VNVisitor`` provides a set of iterators to facilitate walking over
+the tree. Each operates on the current ``VNVisitor`` class (as this)
 and takes an argument type ``AstNode*``.
 
 ``iterate``
@@ -750,8 +753,8 @@ test. For run-time tests, this is followed by a call to the ``execute``
 subroutine. Both of these functions can optionally be provided with a hash
 table as argument specifying additional options.
 
-The test driver assumes by default that the source Verilog file name
-matches the PERL driver name. So a test whose driver is
+The driver.pl script assumes by default that the source Verilog file name
+matches the test script name. So a test whose driver is
 ``t/t_mytest.pl`` will expect a Verilog source file ``t/t_mytest.v``.
 This can be changed using the ``top_filename`` subroutine, for example
 
@@ -814,7 +817,7 @@ which you can install using cpan.
 
 There are some traps to avoid when running regression tests
 
-- When checking the MANIFEST, the test will barf on unexpected code in the
+- When checking the MANIFEST, the test will fail on unexpected code in the
   Verilator tree. So make sure to keep any such code outside the tree.
 
 - Not all Linux systems install Perldoc by default. This is needed for the
@@ -1180,10 +1183,10 @@ Verilator ideally would support all of IEEE, and has the goal to get close
 to full support. However the following IEEE sections and features are not
 anticipated to be ever implemented for the reasons indicated.
 
-IEEE 1800-2017 3.3 recursive modules
+IEEE 1800-2017 3.3 modules within modules
     Little/no tool support, and arguably not a good practice.
 IEEE 1800-2017 6.12 "shortreal"
-    Little/no tool support, and easily simply promoted to real.
+    Little/no tool support, and easily promoted to real.
 IEEE 1800-2017 11.11 Min, typ, max
     No SDF support so will always use typical.
 IEEE 1800-2017 11.12 "let"
@@ -1205,7 +1208,7 @@ IEEE 1800-2017 33 Config
 Distribution
 ============
 
-Copyright 2008-2021 by Wilson Snyder. Verilator is free software; you can
+Copyright 2008-2022 by Wilson Snyder. Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
 

docs/spelling.txt

@@ -676,7 +676,6 @@ prev
 printf
 printtimescale
 profcfunc
-profcfuncs
 prototyptes
 ps
 pthread

docs/xml.rst

@@ -46,9 +46,6 @@ The XML document consists of 4 sections within the top level
    hierarchy. Each instance is represented with the ``<cell>`` element
    with the following attributes:
 
-   -  ``fl`` (deprecated): The file id and line number where the module
-      was instanced. Use ``loc`` instead.
-
    -  ``loc``: The file id, first line number, last line number, first
       column number and last column number of the identifier where the
       module was instanced, separated by commas.
@@ -73,7 +70,7 @@ The XML document consists of 4 sections within the top level
 Distribution
 ============
 
-Copyright 2020-2021 by Wilson Snyder. Verilator is free software; you can
+Copyright 2020-2022 by Wilson Snyder. Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
 

examples/cmake_hello_sc/Makefile

@@ -99,7 +99,7 @@ run:
 
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/cmake_tracing_sc."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
 
 clean mostlyclean distclean maintainer-clean:
 	@rm -rf build logs

examples/make_hello_c/Makefile

@@ -40,7 +40,7 @@ default:
 	obj_dir/Vtop
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/make_tracing_c."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
 
 ######################################################################
 

examples/make_hello_c/top.v

@@ -4,7 +4,8 @@
 // any use, without warranty, 2017 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top;
    initial begin
       $display("Hello World!");

examples/make_hello_sc/Makefile

@@ -49,7 +49,7 @@ run:
 	obj_dir/Vtop
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/make_tracing_sc."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
 
 ######################################################################
 

examples/make_hello_sc/top.v

@@ -4,7 +4,8 @@
 // any use, without warranty, 2017 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top;
    initial begin
       $display("Hello World!");

examples/make_protect_lib/top.v

@@ -4,7 +4,8 @@
 // any use, without warranty, 2019 by Todd Strader.
 // SPDX-License-Identifier: CC0-1.0
 
-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top (input clk);
 
    integer cyc = 0;

examples/make_tracing_c/sim_main.cpp

@@ -69,7 +69,7 @@ int main(int argc, char** argv, char** env) {
         // Historical note, before Verilator 4.200 Verilated::gotFinish()
         // was used above in place of contextp->gotFinish().
         // Most of the contextp-> calls can use Verilated:: calls instead;
-        // the Verilated:: versions simply assume there's a single context
+        // the Verilated:: versions just assume there's a single context
         // being used (per thread).  It's faster and clearer to use the
         // newer contextp-> versions.
 
@@ -103,8 +103,8 @@ int main(int argc, char** argv, char** env) {
         top->eval();
 
         // Read outputs
-        VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
-                  " -> oquad=%" VL_PRI64 "x owide=%x_%08x_%08x\n",
+        VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
+                  " owide=%x_%08x_%08x\n",
                   contextp->time(), top->clk, top->reset_l, top->in_quad, top->out_quad,
                   top->out_wide[2], top->out_wide[1], top->out_wide[0]);
     }

examples/make_tracing_sc/sc_main.cpp

@@ -58,11 +58,11 @@ int sc_main(int argc, char* argv[]) {
 
     // Define interconnect
     sc_signal<bool> reset_l;
-    sc_signal<vluint32_t> in_small;
-    sc_signal<vluint64_t> in_quad;
+    sc_signal<uint32_t> in_small;
+    sc_signal<uint64_t> in_quad;
     sc_signal<sc_bv<70>> in_wide;
-    sc_signal<vluint32_t> out_small;
-    sc_signal<vluint64_t> out_quad;
+    sc_signal<uint32_t> out_small;
+    sc_signal<uint64_t> out_quad;
     sc_signal<sc_bv<70>> out_wide;
 
     // Construct the Verilated model, from inside Vtop.h

include/gtkwave/fstapi.c

@@ -140,6 +140,10 @@ void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint3
 #include <sys/sysctl.h>
 #endif
 
+#if defined(FST_MACOSX) || defined(__MINGW32__) || defined(__OpenBSD__) || defined(__FreeBSD__)
+#define FST_UNBUFFERED_IO
+#endif
+
 #ifdef __GNUC__
 /* Boolean expression more often true than false */
 #define FST_LIKELY(x) __builtin_expect(!!(x), 1)
@@ -4577,12 +4581,11 @@ if(sectype == FST_BL_ZWRAPPER)
                 if(!fcomp) { tmpfile_close(&fcomp, &xc->f_nam); return(0); }
                 }
 
-#if defined(FST_MACOSX)
+#if defined(FST_UNBUFFERED_IO)
         setvbuf(fcomp, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
 #endif
 
 #ifdef __MINGW32__
-        setvbuf(fcomp, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
         xc->filename_unpacked = hf;
 #else
         if(hf)
@@ -4880,7 +4883,7 @@ if((!nam)||(!(xc->f=fopen(nam, "rb"))))
         char *hf = (char *)calloc(1, flen + 6);
         int rc;
 
-#if defined(__MINGW32__) || defined(FST_MACOSX)
+#if defined(FST_UNBUFFERED_IO)
         setvbuf(xc->f, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
 #endif
 
@@ -4989,9 +4992,7 @@ unsigned int secnum = 0;
 int blocks_skipped = 0;
 fst_off_t blkpos = 0;
 uint64_t seclen, beg_tim;
-#ifdef FST_DEBUG
 uint64_t end_tim;
-#endif
 uint64_t frame_uclen, frame_clen, frame_maxhandle, vc_maxhandle;
 fst_off_t vc_start;
 fst_off_t indx_pntr, indx_pos;
@@ -5058,14 +5059,11 @@ for(;;)
         if(!seclen) break;
 
         beg_tim = fstReaderUint64(xc->f);
-#ifdef FST_DEBUG
-        end_tim =
-#endif
-        fstReaderUint64(xc->f);
+        end_tim = fstReaderUint64(xc->f);
 
         if(xc->limit_range_valid)
                 {
-                if(beg_tim < xc->limit_range_start)
+                if(end_tim < xc->limit_range_start)
                         {
                         blocks_skipped++;
                         blkpos += seclen;

include/verilated.mk.in

@@ -2,28 +2,27 @@
 ######################################################################
 # DESCRIPTION: Makefile commands for all verilated target files
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ######################################################################
 
-PERL = @PERL@
-PYTHON3 = @PYTHON3@
+AR = @AR@
 CXX = @CXX@
 LINK = @CXX@
-AR = ar
-RANLIB = ranlib
 OBJCACHE ?= @OBJCACHE@
+PERL = @PERL@
+PYTHON3 = @PYTHON3@
 
 CFG_WITH_CCWARN = @CFG_WITH_CCWARN@
 CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@
 
+# Compiler flags to enable profiling
+CFG_CXXFLAGS_PROFILE = @CFG_CXXFLAGS_PROFILE@
 # Select newest language
 CFG_CXXFLAGS_STD_NEWEST = @CFG_CXXFLAGS_STD_NEWEST@
-# Select oldest language (for Verilator internal testing only)
-CFG_CXXFLAGS_STD_OLDEST = @CFG_CXXFLAGS_STD_OLDEST@
 # Compiler flags to use to turn off unused and generated code warnings, such as -Wno-div-by-zero
 CFG_CXXFLAGS_NO_UNUSED = @CFG_CXXFLAGS_NO_UNUSED@
 # Compiler flags that turn on extra warnings
@@ -104,6 +103,14 @@ OPT_FAST = -Os
 # to change this as the library is small, but can have significant speed impact.
 OPT_GLOBAL = -Os
 
+#######################################################################
+##### Profile builds
+
+ifeq ($(VM_PROFC),1)
+  CPPFLAGS += $(CFG_CXXFLAGS_PROFILE)
+  LDFLAGS  += $(CFG_CXXFLAGS_PROFILE)
+endif
+
 #######################################################################
 ##### SystemC builds
 
@@ -186,6 +193,10 @@ VK_USER_OBJS   = $(addsuffix .o, $(VM_USER_CLASSES))
 # but keeping the distinction for compatibility for now.
 VK_GLOBAL_OBJS = $(addsuffix .o, $(VM_GLOBAL_FAST) $(VM_GLOBAL_SLOW))
 
+# Need to re-build if the generated makefile changes, as compiler options might
+# have changed.
+$(VK_GLOBAL_OBJS): $(VM_PREFIX).mk
+
 ifneq ($(VM_PARALLEL_BUILDS),1)
   # Fast build for small designs: All .cpp files in one fell swoop. This
   # saves total compute, but can be slower if only a little changes. It is
@@ -216,7 +227,9 @@ endif
 	$(info Archive $(AR) -rcs $@ $^)
 	$(foreach L, $(filter-out %.a,$^), $(shell echo $L >>[email protected]_deplist.tmp))
 	@if test $(words $(filter %.a,$^)) -eq 0; then \
-		$(AR) -rcs $@ @[email protected]_deplist.tmp; \
+		$(RM) -f $@; \
+		cat [email protected]_deplist.tmp | xargs $(AR) -rc $@; \
+		$(AR) -s $@; \
 	else \
 		$(RM) -rf [email protected]; \
 		for archive in $(filter %.a,$^); do \
@@ -225,7 +238,9 @@ endif
 			$(AR) -x ../../$${archive}; \
 			cd ../..; \
 		done; \
-		$(AR) -rcs $@ @[email protected]_deplist.tmp [email protected]/*/*.o; \
+		$(RM) -f $@; \
+		cat [email protected]_deplist.tmp | xargs $(AR) -rc $@; \
+		$(AR) -rcs $@ [email protected]/*/*.o; \
 	fi \
 	; $(RM) -rf [email protected]_deplist.tmp [email protected]
 

include/verilated.v

@@ -2,7 +2,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_config.h.in

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -20,6 +20,11 @@
 // Autoconf substitutes this with the strings from AC_INIT.
 #define VERILATOR_PRODUCT "@PACKAGE_NAME@"
 
-/// Verilator version name, e.g. "1.000 2000-01-01"
+/// Verilator version name, e.g. "1.002 2000-01-01"
 // Autoconf substitutes this with the strings from AC_INIT.
 #define VERILATOR_VERSION "@PACKAGE_VERSION@"
+
+/// Verilator version number as integer
+/// As major * 100000 + minor * 1000, e.g. 1002000 == 1.002
+// Autoconf substitutes this with the strings from AC_INIT.
+#define VERILATOR_VERSION_INTEGER @VERILATOR_VERSION_INTEGER@

include/verilated_cov.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -29,6 +29,7 @@
 #include <deque>
 #include <fstream>
 #include <map>
+#include <utility>
 
 //=============================================================================
 // VerilatedCovConst
@@ -58,7 +59,7 @@ public:  // But only local to this file
         }
     }
     virtual ~VerilatedCovImpItem() = default;
-    virtual vluint64_t count() const = 0;
+    virtual uint64_t count() const = 0;
     virtual void zero() const = 0;
 };
 
@@ -75,7 +76,7 @@ private:
 public:
     // METHODS
     // cppcheck-suppress truncLongCastReturn
-    virtual vluint64_t count() const override { return *m_countp; }
+    virtual uint64_t count() const override { return *m_countp; }
     virtual void zero() const override { *m_countp = 0; }
     // CONSTRUCTORS
     // cppcheck-suppress noExplicitConstructor
@@ -132,7 +133,7 @@ private:
     int valueIndex(const std::string& value) VL_REQUIRES(m_mutex) {
         const auto iter = m_valueIndexes.find(value);
         if (iter != m_valueIndexes.end()) return iter->second;
-        m_nextIndex++;
+        ++m_nextIndex;
         assert(m_nextIndex > 0);  // Didn't rollover
         m_valueIndexes.emplace(value, m_nextIndex);
         m_indexValues.emplace(m_nextIndex, value);
@@ -143,8 +144,9 @@ private:
         std::string rtn;
         for (const char* pos = text.c_str(); *pos; ++pos) {
             if (!std::isprint(*pos) || *pos == '%' || *pos == '"') {
-                char hex[10];
-                VL_SNPRINTF(hex, 10, "%%%02X", pos[0]);
+                constexpr size_t LEN_MAX_HEX = 20;
+                char hex[LEN_MAX_HEX];
+                VL_SNPRINTF(hex, LEN_MAX_HEX, "%%%02X", pos[0]);
                 rtn += hex;
             } else {
                 rtn += *pos;
@@ -165,11 +167,11 @@ private:
                                          const std::string& value) VL_PURE {
         std::string name;
         if (key.length() == 1 && std::isalpha(key[0])) {
-            name += std::string("\001") + key;
+            name += std::string{"\001"} + key;
         } else {
-            name += std::string("\001") + dequote(key);
+            name += std::string{"\001"} + dequote(key);
         }
-        name += std::string("\002") + dequote(value);
+        name += std::string{"\002"} + dequote(value);
         return name;
     }
     static std::string combineHier(const std::string& old, const std::string& add) VL_PURE {
@@ -180,33 +182,34 @@ private:
         if (old.empty()) return add;
         if (add.empty()) return old;
 
-        const char* a = old.c_str();
-        const char* b = add.c_str();
+        const char* const a = old.c_str();
+        const char* const b = add.c_str();
 
         // Scan forward to first mismatch
         const char* apre = a;
         const char* bpre = b;
         while (*apre == *bpre) {
-            apre++;
-            bpre++;
+            ++apre;
+            ++bpre;
         }
 
         // We used to backup and split on only .'s but it seems better to be verbose
         // and not assume . is the separator
-        std::string prefix = std::string(a, apre - a);
+        const size_t prefix_len = apre - a;
+        const std::string prefix = std::string{a, prefix_len};
 
         // Scan backward to last mismatch
         const char* apost = a + std::strlen(a) - 1;
         const char* bpost = b + std::strlen(b) - 1;
         while (*apost == *bpost && apost > apre && bpost > bpre) {
-            apost--;
-            bpost--;
+            --apost;
+            --bpost;
         }
 
         // Forward to . so we have a whole word
-        std::string suffix = *bpost ? std::string(bpost + 1) : "";
+        const std::string suffix = *bpost ? std::string{bpost + 1} : "";
 
-        std::string out = prefix + "*" + suffix;
+        const std::string out = prefix + "*" + suffix;
 
         // cout << "\nch pre="<<prefix<<"  s="<<suffix<<"\nch a="<<old<<"\nch b="<<add
         // <<"\ncho="<<out<<endl;
@@ -217,7 +220,7 @@ private:
         for (int i = 0; i < VerilatedCovConst::MAX_KEYS; ++i) {
             if (itemp->m_keys[i] != VerilatedCovConst::KEY_UNDEF) {
                 // We don't compare keys, only values
-                std::string val = m_indexValues[itemp->m_vals[i]];
+                const std::string val = m_indexValues[itemp->m_vals[i]];
                 if (std::string::npos != val.find(match)) {  // Found
                     return true;
                 }
@@ -229,7 +232,7 @@ private:
         // Little selftest
 #define SELF_CHECK(got, exp) \
     do { \
-        if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest\n"); \
+        if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest"); \
     } while (0)
         SELF_CHECK(combineHier("a.b.c", "a.b.c"), "a.b.c");
         SELF_CHECK(combineHier("a.b.c", "a.b"), "a.b*");
@@ -251,19 +254,19 @@ private:
 
 public:
     // PUBLIC METHODS
-    void forcePerInstance(bool flag) VL_MT_SAFE_EXCLUDES(m_mutex) {
+    void forcePerInstance(const bool flag) VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         m_forcePerInstance = flag;
     }
     void clear() VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         clearGuts();
     }
-    void clearNonMatch(const char* matchp) VL_MT_SAFE_EXCLUDES(m_mutex) {
+    void clearNonMatch(const char* const matchp) VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         if (matchp && matchp[0]) {
             ItemList newlist;
             for (const auto& itemp : m_items) {
@@ -278,29 +281,29 @@ public:
     }
     void zero() VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         for (const auto& itemp : m_items) itemp->zero();
     }
 
     // We assume there's always call to i/f/p in that order
     void inserti(VerilatedCovImpItem* itemp) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         assert(!m_insertp);
         m_insertp = itemp;
     }
-    void insertf(const char* filenamep, int lineno) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+    void insertf(const char* const filenamep, const int lineno) VL_MT_SAFE_EXCLUDES(m_mutex) {
+        const VerilatedLockGuard lock{m_mutex};
         m_insertFilenamep = filenamep;
         m_insertLineno = lineno;
     }
     void insertp(const char* ckeyps[VerilatedCovConst::MAX_KEYS],
                  const char* valps[VerilatedCovConst::MAX_KEYS]) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         assert(m_insertp);
         // First two key/vals are filename
         ckeyps[0] = "filename";
         valps[0] = m_insertFilenamep;
-        std::string linestr = vlCovCvtToStr(m_insertLineno);
+        const std::string linestr = vlCovCvtToStr(m_insertLineno);
         ckeyps[1] = "lineno";
         valps[1] = linestr.c_str();
         // Default page if not specified
@@ -308,7 +311,8 @@ public:
         while (const char* foundp = std::strchr(fnstartp, '/')) fnstartp = foundp + 1;
         const char* fnendp = fnstartp;
         for (; *fnendp && *fnendp != '.'; fnendp++) {}
-        std::string page_default = "sp_user/" + std::string(fnstartp, fnendp - fnstartp);
+        const size_t page_len = fnendp - fnstartp;
+        const std::string page_default = "sp_user/" + std::string{fnstartp, page_len};
         ckeyps[2] = "page";
         valps[2] = page_default.c_str();
 
@@ -337,9 +341,9 @@ public:
                 // cout<<"   "<<__FUNCTION__<<"  "<<key<<" = "<<val<<endl;
                 m_insertp->m_keys[addKeynum] = valueIndex(key);
                 m_insertp->m_vals[addKeynum] = valueIndex(val);
-                addKeynum++;
+                ++addKeynum;
                 if (VL_UNCOVERABLE(!legalKey(key))) {
-                    std::string msg
+                    const std::string msg
                         = ("%Error: Coverage keys of one character, or letter+digit are illegal: "
                            + key);  // LCOV_EXCL_LINE
                     VL_FATAL_MT("", 0, "", msg.c_str());
@@ -353,22 +357,22 @@ public:
 
     void write(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
 #ifndef VM_COVERAGE
-        VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled\n");
+        VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled");
 #endif
         selftest();
 
-        std::ofstream os(filename);
+        std::ofstream os{filename};
         if (os.fail()) {
-            std::string msg = std::string("%Error: Can't write '") + filename + "'";
+            const std::string msg = std::string{"%Error: Can't write '"} + filename + "'";
             VL_FATAL_MT("", 0, "", msg.c_str());
             return;
         }
         os << "# SystemC::Coverage-3\n";
 
         // Build list of events; totalize if collapsing hierarchy
-        std::map<const std::string, std::pair<std::string, vluint64_t>> eventCounts;
+        std::map<const std::string, std::pair<std::string, uint64_t>> eventCounts;
         for (const auto& itemp : m_items) {
             std::string name;
             std::string hier;
@@ -377,8 +381,9 @@ public:
 
             for (int i = 0; i < VerilatedCovConst::MAX_KEYS; ++i) {
                 if (itemp->m_keys[i] != VerilatedCovConst::KEY_UNDEF) {
-                    std::string key = VerilatedCovKey::shortKey(m_indexValues[itemp->m_keys[i]]);
-                    std::string val = m_indexValues[itemp->m_vals[i]];
+                    const std::string key
+                        = VerilatedCovKey::shortKey(m_indexValues[itemp->m_keys[i]]);
+                    const std::string val = m_indexValues[itemp->m_vals[i]];
                     if (key == VL_CIK_PER_INSTANCE) {
                         if (val != "0") per_instance = true;
                     }
@@ -434,11 +439,11 @@ void VerilatedCovContext::clearNonMatch(const char* matchp) VL_MT_SAFE {
 }
 void VerilatedCovContext::zero() VL_MT_SAFE { impp()->zero(); }
 void VerilatedCovContext::write(const char* filenamep) VL_MT_SAFE { impp()->write(filenamep); }
-void VerilatedCovContext::_inserti(vluint32_t* itemp) VL_MT_SAFE {
-    impp()->inserti(new VerilatedCoverItemSpec<vluint32_t>(itemp));
+void VerilatedCovContext::_inserti(uint32_t* itemp) VL_MT_SAFE {
+    impp()->inserti(new VerilatedCoverItemSpec<uint32_t>{itemp});
 }
-void VerilatedCovContext::_inserti(vluint64_t* itemp) VL_MT_SAFE {
-    impp()->inserti(new VerilatedCoverItemSpec<vluint64_t>(itemp));
+void VerilatedCovContext::_inserti(uint64_t* itemp) VL_MT_SAFE {
+    impp()->inserti(new VerilatedCoverItemSpec<uint64_t>{itemp});
 }
 void VerilatedCovContext::_insertf(const char* filename, int lineno) VL_MT_SAFE {
     impp()->insertf(filename, lineno);
@@ -511,7 +516,7 @@ VerilatedCovContext* VerilatedCov::threadCovp() VL_MT_SAFE {
 VerilatedCovContext* VerilatedContext::coveragep() VL_MT_SAFE {
     static VerilatedMutex s_mutex;
     if (VL_UNLIKELY(!m_coveragep)) {
-        const VerilatedLockGuard lock(s_mutex);
+        const VerilatedLockGuard lock{s_mutex};
         if (VL_LIKELY(!m_coveragep)) {  // Not redundant, prevents race
             m_coveragep.reset(new VerilatedCovImp);
         }

include/verilated_cov.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -72,7 +72,7 @@ class VerilatedCovImp;
 ///
 /// Example:
 ///
-///     vluint32_t m_cases[10];  // Storage for coverage data
+///     uint32_t m_cases[10];  // Storage for coverage data
 ///     constructor() {
 ///         // Initialize
 ///         for (int i = 0; i < 10; ++i) m_cases[i] = 0;
@@ -126,8 +126,8 @@ public:  // But Internal use only
     // Call _insert1, followed by _insert2 and _insert3
     // Do not call directly; use VL_COVER_INSERT or higher level macros instead
     // _insert1: Remember item pointer with count.  (Not const, as may add zeroing function)
-    void _inserti(vluint32_t* itemp) VL_MT_SAFE;
-    void _inserti(vluint64_t* itemp) VL_MT_SAFE;
+    void _inserti(uint32_t* itemp) VL_MT_SAFE;
+    void _inserti(uint64_t* itemp) VL_MT_SAFE;
     // _insert2: Set default filename and line number
     void _insertf(const char* filename, int lineno) VL_MT_SAFE;
     // _insert3: Set parameters

include/verilated_cov_key.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_dpi.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -68,7 +68,7 @@ svLogic svGetBitselLogic(const svLogicVecVal* sp, int bit) {
             | (((sp[VL_BITWORD_I(bit)].bval >> VL_BITBIT_I(bit)) & 1) << 1));
 }
 
-void svPutBitselBit(svBitVecVal* dp, int bit, svBit s) { VL_ASSIGNBIT_WI(32, bit, dp, s); }
+void svPutBitselBit(svBitVecVal* dp, int bit, svBit s) { VL_ASSIGNBIT_WI(bit, dp, s); }
 void svPutBitselLogic(svLogicVecVal* dp, int bit, svLogic s) {
     // Verilator doesn't support X/Z so only aval
     dp[VL_BITWORD_I(bit)].aval = ((dp[VL_BITWORD_I(bit)].aval & ~(VL_UL(1) << VL_BITBIT_I(bit)))
@@ -79,19 +79,19 @@ void svPutBitselLogic(svLogicVecVal* dp, int bit, svLogic s) {
 
 void svGetPartselBit(svBitVecVal* dp, const svBitVecVal* sp, int lsb, int width) {
     // See also VL_SEL_WWI
-    int msb = lsb + width - 1;
-    int word_shift = VL_BITWORD_I(lsb);
+    const int msb = lsb + width - 1;
+    const int word_shift = VL_BITWORD_I(lsb);
     if (VL_BITBIT_I(lsb) == 0) {
         // Just a word extract
         for (int i = 0; i < VL_WORDS_I(width); ++i) dp[i] = sp[i + word_shift];
     } else {
-        int loffset = lsb & VL_SIZEBITS_I;
-        int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
+        const int loffset = lsb & VL_SIZEBITS_I;
+        const int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
         // Middle words
-        int words = VL_WORDS_I(msb - lsb + 1);
+        const int words = VL_WORDS_I(msb - lsb + 1);
         for (int i = 0; i < words; ++i) {
             dp[i] = sp[i + word_shift] >> loffset;
-            int upperword = i + word_shift + 1;
+            const int upperword = i + word_shift + 1;
             if (upperword <= static_cast<int>(VL_BITWORD_I(msb))) {
                 dp[i] |= sp[upperword] << nbitsfromlow;
             }
@@ -101,20 +101,20 @@ void svGetPartselBit(svBitVecVal* dp, const svBitVecVal* sp, int lsb, int width)
     dp[VL_WORDS_I(width) - 1] &= VL_MASK_I(width);
 }
 void svGetPartselLogic(svLogicVecVal* dp, const svLogicVecVal* sp, int lsb, int width) {
-    int msb = lsb + width - 1;
-    int word_shift = VL_BITWORD_I(lsb);
+    const int msb = lsb + width - 1;
+    const int word_shift = VL_BITWORD_I(lsb);
     if (VL_BITBIT_I(lsb) == 0) {
         // Just a word extract
         for (int i = 0; i < VL_WORDS_I(width); ++i) dp[i] = sp[i + word_shift];
     } else {
-        int loffset = lsb & VL_SIZEBITS_I;
-        int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
+        const int loffset = lsb & VL_SIZEBITS_I;
+        const int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
         // Middle words
-        int words = VL_WORDS_I(msb - lsb + 1);
+        const int words = VL_WORDS_I(msb - lsb + 1);
         for (int i = 0; i < words; ++i) {
             dp[i].aval = sp[i + word_shift].aval >> loffset;
             dp[i].bval = sp[i + word_shift].bval >> loffset;
-            int upperword = i + word_shift + 1;
+            const int upperword = i + word_shift + 1;
             if (upperword <= static_cast<int>(VL_BITWORD_I(msb))) {
                 dp[i].aval |= sp[upperword].aval << nbitsfromlow;
                 dp[i].bval |= sp[upperword].bval << nbitsfromlow;
@@ -127,22 +127,22 @@ void svGetPartselLogic(svLogicVecVal* dp, const svLogicVecVal* sp, int lsb, int
 }
 void svPutPartselBit(svBitVecVal* dp, const svBitVecVal s, int lbit, int width) {
     // See also _vl_insert_WI
-    int hbit = lbit + width - 1;
-    int hoffset = VL_BITBIT_I(hbit);
-    int loffset = VL_BITBIT_I(lbit);
+    const int hbit = lbit + width - 1;
+    const int hoffset = VL_BITBIT_I(hbit);
+    const int loffset = VL_BITBIT_I(lbit);
     if (hoffset == VL_SIZEBITS_I && loffset == 0) {
         // Fast and common case, word based insertion
         dp[VL_BITWORD_I(lbit)] = s;
     } else {
-        int hword = VL_BITWORD_I(hbit);
-        int lword = VL_BITWORD_I(lbit);
+        const int hword = VL_BITWORD_I(hbit);
+        const int lword = VL_BITWORD_I(lbit);
         if (hword == lword) {  // know < 32 bits because above checks it
-            IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
+            const IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
             dp[lword] = (dp[lword] & ~insmask) | ((s << loffset) & insmask);
         } else {
-            IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
-            IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
-            int nbitsonright = 32 - loffset;  // bits that end up in lword
+            const IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
+            const IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
+            const int nbitsonright = 32 - loffset;  // bits that end up in lword
             dp[lword] = (dp[lword] & ~linsmask) | ((s << loffset) & linsmask);
             dp[hword] = (dp[hword] & ~hinsmask) | ((s >> nbitsonright) & hinsmask);
         }
@@ -150,24 +150,24 @@ void svPutPartselBit(svBitVecVal* dp, const svBitVecVal s, int lbit, int width)
 }
 // cppcheck-suppress passedByValue
 void svPutPartselLogic(svLogicVecVal* dp, const svLogicVecVal s, int lbit, int width) {
-    int hbit = lbit + width - 1;
-    int hoffset = VL_BITBIT_I(hbit);
-    int loffset = VL_BITBIT_I(lbit);
+    const int hbit = lbit + width - 1;
+    const int hoffset = VL_BITBIT_I(hbit);
+    const int loffset = VL_BITBIT_I(lbit);
     if (hoffset == VL_SIZEBITS_I && loffset == 0) {
         // Fast and common case, word based insertion
         dp[VL_BITWORD_I(lbit)].aval = s.aval;
         dp[VL_BITWORD_I(lbit)].bval = s.bval;
     } else {
-        int hword = VL_BITWORD_I(hbit);
-        int lword = VL_BITWORD_I(lbit);
+        const int hword = VL_BITWORD_I(hbit);
+        const int lword = VL_BITWORD_I(lbit);
         if (hword == lword) {  // know < 32 bits because above checks it
-            IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
+            const IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
             dp[lword].aval = (dp[lword].aval & ~insmask) | ((s.aval << loffset) & insmask);
             dp[lword].bval = (dp[lword].bval & ~insmask) | ((s.bval << loffset) & insmask);
         } else {
-            IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
-            IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
-            int nbitsonright = 32 - loffset;  // bits that end up in lword
+            const IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
+            const IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
+            const int nbitsonright = 32 - loffset;  // bits that end up in lword
             dp[lword].aval = (dp[lword].aval & ~linsmask) | ((s.aval << loffset) & linsmask);
             dp[lword].bval = (dp[lword].bval & ~linsmask) | ((s.bval << loffset) & linsmask);
             dp[hword].aval = (dp[hword].aval & ~hinsmask) | ((s.aval >> nbitsonright) & hinsmask);
@@ -184,7 +184,7 @@ static inline const VerilatedDpiOpenVar* _vl_openhandle_varp(const svOpenArrayHa
         VL_FATAL_MT(__FILE__, __LINE__, "",
                     "%%Error: DPI svOpenArrayHandle function called with nullptr handle");
     }
-    const VerilatedDpiOpenVar* varp = reinterpret_cast<const VerilatedDpiOpenVar*>(h);
+    const VerilatedDpiOpenVar* const varp = reinterpret_cast<const VerilatedDpiOpenVar*>(h);
     if (VL_UNLIKELY(!varp->magicOk())) {
         VL_FATAL_MT(__FILE__, __LINE__, "",
                     "%%Error: DPI svOpenArrayHandle function called with non-Verilator handle");
@@ -205,13 +205,13 @@ int svDimensions(const svOpenArrayHandle h) { return _vl_openhandle_varp(h)->udi
 
 // Return pointer to open array data, or nullptr if not in IEEE standard C layout
 void* svGetArrayPtr(const svOpenArrayHandle h) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h);
     if (VL_UNLIKELY(!varp->isDpiStdLayout())) return nullptr;
     return varp->datap();
 }
 // Return size of open array, or 0 if not in IEEE standard C layout
 int svSizeOfArray(const svOpenArrayHandle h) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h);
     if (VL_UNLIKELY(!varp->isDpiStdLayout())) return 0;
     // Truncate 64 bits to int; DPI is limited to 4GB
     return static_cast<int>(varp->totalSize());
@@ -264,22 +264,22 @@ static void* _vl_svGetArrElemPtr(const svOpenArrayHandle h, int nargs, int indx1
                                  int indx3) VL_MT_SAFE {
     const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
     if (VL_UNLIKELY(!varp->isDpiStdLayout())) return nullptr;
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     return datap;
 }
 
 // Copy to user bit array from simulator open array
 static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int nargs,
                                       int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: d[0] = *(reinterpret_cast<CData*>(datap)); return;
     case VLVT_UINT16: d[0] = *(reinterpret_cast<SData*>(datap)); return;
     case VLVT_UINT32: d[0] = *(reinterpret_cast<IData*>(datap)); return;
     case VLVT_UINT64: {
-        WData lwp[2];
+        VlWide<2> lwp;
         VL_SET_WQ(lwp, *(reinterpret_cast<QData*>(datap)));
         d[0] = lwp[0];
         d[1] = lwp[1];
@@ -299,8 +299,8 @@ static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s,
 // Copy to user logic array from simulator open array
 static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int nargs,
                                         int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8:
@@ -316,7 +316,7 @@ static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandl
         d[0].bval = 0;
         return;
     case VLVT_UINT64: {
-        WData lwp[2];
+        VlWide<2> lwp;
         VL_SET_WQ(lwp, *(reinterpret_cast<QData*>(datap)));
         d[0].aval = lwp[0];
         d[0].bval = 0;
@@ -342,8 +342,8 @@ static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandl
 // Copy to simulator open array from from user bit array
 static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int nargs,
                                       int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: *(reinterpret_cast<CData*>(datap)) = s[0]; return;
@@ -364,8 +364,8 @@ static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecV
 // Copy to simulator open array from from user logic array
 static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s,
                                         int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: *(reinterpret_cast<CData*>(datap)) = s[0].aval; return;
@@ -386,10 +386,10 @@ static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogic
 
 // Return bit from simulator open array
 static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1, int indx2,
-                                 int indx3, int indx4) VL_MT_SAFE {
+                                 int indx3, int) VL_MT_SAFE {
     // One extra index supported, as need bit number
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return 0;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: return (*(reinterpret_cast<CData*>(datap))) & 1;
@@ -401,11 +401,11 @@ static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1
 }
 // Update simulator open array from bit
 static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int nargs, int indx1,
-                                int indx2, int indx3, int indx4) VL_MT_SAFE {
+                                int indx2, int indx3, int) VL_MT_SAFE {
     // One extra index supported, as need bit number
     value &= 1;  // Make sure clean
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: *(reinterpret_cast<CData*>(datap)) = value; return;
@@ -417,10 +417,10 @@ static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int narg
 }
 
 //======================================================================
-// DPI accessors that simply call above functions
+// DPI accessors that call above functions
 
 void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h);
     void* datap;
     va_list ap;
     va_start(ap, indx1);
@@ -428,13 +428,13 @@ void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) {
     switch (varp->udims()) {
     case 1: datap = _vl_svGetArrElemPtr(h, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         datap = _vl_svGetArrElemPtr(h, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         datap = _vl_svGetArrElemPtr(h, 3, indx1, indx2, indx3);
         break;
     }
@@ -454,19 +454,19 @@ void* svGetArrElemPtr3(const svOpenArrayHandle h, int indx1, int indx2, int indx
 }
 
 void svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutBitArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutBitArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -486,19 +486,19 @@ void svPutBitArrElem3VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int
     _vl_svPutBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
 }
 void svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutLogicArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutLogicArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -522,19 +522,19 @@ void svPutLogicArrElem3VecVal(const svOpenArrayHandle d, const svLogicVecVal* s,
 // From simulator storage into user space
 
 void svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svGetBitArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svGetBitArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svGetBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -553,19 +553,19 @@ void svGetBitArrElem3VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1
     _vl_svGetBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
 }
 void svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svGetLogicArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svGetLogicArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svGetLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -585,20 +585,20 @@ void svGetLogicArrElem3VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int i
 }
 
 svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     svBit out;
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: out = _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -618,20 +618,20 @@ svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx
 }
 svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...) {
     // Verilator doesn't support X/Z so can just call Bit version
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     svBit out;
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: out = _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -654,19 +654,19 @@ svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int
 }
 
 void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -685,19 +685,19 @@ void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1, int ind
 }
 void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, ...) {
     // Verilator doesn't support X/Z so can just call Bit version
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -732,15 +732,15 @@ svScope svGetScope() {
 }
 
 svScope svSetScope(const svScope scope) {
-    const VerilatedScope* prevScopep = Verilated::dpiScope();
-    const VerilatedScope* vscopep = reinterpret_cast<const VerilatedScope*>(scope);
+    const VerilatedScope* const prevScopep = Verilated::dpiScope();
+    const VerilatedScope* const vscopep = reinterpret_cast<const VerilatedScope*>(scope);
     Verilated::dpiScope(vscopep);
     // NOLINTNEXTLINE(google-readability-casting)
     return (svScope)(prevScopep);
 }
 
 const char* svGetNameFromScope(const svScope scope) {
-    const VerilatedScope* vscopep = reinterpret_cast<const VerilatedScope*>(scope);
+    const VerilatedScope* const vscopep = reinterpret_cast<const VerilatedScope*>(scope);
     return vscopep->name();
 }
 

include/verilated_dpi.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -37,7 +37,7 @@
 
 // Convert svBitVecVal to Verilator internal data
 static inline void VL_SET_W_SVBV(int obits, WDataOutP owp, const svBitVecVal* lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i];
     owp[words - 1] = lwp[words - 1] & VL_MASK_I(obits);
 }
@@ -47,20 +47,20 @@ static inline QData VL_SET_Q_SVBV(const svBitVecVal* lwp) VL_MT_SAFE {
 static inline IData VL_SET_I_SVBV(const svBitVecVal* lwp) VL_MT_SAFE { return lwp[0]; }
 
 // Convert Verilator internal data to svBitVecVal
-static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, WDataInP lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, const WDataInP lwp) VL_MT_SAFE {
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i];
     owp[words - 1] = lwp[words - 1] & VL_MASK_I(obits);
 }
-static inline void VL_SET_SVBV_I(int, svBitVecVal* owp, IData ld) VL_MT_SAFE { owp[0] = ld; }
-static inline void VL_SET_SVBV_Q(int, svBitVecVal* owp, QData ld) VL_MT_SAFE {
+static inline void VL_SET_SVBV_I(int, svBitVecVal* owp, const IData ld) VL_MT_SAFE { owp[0] = ld; }
+static inline void VL_SET_SVBV_Q(int, svBitVecVal* owp, const QData ld) VL_MT_SAFE {
     VL_SET_WQ(owp, ld);
 }
 
 // Convert svLogicVecVal to Verilator internal data
 // Note these functions ignore X/Z in svLogicVecVal
 static inline void VL_SET_W_SVLV(int obits, WDataOutP owp, const svLogicVecVal* lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i].aval;
     owp[words - 1] = lwp[words - 1].aval & VL_MASK_I(obits);
 }
@@ -71,18 +71,18 @@ static inline IData VL_SET_I_SVLV(const svLogicVecVal* lwp) VL_MT_SAFE { return
 
 // Convert Verilator internal data to svLogicVecVal
 // Note these functions never create X/Z in svLogicVecVal
-static inline void VL_SET_SVLV_W(int obits, svLogicVecVal* owp, WDataInP lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+static inline void VL_SET_SVLV_W(int obits, svLogicVecVal* owp, const WDataInP lwp) VL_MT_SAFE {
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words; ++i) owp[i].bval = 0;
     for (int i = 0; i < words - 1; ++i) owp[i].aval = lwp[i];
     owp[words - 1].aval = lwp[words - 1] & VL_MASK_I(obits);
 }
-static inline void VL_SET_SVLV_I(int, svLogicVecVal* owp, IData ld) VL_MT_SAFE {
+static inline void VL_SET_SVLV_I(int, svLogicVecVal* owp, const IData ld) VL_MT_SAFE {
     owp[0].aval = ld;
     owp[0].bval = 0;
 }
-static inline void VL_SET_SVLV_Q(int, svLogicVecVal* owp, QData ld) VL_MT_SAFE {
-    WData lwp[2];
+static inline void VL_SET_SVLV_Q(int, svLogicVecVal* owp, const QData ld) VL_MT_SAFE {
+    VlWide<2> lwp;
     VL_SET_WQ(lwp, ld);
     owp[0].aval = lwp[0];
     owp[0].bval = 0;

include/verilated_fst_c.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -53,29 +53,31 @@
 
 //=============================================================================
 // Check that vltscope_t matches fstScopeType
-static_assert((int)FST_ST_VCD_MODULE == (int)VLT_TRACE_SCOPE_MODULE,
+
+static_assert(static_cast<int>(FST_ST_VCD_MODULE) == static_cast<int>(VLT_TRACE_SCOPE_MODULE),
               "VLT_TRACE_SCOPE_MODULE mismatches");
-static_assert((int)FST_ST_VCD_TASK == (int)VLT_TRACE_SCOPE_TASK,
+static_assert(static_cast<int>(FST_ST_VCD_TASK) == static_cast<int>(VLT_TRACE_SCOPE_TASK),
               "VLT_TRACE_SCOPE_TASK mismatches");
-static_assert((int)FST_ST_VCD_FUNCTION == (int)VLT_TRACE_SCOPE_FUNCTION,
+static_assert(static_cast<int>(FST_ST_VCD_FUNCTION) == static_cast<int>(VLT_TRACE_SCOPE_FUNCTION),
               "VLT_TRACE_SCOPE_FUNCTION mismatches");
-static_assert((int)FST_ST_VCD_BEGIN == (int)VLT_TRACE_SCOPE_BEGIN,
+static_assert(static_cast<int>(FST_ST_VCD_BEGIN) == static_cast<int>(VLT_TRACE_SCOPE_BEGIN),
               "VLT_TRACE_SCOPE_BEGIN mismatches");
-static_assert((int)FST_ST_VCD_FORK == (int)VLT_TRACE_SCOPE_FORK,
+static_assert(static_cast<int>(FST_ST_VCD_FORK) == static_cast<int>(VLT_TRACE_SCOPE_FORK),
               "VLT_TRACE_SCOPE_FORK mismatches");
-static_assert((int)FST_ST_VCD_GENERATE == (int)VLT_TRACE_SCOPE_GENERATE,
+static_assert(static_cast<int>(FST_ST_VCD_GENERATE) == static_cast<int>(VLT_TRACE_SCOPE_GENERATE),
               "VLT_TRACE_SCOPE_GENERATE mismatches");
-static_assert((int)FST_ST_VCD_STRUCT == (int)VLT_TRACE_SCOPE_STRUCT,
+static_assert(static_cast<int>(FST_ST_VCD_STRUCT) == static_cast<int>(VLT_TRACE_SCOPE_STRUCT),
               "VLT_TRACE_SCOPE_STRUCT mismatches");
-static_assert((int)FST_ST_VCD_UNION == (int)VLT_TRACE_SCOPE_UNION,
+static_assert(static_cast<int>(FST_ST_VCD_UNION) == static_cast<int>(VLT_TRACE_SCOPE_UNION),
               "VLT_TRACE_SCOPE_UNION mismatches");
-static_assert((int)FST_ST_VCD_CLASS == (int)VLT_TRACE_SCOPE_CLASS,
+static_assert(static_cast<int>(FST_ST_VCD_CLASS) == static_cast<int>(VLT_TRACE_SCOPE_CLASS),
               "VLT_TRACE_SCOPE_CLASS mismatches");
-static_assert((int)FST_ST_VCD_INTERFACE == (int)VLT_TRACE_SCOPE_INTERFACE,
+static_assert(static_cast<int>(FST_ST_VCD_INTERFACE)
+                  == static_cast<int>(VLT_TRACE_SCOPE_INTERFACE),
               "VLT_TRACE_SCOPE_INTERFACE mismatches");
-static_assert((int)FST_ST_VCD_PACKAGE == (int)VLT_TRACE_SCOPE_PACKAGE,
+static_assert(static_cast<int>(FST_ST_VCD_PACKAGE) == static_cast<int>(VLT_TRACE_SCOPE_PACKAGE),
               "VLT_TRACE_SCOPE_PACKAGE mismatches");
-static_assert((int)FST_ST_VCD_PROGRAM == (int)VLT_TRACE_SCOPE_PROGRAM,
+static_assert(static_cast<int>(FST_ST_VCD_PROGRAM) == static_cast<int>(VLT_TRACE_SCOPE_PROGRAM),
               "VLT_TRACE_SCOPE_PROGRAM mismatches");
 
 //=============================================================================
@@ -98,7 +100,7 @@ VerilatedFst::~VerilatedFst() {
 }
 
 void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
-    const VerilatedLockGuard lock(m_mutex);
+    const VerilatedLockGuard lock{m_mutex};
     m_fst = fstWriterCreate(filename, 1);
     fstWriterSetPackType(m_fst, FST_WR_PT_LZ4);
     fstWriterSetTimescaleFromString(m_fst, timeResStr().c_str());  // lintok-begin-on-ref
@@ -120,7 +122,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 
     // convert m_code2symbol into an array for fast lookup
     if (!m_symbolp) {
-        m_symbolp = new fstHandle[nextCode()];
+        m_symbolp = new fstHandle[nextCode()]{0};
         for (const auto& i : m_code2symbol) m_symbolp[i.first] = i.second;
     }
     m_code2symbol.clear();
@@ -130,44 +132,46 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 }
 
 void VerilatedFst::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
-    const VerilatedLockGuard lock(m_mutex);
+    const VerilatedLockGuard lock{m_mutex};
     VerilatedTrace<VerilatedFst>::closeBase();
     fstWriterClose(m_fst);
     m_fst = nullptr;
 }
 
 void VerilatedFst::flush() VL_MT_SAFE_EXCLUDES(m_mutex) {
-    const VerilatedLockGuard lock(m_mutex);
+    const VerilatedLockGuard lock{m_mutex};
     VerilatedTrace<VerilatedFst>::flushBase();
     fstWriterFlushContext(m_fst);
 }
 
-void VerilatedFst::emitTimeChange(vluint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); }
+void VerilatedFst::emitTimeChange(uint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); }
 
 //=============================================================================
 // Decl
 
-void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elements,
+void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elements,
                                  unsigned int minValbits, const char** itemNamesp,
                                  const char** itemValuesp) {
-    fstEnumHandle enumNum
+    const fstEnumHandle enumNum
         = fstWriterCreateEnumTable(m_fst, name, elements, minValbits, itemNamesp, itemValuesp);
     m_local2fstdtype[dtypenum] = enumNum;
 }
 
-void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
-                           fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
+void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                           fstVarType vartype, bool array, int arraynum, bool bussed, int msb,
+                           int lsb) {
     const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1;
 
-    VerilatedTrace<VerilatedFst>::declCode(code, bits, false);
+    const bool enabled = VerilatedTrace<VerilatedFst>::declCode(code, name, bits, false);
+    if (!enabled) return;
 
-    std::istringstream nameiss(name);
+    std::string nameasstr = namePrefix() + name;
+    std::istringstream nameiss{nameasstr};
     std::istream_iterator<std::string> beg(nameiss);
     std::istream_iterator<std::string> end;
     std::list<std::string> tokens(beg, end);  // Split name
-    std::string symbol_name(tokens.back());
+    std::string symbol_name{tokens.back()};
     tokens.pop_back();  // Remove symbol name from hierarchy
-    tokens.insert(tokens.begin(), moduleName());  // Add current module to the hierarchy
     std::string tmpModName;
 
     // Find point where current and new scope diverge
@@ -191,22 +195,23 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV
             tmpModName = *new_it;
             tmpModName.pop_back();
             // If the scope ends with a non-ascii character, it will be 0x80 + fstScopeType
-            fstWriterSetScope(m_fst, (fstScopeType)(new_it->back() & 0x7f), tmpModName.c_str(),
-                              nullptr);
-        } else
+            fstWriterSetScope(m_fst, static_cast<fstScopeType>(new_it->back() & 0x7f),
+                              tmpModName.c_str(), nullptr);
+        } else {
             fstWriterSetScope(m_fst, FST_ST_VCD_SCOPE, new_it->c_str(), nullptr);
-
+        }
         m_curScope.push_back(*new_it);
         new_it = tokens.erase(new_it);
     }
 
     std::stringstream name_ss;
     name_ss << symbol_name;
-    if (array) name_ss << "(" << arraynum << ")";
+    if (array) name_ss << "[" << arraynum << "]";
+    if (bussed) name_ss << " [" << msb << ":" << lsb << "]";
     std::string name_str = name_ss.str();
 
     if (dtypenum > 0) {
-        fstEnumHandle enumNum = m_local2fstdtype[dtypenum];
+        const fstEnumHandle enumNum = m_local2fstdtype[dtypenum];
         fstWriterEmitEnumTableRef(m_fst, enumNum);
     }
 
@@ -219,25 +224,25 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV
     }
 }
 
-void VerilatedFst::declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                            fstVarType vartype, bool array, int arraynum) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, 0, 0);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0);
 }
-void VerilatedFst::declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                            fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb);
 }
-void VerilatedFst::declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declQuad(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                             fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb);
 }
-void VerilatedFst::declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declArray(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                              fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb);
 }
-void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declDouble(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                               fstVarType vartype, bool array, int arraynum) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, 63, 0);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 63, 0);
 }
 
 // Note: emit* are only ever called from one place (full* in
@@ -245,40 +250,45 @@ void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, f
 // so always inline them.
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitBit(vluint32_t code, CData newval) {
+void VerilatedFst::emitBit(uint32_t code, CData newval) {
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     fstWriterEmitValueChange(m_fst, m_symbolp[code], newval ? "1" : "0");
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) {
+void VerilatedFst::emitCData(uint32_t code, CData newval, int bits) {
     char buf[VL_BYTESIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtCDataToStr(buf, newval << (VL_BYTESIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) {
+void VerilatedFst::emitSData(uint32_t code, SData newval, int bits) {
     char buf[VL_SHORTSIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtSDataToStr(buf, newval << (VL_SHORTSIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) {
+void VerilatedFst::emitIData(uint32_t code, IData newval, int bits) {
     char buf[VL_IDATASIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtIDataToStr(buf, newval << (VL_IDATASIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitQData(vluint32_t code, QData newval, int bits) {
+void VerilatedFst::emitQData(uint32_t code, QData newval, int bits) {
     char buf[VL_QUADSIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtQDataToStr(buf, newval << (VL_QUADSIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) {
+void VerilatedFst::emitWData(uint32_t code, const WData* newvalp, int bits) {
     int words = VL_WORDS_I(bits);
     char* wp = m_strbuf;
     // Convert the most significant word
@@ -294,6 +304,6 @@ void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) {
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitDouble(vluint32_t code, double newval) {
+void VerilatedFst::emitDouble(uint32_t code, double newval) {
     fstWriterEmitValueChange(m_fst, m_symbolp[code], &newval);
 }

include/verilated_fst_c.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -45,7 +45,7 @@ private:
     // FST specific internals
 
     void* m_fst;
-    std::map<vluint32_t, fstHandle> m_code2symbol;
+    std::map<uint32_t, fstHandle> m_code2symbol;
     std::map<int, fstEnumHandle> m_local2fstdtype;
     std::list<std::string> m_curScope;
     fstHandle* m_symbolp = nullptr;  // same as m_code2symbol, but as an array
@@ -53,15 +53,15 @@ private:
 
     // CONSTRUCTORS
     VL_UNCOPYABLE(VerilatedFst);
-    void declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
-                 fstVarType vartype, bool array, int arraynum, int msb, int lsb);
+    void declare(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                 fstVarType vartype, bool array, int arraynum, bool bussed, int msb, int lsb);
 
 protected:
     //=========================================================================
     // Implementation of VerilatedTrace interface
 
     // Implementations of protected virtual methods for VerilatedTrace
-    virtual void emitTimeChange(vluint64_t timeui) override;
+    virtual void emitTimeChange(uint64_t timeui) override;
 
     // Hooks called from VerilatedTrace
     virtual bool preFullDump() override { return isOpen(); }
@@ -69,13 +69,13 @@ protected:
 
     // Implementations of duck-typed methods for VerilatedTrace. These are
     // called from only one place (namely full*) so always inline them.
-    inline void emitBit(vluint32_t code, CData newval);
-    inline void emitCData(vluint32_t code, CData newval, int bits);
-    inline void emitSData(vluint32_t code, SData newval, int bits);
-    inline void emitIData(vluint32_t code, IData newval, int bits);
-    inline void emitQData(vluint32_t code, QData newval, int bits);
-    inline void emitWData(vluint32_t code, const WData* newvalp, int bits);
-    inline void emitDouble(vluint32_t code, double newval);
+    inline void emitBit(uint32_t code, CData newval);
+    inline void emitCData(uint32_t code, CData newval, int bits);
+    inline void emitSData(uint32_t code, SData newval, int bits);
+    inline void emitIData(uint32_t code, IData newval, int bits);
+    inline void emitQData(uint32_t code, QData newval, int bits);
+    inline void emitWData(uint32_t code, const WData* newvalp, int bits);
+    inline void emitDouble(uint32_t code, double newval);
 
 public:
     //=========================================================================
@@ -98,29 +98,30 @@ public:
     // Internal interface to Verilator generated code
 
     // Inside dumping routines, declare a data type
-    void declDTypeEnum(int dtypenum, const char* name, vluint32_t elements,
-                       unsigned int minValbits, const char** itemNamesp, const char** itemValuesp);
+    void declDTypeEnum(int dtypenum, const char* name, uint32_t elements, unsigned int minValbits,
+                       const char** itemNamesp, const char** itemValuesp);
 
     // Inside dumping routines, declare a signal
-    void declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                  fstVarType vartype, bool array, int arraynum);
-    void declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                  fstVarType vartype, bool array, int arraynum, int msb, int lsb);
-    void declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declQuad(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                   fstVarType vartype, bool array, int arraynum, int msb, int lsb);
-    void declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declArray(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                    fstVarType vartype, bool array, int arraynum, int msb, int lsb);
-    void declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declDouble(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                     fstVarType vartype, bool array, int arraynum);
 };
 
 #ifndef DOXYGEN
 // Declare specialization here as it's used in VerilatedFstC just below
-template <> void VerilatedTrace<VerilatedFst>::dump(vluint64_t timeui);
+template <> void VerilatedTrace<VerilatedFst>::dump(uint64_t timeui);
 template <> void VerilatedTrace<VerilatedFst>::set_time_unit(const char* unitp);
 template <> void VerilatedTrace<VerilatedFst>::set_time_unit(const std::string& unit);
 template <> void VerilatedTrace<VerilatedFst>::set_time_resolution(const char* unitp);
 template <> void VerilatedTrace<VerilatedFst>::set_time_resolution(const std::string& unit);
+template <> void VerilatedTrace<VerilatedFst>::dumpvars(int level, const std::string& hier);
 #endif
 
 //=============================================================================
@@ -139,7 +140,7 @@ public:
     explicit VerilatedFstC(void* filep = nullptr)
         : m_sptrace{filep} {}
     /// Destruct, flush, and close the dump
-    ~VerilatedFstC() { close(); }
+    virtual ~VerilatedFstC() { close(); }
 
     // METHODS - User called
 
@@ -154,12 +155,12 @@ public:
     /// Write one cycle of dump data
     /// Call with the current context's time just after eval'ed,
     /// e.g. ->dump(contextp->time())
-    void dump(vluint64_t timeui) { m_sptrace.dump(timeui); }
+    void dump(uint64_t timeui) { m_sptrace.dump(timeui); }
     /// Write one cycle of dump data - backward compatible and to reduce
-    /// conversion warnings.  It's better to use a vluint64_t time instead.
-    void dump(double timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
-    void dump(vluint32_t timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
-    void dump(int timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
+    /// conversion warnings.  It's better to use a uint64_t time instead.
+    void dump(double timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+    void dump(uint32_t timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+    void dump(int timestamp) { dump(static_cast<uint64_t>(timestamp)); }
 
     // METHODS - Internal/backward compatible
     // \protectedsection
@@ -178,9 +179,14 @@ public:
     void set_time_resolution(const std::string& unit) VL_MT_SAFE {
         m_sptrace.set_time_resolution(unit);
     }
+    // Set variables to dump, using $dumpvars format
+    // If level = 0, dump everything and hier is then ignored
+    void dumpvars(int level, const std::string& hier) VL_MT_SAFE {
+        m_sptrace.dumpvars(level, hier);
+    }
 
     // Internal class access
-    inline VerilatedFst* spTrace() { return &m_sptrace; };
+    inline VerilatedFst* spTrace() { return &m_sptrace; }
 };
 
 #endif  // guard

include/verilated_fst_sc.cpp

@@ -3,7 +3,7 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -27,6 +27,17 @@
 //======================================================================
 //======================================================================
 
+void VerilatedFstSc::open(const char* filename) {
+    if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+        vl_fatal(__FILE__, __LINE__, "VerilatedFstSc",
+                 ("%Error: VerilatedFstSc::open(\"" + std::string(filename)
+                  + "\") is called before sc_core::sc_start(). "
+                    "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.")
+                     .c_str());
+    }
+    VerilatedFstC::open(filename);
+}
+
 //--------------------------------------------------
 // SystemC 2.1.v1
 // cppcheck-suppress unusedFunction

include/verilated_fst_sc.h

@@ -1,7 +1,7 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //=============================================================================
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -26,6 +26,8 @@
 #include "verilated_sc.h"
 #include "verilated_fst_c.h"
 
+#include <string>
+
 //=============================================================================
 // VerilatedFstSc
 ///
@@ -42,9 +44,9 @@ public:
         // We want to avoid a depreciated warning, but still be back compatible.
         // Turning off the message just for this still results in an
         // annoying "to turn off" message.
-        sc_time t1sec(1, SC_SEC);
+        const sc_time t1sec(1, SC_SEC);
         if (t1sec.to_default_time_units() != 0) {
-            sc_time tunits(1.0 / t1sec.to_default_time_units(), SC_SEC);
+            const sc_time tunits(1.0 / t1sec.to_default_time_units(), SC_SEC);
             spTrace()->set_time_unit(tunits.to_string());
         }
         spTrace()->set_time_resolution(sc_get_time_resolution().to_string());
@@ -57,6 +59,9 @@ public:
         if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); }
     }
 
+    // Override VerilatedFstC. Must be called after starting simulation.
+    virtual void open(const char* filename) /*override*/ VL_MT_SAFE;
+
 private:
     /// Fake outs for linker
 

include/verilated_heavy.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2010-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2010-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -12,970 +12,20 @@
 //*************************************************************************
 ///
 /// \file
-/// \brief Verilated string and data-type header
+/// \brief Verilated old string and data-type header
 ///
-/// This file is included automatically by Verilator at the top of
-/// all C++ files it generates.  It is used when strings or other
-/// heavyweight types are required; these contents are not part of
-/// verilated.h to save compile time when such types aren't used.
+/// This file is deprecated, and provided for backwards compatibility.
+/// Include verilated.h instead.
 ///
 //*************************************************************************
 
 #ifndef VERILATOR_VERILATED_HEAVY_H_
 #define VERILATOR_VERILATED_HEAVY_H_
 
+#ifdef VL_NO_LEGACY
+#error "Include <verilated.h> instead of <verilated_heavy.h>"
+#endif
+
 #include "verilated.h"
 
-#include <algorithm>
-#include <array>
-#include <deque>
-#include <map>
-#include <memory>
-#include <set>
-#include <string>
-#include <unordered_set>
-
-//===================================================================
-// String formatters (required by below containers)
-
-extern std::string VL_TO_STRING(CData lhs);
-extern std::string VL_TO_STRING(SData lhs);
-extern std::string VL_TO_STRING(IData lhs);
-extern std::string VL_TO_STRING(QData lhs);
-inline std::string VL_TO_STRING(const std::string& obj) { return "\"" + obj + "\""; }
-extern std::string VL_TO_STRING_W(int words, WDataInP obj);
-
-//===================================================================
-// Shuffle RNG
-
-class VlURNG final {
-public:
-    using result_type = size_t;
-    static constexpr size_t min() { return 0; }
-    static constexpr size_t max() { return 1ULL << 31; }
-    size_t operator()() { return VL_MASK_I(31) & VL_RANDOM_I(32); }
-};
-
-//===================================================================
-// Readmem/Writemem operation classes
-
-class VlReadMem final {
-    bool m_hex;  // Hex format
-    int m_bits;  // Bit width of values
-    const std::string& m_filename;  // Filename
-    QData m_end;  // End address (as specified by user)
-    FILE* m_fp;  // File handle for filename
-    QData m_addr;  // Next address to read
-    int m_linenum;  // Line number last read from file
-public:
-    VlReadMem(bool hex, int bits, const std::string& filename, QData start, QData end);
-    ~VlReadMem();
-    bool isOpen() const { return m_fp != nullptr; }
-    int linenum() const { return m_linenum; }
-    bool get(QData& addrr, std::string& valuer);
-    void setData(void* valuep, const std::string& rhs);
-};
-
-class VlWriteMem final {
-    bool m_hex;  // Hex format
-    int m_bits;  // Bit width of values
-    FILE* m_fp;  // File handle for filename
-    QData m_addr;  // Next address to write
-public:
-    VlWriteMem(bool hex, int bits, const std::string& filename, QData start, QData end);
-    ~VlWriteMem();
-    bool isOpen() const { return m_fp != nullptr; }
-    void print(QData addr, bool addrstamp, const void* valuep);
-};
-
-//===================================================================
-/// Verilog wide unpacked bit container.
-/// Similar to std::array<WData, N>, but lighter weight, only methods needed
-/// by Verilator, to help compile time.
-///
-/// For example a Verilog "bit [94:0]" will become a VlWide<3> because 3*32
-/// bits are needed to hold the 95 bits. The MSB (bit 96) must always be
-/// zero in memory, but during intermediate operations in the Verilated
-/// internals is unpredictable.
-
-template <std::size_t T_Words> class VlWide final {
-    EData m_storage[T_Words];
-
-public:
-    // cppcheck-suppress uninitVar
-    VlWide() = default;
-    ~VlWide() = default;
-    VlWide(const VlWide&) = default;
-    VlWide(VlWide&&) = default;
-
-    // OPERATOR METHODS
-    VlWide& operator=(const VlWide&) = default;
-    VlWide& operator=(VlWide&&) = default;
-    const EData& operator[](size_t index) const { return m_storage[index]; };
-    EData& operator[](size_t index) { return m_storage[index]; };
-    operator WDataOutP() { return &m_storage[0]; }
-    operator WDataInP() const { return &m_storage[0]; }
-
-    // METHODS
-    const EData& at(size_t index) const { return m_storage[index]; }
-    EData& at(size_t index) { return m_storage[index]; }
-    WData* data() { return &m_storage[0]; }
-    const WData* data() const { return &m_storage[0]; }
-    bool operator<(const VlWide<T_Words>& rhs) const {
-        return VL_LT_W(T_Words, data(), rhs.data());
-    }
-};
-
-// Convert a C array to std::array reference by pointer magic, without copy.
-// Data type (second argument) is so the function template can automatically generate.
-template <std::size_t T_Words> VlWide<T_Words>& VL_CVT_W_A(WDataInP inp, const VlWide<T_Words>&) {
-    return *((VlWide<T_Words>*)inp);
-}
-
-template <std::size_t T_Words> std::string VL_TO_STRING(const VlWide<T_Words>& obj) {
-    return VL_TO_STRING_W(T_Words, obj.data());
-}
-
-//===================================================================
-// Verilog queue and dynamic array container
-// There are no multithreaded locks on this; the base variable must
-// be protected by other means
-//
-// Bound here is the maximum size() allowed, e.g. 1 + SystemVerilog bound
-// For dynamic arrays it is always zero
-template <class T_Value, size_t T_MaxSize = 0> class VlQueue final {
-private:
-    // TYPES
-    using Deque = std::deque<T_Value>;
-
-public:
-    using const_iterator = typename Deque::const_iterator;
-
-private:
-    // MEMBERS
-    Deque m_deque;  // State of the assoc array
-    T_Value m_defaultValue;  // Default value
-
-public:
-    // CONSTRUCTORS
-    // m_defaultValue isn't defaulted. Caller's constructor must do it.
-    VlQueue() = default;
-    ~VlQueue() = default;
-    VlQueue(const VlQueue&) = default;
-    VlQueue(VlQueue&&) = default;
-    VlQueue& operator=(const VlQueue&) = default;
-    VlQueue& operator=(VlQueue&&) = default;
-
-    // Standard copy constructor works. Verilog: assoca = assocb
-    // Also must allow conversion from a different T_MaxSize queue
-    template <size_t U_MaxSize = 0> VlQueue operator=(const VlQueue<T_Value, U_MaxSize>& rhs) {
-        m_deque = rhs.privateDeque();
-        if (VL_UNLIKELY(T_MaxSize && T_MaxSize < m_deque.size())) m_deque.resize(T_MaxSize - 1);
-        return *this;
-    }
-
-    static VlQueue cons(const T_Value& lhs) {
-        VlQueue out;
-        out.push_back(lhs);
-        return out;
-    }
-    static VlQueue cons(const T_Value& lhs, const T_Value& rhs) {
-        VlQueue out;
-        out.push_back(rhs);
-        out.push_back(lhs);
-        return out;
-    }
-    static VlQueue cons(const VlQueue& lhs, const T_Value& rhs) {
-        VlQueue out = lhs;
-        out.push_front(rhs);
-        return out;
-    }
-    static VlQueue cons(const T_Value& lhs, const VlQueue& rhs) {
-        VlQueue out = rhs;
-        out.push_back(lhs);
-        return out;
-    }
-    static VlQueue cons(const VlQueue& lhs, const VlQueue& rhs) {
-        VlQueue out = rhs;
-        for (const auto& i : lhs.m_deque) out.push_back(i);
-        return out;
-    }
-
-    // METHODS
-    T_Value& atDefault() { return m_defaultValue; }
-    const T_Value& atDefault() const { return m_defaultValue; }
-    const Deque& privateDeque() const { return m_deque; }
-
-    // Size. Verilog: function int size(), or int num()
-    int size() const { return m_deque.size(); }
-    // Clear array. Verilog: function void delete([input index])
-    void clear() { m_deque.clear(); }
-    void erase(vlsint32_t index) {
-        if (VL_LIKELY(index >= 0 && index < m_deque.size()))
-            m_deque.erase(m_deque.begin() + index);
-    }
-
-    // Dynamic array new[] becomes a renew()
-    void renew(size_t size) {
-        clear();
-        m_deque.resize(size, atDefault());
-    }
-    // Dynamic array new[]() becomes a renew_copy()
-    void renew_copy(size_t size, const VlQueue<T_Value, T_MaxSize>& rhs) {
-        if (size == 0) {
-            clear();
-        } else {
-            *this = rhs;
-            m_deque.resize(size, atDefault());
-        }
-    }
-
-    // function void q.push_front(value)
-    void push_front(const T_Value& value) {
-        m_deque.push_front(value);
-        if (VL_UNLIKELY(T_MaxSize != 0 && m_deque.size() > T_MaxSize)) m_deque.pop_back();
-    }
-    // function void q.push_back(value)
-    void push_back(const T_Value& value) {
-        if (VL_LIKELY(T_MaxSize == 0 || m_deque.size() < T_MaxSize)) m_deque.push_back(value);
-    }
-    // function value_t q.pop_front();
-    T_Value pop_front() {
-        if (m_deque.empty()) return m_defaultValue;
-        T_Value v = m_deque.front();
-        m_deque.pop_front();
-        return v;
-    }
-    // function value_t q.pop_back();
-    T_Value pop_back() {
-        if (m_deque.empty()) return m_defaultValue;
-        T_Value v = m_deque.back();
-        m_deque.pop_back();
-        return v;
-    }
-
-    // Setting. Verilog: assoc[index] = v
-    // Can't just overload operator[] or provide a "at" reference to set,
-    // because we need to be able to insert only when the value is set
-    T_Value& at(vlsint32_t index) {
-        static T_Value s_throwAway;
-        // Needs to work for dynamic arrays, so does not use T_MaxSize
-        if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) {
-            s_throwAway = atDefault();
-            return s_throwAway;
-        } else {
-            return m_deque[index];
-        }
-    }
-    // Accessing. Verilog: v = assoc[index]
-    const T_Value& at(vlsint32_t index) const {
-        static T_Value s_throwAway;
-        // Needs to work for dynamic arrays, so does not use T_MaxSize
-        if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) {
-            return atDefault();
-        } else {
-            return m_deque[index];
-        }
-    }
-    // function void q.insert(index, value);
-    void insert(vlsint32_t index, const T_Value& value) {
-        if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) return;
-        m_deque.insert(m_deque.begin() + index, value);
-    }
-
-    // Return slice q[lsb:msb]
-    VlQueue slice(vlsint32_t lsb, vlsint32_t msb) const {
-        VlQueue out;
-        if (VL_UNLIKELY(lsb < 0)) lsb = 0;
-        if (VL_UNLIKELY(lsb >= m_deque.size())) lsb = m_deque.size() - 1;
-        if (VL_UNLIKELY(msb >= m_deque.size())) msb = m_deque.size() - 1;
-        for (vlsint32_t i = lsb; i <= msb; ++i) out.push_back(m_deque[i]);
-        return out;
-    }
-
-    // For save/restore
-    const_iterator begin() const { return m_deque.begin(); }
-    const_iterator end() const { return m_deque.end(); }
-
-    // Methods
-    void sort() { std::sort(m_deque.begin(), m_deque.end()); }
-    template <typename Func> void sort(Func with_func) {
-        // with_func returns arbitrary type to use for the sort comparison
-        std::sort(m_deque.begin(), m_deque.end(), [=](const T_Value& a, const T_Value& b) {
-            // index number is meaninless with sort, as it changes
-            return with_func(0, a) < with_func(0, b);
-        });
-    }
-    void rsort() { std::sort(m_deque.rbegin(), m_deque.rend()); }
-    template <typename Func> void rsort(Func with_func) {
-        // with_func returns arbitrary type to use for the sort comparison
-        std::sort(m_deque.rbegin(), m_deque.rend(), [=](const T_Value& a, const T_Value& b) {
-            // index number is meaninless with sort, as it changes
-            return with_func(0, a) < with_func(0, b);
-        });
-    }
-    void reverse() { std::reverse(m_deque.begin(), m_deque.end()); }
-    void shuffle() { std::shuffle(m_deque.begin(), m_deque.end(), VlURNG()); }
-    VlQueue unique() const {
-        VlQueue out;
-        std::unordered_set<T_Value> saw;
-        for (const auto& i : m_deque) {
-            auto it = saw.find(i);
-            if (it == saw.end()) {
-                saw.insert(it, i);
-                out.push_back(i);
-            }
-        }
-        return out;
-    }
-    VlQueue<IData> unique_index() const {
-        VlQueue<IData> out;
-        IData index = 0;
-        std::unordered_set<T_Value> saw;
-        for (const auto& i : m_deque) {
-            auto it = saw.find(i);
-            if (it == saw.end()) {
-                saw.insert(it, i);
-                out.push_back(index);
-            }
-            ++index;
-        }
-        return out;
-    }
-    template <typename Func> VlQueue find(Func with_func) const {
-        VlQueue out;
-        IData index = 0;
-        for (const auto& i : m_deque) {
-            if (with_func(index, i)) out.push_back(i);
-            ++index;
-        }
-        return out;
-    }
-    template <typename Func> VlQueue<IData> find_index(Func with_func) const {
-        VlQueue<IData> out;
-        IData index = 0;
-        for (const auto& i : m_deque) {
-            if (with_func(index, i)) out.push_back(index);
-            ++index;
-        }
-        return out;
-    }
-    template <typename Func> VlQueue find_first(Func with_func) const {
-        // Can't use std::find_if as need index number
-        IData index = 0;
-        for (const auto& i : m_deque) {
-            if (with_func(index, i)) return VlQueue::cons(i);
-            ++index;
-        }
-        return VlQueue{};
-    }
-    template <typename Func> VlQueue<IData> find_first_index(Func with_func) const {
-        IData index = 0;
-        for (const auto& i : m_deque) {
-            if (with_func(index, i)) return VlQueue<IData>::cons(index);
-            ++index;
-        }
-        return VlQueue<IData>{};
-    }
-    template <typename Func> VlQueue find_last(Func with_func) const {
-        IData index = m_deque.size() - 1;
-        for (auto it = m_deque.rbegin(); it != m_deque.rend(); ++it) {
-            if (with_func(index, *it)) return VlQueue::cons(*it);
-            --index;
-        }
-        return VlQueue{};
-    }
-    template <typename Func> VlQueue<IData> find_last_index(Func with_func) const {
-        IData index = m_deque.size() - 1;
-        for (auto it = m_deque.rbegin(); it != m_deque.rend(); ++it) {
-            if (with_func(index, *it)) return VlQueue<IData>::cons(index);
-            --index;
-        }
-        return VlQueue<IData>{};
-    }
-
-    // Reduction operators
-    VlQueue min() const {
-        if (m_deque.empty()) return VlQueue();
-        const auto it = std::min_element(m_deque.begin(), m_deque.end());
-        return VlQueue::cons(*it);
-    }
-    VlQueue max() const {
-        if (m_deque.empty()) return VlQueue();
-        const auto it = std::max_element(m_deque.begin(), m_deque.end());
-        return VlQueue::cons(*it);
-    }
-
-    T_Value r_sum() const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_deque) out += i;
-        return out;
-    }
-    template <typename Func> T_Value r_sum(Func with_func) const {
-        T_Value out(0);  // Type must have assignment operator
-        IData index = 0;
-        for (const auto& i : m_deque) out += with_func(index++, i);
-        return out;
-    }
-    T_Value r_product() const {
-        if (m_deque.empty()) return T_Value(0);
-        auto it = m_deque.begin();
-        T_Value out{*it};
-        ++it;
-        for (; it != m_deque.end(); ++it) out *= *it;
-        return out;
-    }
-    template <typename Func> T_Value r_product(Func with_func) const {
-        if (m_deque.empty()) return T_Value(0);
-        auto it = m_deque.begin();
-        IData index = 0;
-        T_Value out{with_func(index, *it)};
-        ++it;
-        ++index;
-        for (; it != m_deque.end(); ++it) out *= with_func(index++, *it);
-        return out;
-    }
-    T_Value r_and() const {
-        if (m_deque.empty()) return T_Value(0);
-        auto it = m_deque.begin();
-        T_Value out{*it};
-        ++it;
-        for (; it != m_deque.end(); ++it) out &= *it;
-        return out;
-    }
-    template <typename Func> T_Value r_and(Func with_func) const {
-        if (m_deque.empty()) return T_Value(0);
-        auto it = m_deque.begin();
-        IData index = 0;
-        T_Value out{with_func(index, *it)};
-        ++it;
-        ++index;
-        for (; it != m_deque.end(); ++it) out &= with_func(index, *it);
-        return out;
-    }
-    T_Value r_or() const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_deque) out |= i;
-        return out;
-    }
-    template <typename Func> T_Value r_or(Func with_func) const {
-        T_Value out(0);  // Type must have assignment operator
-        IData index = 0;
-        for (const auto& i : m_deque) out |= with_func(index++, i);
-        return out;
-    }
-    T_Value r_xor() const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_deque) out ^= i;
-        return out;
-    }
-    template <typename Func> T_Value r_xor(Func with_func) const {
-        T_Value out(0);  // Type must have assignment operator
-        IData index = 0;
-        for (const auto& i : m_deque) out ^= with_func(index++, i);
-        return out;
-    }
-
-    // Dumping. Verilog: str = $sformatf("%p", assoc)
-    std::string to_string() const {
-        if (m_deque.empty()) return "'{}";  // No trailing space
-        std::string out = "'{";
-        std::string comma;
-        for (const auto& i : m_deque) {
-            out += comma + VL_TO_STRING(i);
-            comma = ", ";
-        }
-        return out + "} ";
-    }
-};
-
-template <class T_Value> std::string VL_TO_STRING(const VlQueue<T_Value>& obj) {
-    return obj.to_string();
-}
-
-//===================================================================
-// Verilog associative array container
-// There are no multithreaded locks on this; the base variable must
-// be protected by other means
-//
-template <class T_Key, class T_Value> class VlAssocArray final {
-private:
-    // TYPES
-    using Map = std::map<T_Key, T_Value>;
-
-public:
-    using const_iterator = typename Map::const_iterator;
-
-private:
-    // MEMBERS
-    Map m_map;  // State of the assoc array
-    T_Value m_defaultValue;  // Default value
-
-public:
-    // CONSTRUCTORS
-    // m_defaultValue isn't defaulted. Caller's constructor must do it.
-    VlAssocArray() = default;
-    ~VlAssocArray() = default;
-    VlAssocArray(const VlAssocArray&) = default;
-    VlAssocArray(VlAssocArray&&) = default;
-    VlAssocArray& operator=(const VlAssocArray&) = default;
-    VlAssocArray& operator=(VlAssocArray&&) = default;
-
-    // METHODS
-    T_Value& atDefault() { return m_defaultValue; }
-    const T_Value& atDefault() const { return m_defaultValue; }
-
-    // Size of array. Verilog: function int size(), or int num()
-    int size() const { return m_map.size(); }
-    // Clear array. Verilog: function void delete([input index])
-    void clear() { m_map.clear(); }
-    void erase(const T_Key& index) { m_map.erase(index); }
-    // Return 0/1 if element exists. Verilog: function int exists(input index)
-    int exists(const T_Key& index) const { return m_map.find(index) != m_map.end(); }
-    // Return first element.  Verilog: function int first(ref index);
-    int first(T_Key& indexr) const {
-        const auto it = m_map.cbegin();
-        if (it == m_map.end()) return 0;
-        indexr = it->first;
-        return 1;
-    }
-    // Return last element.  Verilog: function int last(ref index)
-    int last(T_Key& indexr) const {
-        const auto it = m_map.crbegin();
-        if (it == m_map.rend()) return 0;
-        indexr = it->first;
-        return 1;
-    }
-    // Return next element. Verilog: function int next(ref index)
-    int next(T_Key& indexr) const {
-        auto it = m_map.find(indexr);
-        if (VL_UNLIKELY(it == m_map.end())) return 0;
-        ++it;
-        if (VL_UNLIKELY(it == m_map.end())) return 0;
-        indexr = it->first;
-        return 1;
-    }
-    // Return prev element. Verilog: function int prev(ref index)
-    int prev(T_Key& indexr) const {
-        auto it = m_map.find(indexr);
-        if (VL_UNLIKELY(it == m_map.end())) return 0;
-        if (VL_UNLIKELY(it == m_map.begin())) return 0;
-        --it;
-        indexr = it->first;
-        return 1;
-    }
-    // Setting. Verilog: assoc[index] = v
-    // Can't just overload operator[] or provide a "at" reference to set,
-    // because we need to be able to insert only when the value is set
-    T_Value& at(const T_Key& index) {
-        const auto it = m_map.find(index);
-        if (it == m_map.end()) {
-            std::pair<typename Map::iterator, bool> pit = m_map.emplace(index, m_defaultValue);
-            return pit.first->second;
-        }
-        return it->second;
-    }
-    // Accessing. Verilog: v = assoc[index]
-    const T_Value& at(const T_Key& index) const {
-        const auto it = m_map.find(index);
-        if (it == m_map.end()) {
-            return m_defaultValue;
-        } else {
-            return it->second;
-        }
-    }
-    // Setting as a chained operation
-    VlAssocArray& set(const T_Key& index, const T_Value& value) {
-        at(index) = value;
-        return *this;
-    }
-    VlAssocArray& setDefault(const T_Value& value) {
-        atDefault() = value;
-        return *this;
-    }
-
-    // For save/restore
-    const_iterator begin() const { return m_map.begin(); }
-    const_iterator end() const { return m_map.end(); }
-
-    // Methods
-    VlQueue<T_Value> unique() const {
-        VlQueue<T_Value> out;
-        std::set<T_Value> saw;
-        for (const auto& i : m_map) {
-            auto it = saw.find(i.second);
-            if (it == saw.end()) {
-                saw.insert(it, i.second);
-                out.push_back(i.second);
-            }
-        }
-        return out;
-    }
-    VlQueue<T_Key> unique_index() const {
-        VlQueue<T_Key> out;
-        std::set<T_Key> saw;
-        for (const auto& i : m_map) {
-            auto it = saw.find(i.second);
-            if (it == saw.end()) {
-                saw.insert(it, i.second);
-                out.push_back(i.first);
-            }
-        }
-        return out;
-    }
-    template <typename Func> VlQueue<T_Value> find(Func with_func) const {
-        VlQueue<T_Value> out;
-        for (const auto& i : m_map)
-            if (with_func(i.first, i.second)) out.push_back(i.second);
-        return out;
-    }
-    template <typename Func> VlQueue<T_Key> find_index(Func with_func) const {
-        VlQueue<T_Key> out;
-        for (const auto& i : m_map)
-            if (with_func(i.first, i.second)) out.push_back(i.first);
-        return out;
-    }
-    template <typename Func> VlQueue<T_Value> find_first(Func with_func) const {
-        const auto it
-            = std::find_if(m_map.begin(), m_map.end(), [=](const std::pair<T_Key, T_Value>& i) {
-                  return with_func(i.first, i.second);
-              });
-        if (it == m_map.end()) return VlQueue<T_Value>{};
-        return VlQueue<T_Value>::cons(it->second);
-    }
-    template <typename Func> VlQueue<T_Key> find_first_index(Func with_func) const {
-        const auto it
-            = std::find_if(m_map.begin(), m_map.end(), [=](const std::pair<T_Key, T_Value>& i) {
-                  return with_func(i.first, i.second);
-              });
-        if (it == m_map.end()) return VlQueue<T_Value>{};
-        return VlQueue<T_Key>::cons(it->first);
-    }
-    template <typename Func> VlQueue<T_Value> find_last(Func with_func) const {
-        const auto it
-            = std::find_if(m_map.rbegin(), m_map.rend(), [=](const std::pair<T_Key, T_Value>& i) {
-                  return with_func(i.first, i.second);
-              });
-        if (it == m_map.rend()) return VlQueue<T_Value>{};
-        return VlQueue<T_Value>::cons(it->second);
-    }
-    template <typename Func> VlQueue<T_Key> find_last_index(Func with_func) const {
-        const auto it
-            = std::find_if(m_map.rbegin(), m_map.rend(), [=](const std::pair<T_Key, T_Value>& i) {
-                  return with_func(i.first, i.second);
-              });
-        if (it == m_map.rend()) return VlQueue<T_Value>{};
-        return VlQueue<T_Key>::cons(it->first);
-    }
-
-    // Reduction operators
-    VlQueue<T_Value> min() const {
-        if (m_map.empty()) return VlQueue<T_Value>();
-        const auto it = std::min_element(
-            m_map.begin(), m_map.end(),
-            [](const std::pair<T_Key, T_Value>& a, const std::pair<T_Key, T_Value>& b) {
-                return a.second < b.second;
-            });
-        return VlQueue<T_Value>::cons(it->second);
-    }
-    VlQueue<T_Value> max() const {
-        if (m_map.empty()) return VlQueue<T_Value>();
-        const auto it = std::max_element(
-            m_map.begin(), m_map.end(),
-            [](const std::pair<T_Key, T_Value>& a, const std::pair<T_Key, T_Value>& b) {
-                return a.second < b.second;
-            });
-        return VlQueue<T_Value>::cons(it->second);
-    }
-
-    T_Value r_sum() const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_map) out += i.second;
-        return out;
-    }
-    template <typename Func> T_Value r_sum(Func with_func) const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_map) out += with_func(i.first, i.second);
-        return out;
-    }
-    T_Value r_product() const {
-        if (m_map.empty()) return T_Value(0);
-        auto it = m_map.begin();
-        T_Value out{it->second};
-        ++it;
-        for (; it != m_map.end(); ++it) out *= it->second;
-        return out;
-    }
-    template <typename Func> T_Value r_product(Func with_func) const {
-        if (m_map.empty()) return T_Value(0);
-        auto it = m_map.begin();
-        T_Value out{with_func(it->first, it->second)};
-        ++it;
-        for (; it != m_map.end(); ++it) out *= with_func(it->first, it->second);
-        return out;
-    }
-    T_Value r_and() const {
-        if (m_map.empty()) return T_Value(0);
-        auto it = m_map.begin();
-        T_Value out{it->second};
-        ++it;
-        for (; it != m_map.end(); ++it) out &= it->second;
-        return out;
-    }
-    template <typename Func> T_Value r_and(Func with_func) const {
-        if (m_map.empty()) return T_Value(0);
-        auto it = m_map.begin();
-        T_Value out{with_func(it->first, it->second)};
-        ++it;
-        for (; it != m_map.end(); ++it) out &= with_func(it->first, it->second);
-        return out;
-    }
-    T_Value r_or() const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_map) out |= i.second;
-        return out;
-    }
-    template <typename Func> T_Value r_or(Func with_func) const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_map) out |= with_func(i.first, i.second);
-        return out;
-    }
-    T_Value r_xor() const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_map) out ^= i.second;
-        return out;
-    }
-    template <typename Func> T_Value r_xor(Func with_func) const {
-        T_Value out(0);  // Type must have assignment operator
-        for (const auto& i : m_map) out ^= with_func(i.first, i.second);
-        return out;
-    }
-
-    // Dumping. Verilog: str = $sformatf("%p", assoc)
-    std::string to_string() const {
-        if (m_map.empty()) return "'{}";  // No trailing space
-        std::string out = "'{";
-        std::string comma;
-        for (const auto& i : m_map) {
-            out += comma + VL_TO_STRING(i.first) + ":" + VL_TO_STRING(i.second);
-            comma = ", ";
-        }
-        // Default not printed - maybe random init data
-        return out + "} ";
-    }
-};
-
-template <class T_Key, class T_Value>
-std::string VL_TO_STRING(const VlAssocArray<T_Key, T_Value>& obj) {
-    return obj.to_string();
-}
-
-template <class T_Key, class T_Value>
-void VL_READMEM_N(bool hex, int bits, const std::string& filename,
-                  VlAssocArray<T_Key, T_Value>& obj, QData start, QData end) VL_MT_SAFE {
-    VlReadMem rmem(hex, bits, filename, start, end);
-    if (VL_UNLIKELY(!rmem.isOpen())) return;
-    while (true) {
-        QData addr;
-        std::string data;
-        if (rmem.get(addr /*ref*/, data /*ref*/)) {
-            rmem.setData(&(obj.at(addr)), data);
-        } else {
-            break;
-        }
-    }
-}
-
-template <class T_Key, class T_Value>
-void VL_WRITEMEM_N(bool hex, int bits, const std::string& filename,
-                   const VlAssocArray<T_Key, T_Value>& obj, QData start, QData end) VL_MT_SAFE {
-    VlWriteMem wmem(hex, bits, filename, start, end);
-    if (VL_UNLIKELY(!wmem.isOpen())) return;
-    for (const auto& i : obj) {
-        QData addr = i.first;
-        if (addr >= start && addr <= end) wmem.print(addr, true, &(i.second));
-    }
-}
-
-//===================================================================
-/// Verilog packed array container
-/// For when a standard C++[] array is not sufficient, e.g. an
-/// array under a queue, or methods operating on the array.
-///
-/// This class may get exposed to a Verilated Model's top I/O, if the top
-/// IO has an unpacked array.
-
-template <class T_Value, std::size_t T_Depth> class VlUnpacked final {
-private:
-    // TYPES
-    using Array = std::array<T_Value, T_Depth>;
-
-public:
-    using const_iterator = typename Array::const_iterator;
-
-private:
-    // MEMBERS
-    Array m_array;  // Contents of the packed array
-
-public:
-    // CONSTRUCTORS
-    VlUnpacked() = default;
-    ~VlUnpacked() = default;
-    VlUnpacked(const VlUnpacked&) = default;
-    VlUnpacked(VlUnpacked&&) = default;
-    VlUnpacked& operator=(const VlUnpacked&) = default;
-    VlUnpacked& operator=(VlUnpacked&&) = default;
-
-    // METHODS
-    // Raw access
-    WData* data() { return &m_array[0]; }
-    const WData* data() const { return &m_array[0]; }
-
-    T_Value& operator[](size_t index) { return m_array[index]; };
-    const T_Value& operator[](size_t index) const { return m_array[index]; };
-
-    // Dumping. Verilog: str = $sformatf("%p", assoc)
-    std::string to_string() const {
-        std::string out = "'{";
-        std::string comma;
-        for (int i = 0; i < T_Depth; ++i) {
-            out += comma + VL_TO_STRING(m_array[i]);
-            comma = ", ";
-        }
-        return out + "} ";
-    }
-};
-
-template <class T_Value, std::size_t T_Depth>
-std::string VL_TO_STRING(const VlUnpacked<T_Value, T_Depth>& obj) {
-    return obj.to_string();
-}
-
-//===================================================================
-// Verilog class reference container
-// There are no multithreaded locks on this; the base variable must
-// be protected by other means
-
-#define VlClassRef std::shared_ptr
-
-template <class T>  // T typically of type VlClassRef<x>
-inline T VL_NULL_CHECK(T t, const char* filename, int linenum) {
-    if (VL_UNLIKELY(!t)) Verilated::nullPointerError(filename, linenum);
-    return t;
-}
-
-template <typename T, typename U>
-static inline bool VL_CAST_DYNAMIC(VlClassRef<T> in, VlClassRef<U>& outr) {
-    VlClassRef<U> casted = std::dynamic_pointer_cast<U>(in);
-    if (VL_LIKELY(casted)) {
-        outr = casted;
-        return true;
-    } else {
-        return false;
-    }
-}
-
-//======================================================================
-// Conversion functions
-
-extern std::string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp) VL_MT_SAFE;
-inline std::string VL_CVT_PACK_STR_NQ(QData lhs) VL_PURE {
-    WData lw[VL_WQ_WORDS_E];
-    VL_SET_WQ(lw, lhs);
-    return VL_CVT_PACK_STR_NW(VL_WQ_WORDS_E, lw);
-}
-inline std::string VL_CVT_PACK_STR_NN(const std::string& lhs) VL_PURE { return lhs; }
-inline std::string& VL_CVT_PACK_STR_NN(std::string& lhs) VL_PURE { return lhs; }
-inline std::string VL_CVT_PACK_STR_NI(IData lhs) VL_PURE {
-    WData lw[VL_WQ_WORDS_E];
-    VL_SET_WI(lw, lhs);
-    return VL_CVT_PACK_STR_NW(1, lw);
-}
-inline std::string VL_CONCATN_NNN(const std::string& lhs, const std::string& rhs) VL_PURE {
-    return lhs + rhs;
-}
-inline std::string VL_REPLICATEN_NNQ(int, int, int, const std::string& lhs, IData rep) VL_PURE {
-    std::string out;
-    out.reserve(lhs.length() * rep);
-    for (unsigned times = 0; times < rep; ++times) out += lhs;
-    return out;
-}
-inline std::string VL_REPLICATEN_NNI(int obits, int lbits, int rbits, const std::string& lhs,
-                                     IData rep) VL_PURE {
-    return VL_REPLICATEN_NNQ(obits, lbits, rbits, lhs, rep);
-}
-
-inline IData VL_LEN_IN(const std::string& ld) { return ld.length(); }
-extern std::string VL_TOLOWER_NN(const std::string& ld);
-extern std::string VL_TOUPPER_NN(const std::string& ld);
-
-extern IData VL_FERROR_IN(IData fpi, std::string& outputr) VL_MT_SAFE;
-extern IData VL_FOPEN_NN(const std::string& filename, const std::string& mode) VL_MT_SAFE;
-extern IData VL_FOPEN_MCD_N(const std::string& filename) VL_MT_SAFE;
-extern void VL_READMEM_N(bool hex, int bits, QData depth, int array_lsb,
-                         const std::string& filename, void* memp, QData start,
-                         QData end) VL_MT_SAFE;
-extern void VL_WRITEMEM_N(bool hex, int bits, QData depth, int array_lsb,
-                          const std::string& filename, const void* memp, QData start,
-                          QData end) VL_MT_SAFE;
-extern IData VL_SSCANF_INX(int lbits, const std::string& ld, const char* formatp, ...) VL_MT_SAFE;
-extern void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp,
-                         ...) VL_MT_SAFE;
-extern std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE;
-extern void VL_TIMEFORMAT_IINI(int units, int precision, const std::string& suffix, int width,
-                               VerilatedContext* contextp) VL_MT_SAFE;
-extern IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_MT_SAFE;
-inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, CData& rdr) VL_MT_SAFE {
-    WData rwp[2];  // WData must always be at least 2
-    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
-    if (got) rdr = rwp[0];
-    return got;
-}
-inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, SData& rdr) VL_MT_SAFE {
-    WData rwp[2];  // WData must always be at least 2
-    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
-    if (got) rdr = rwp[0];
-    return got;
-}
-inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, IData& rdr) VL_MT_SAFE {
-    WData rwp[2];
-    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
-    if (got) rdr = rwp[0];
-    return got;
-}
-inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, QData& rdr) VL_MT_SAFE {
-    WData rwp[2];
-    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
-    if (got) rdr = VL_SET_QW(rwp);
-    return got;
-}
-inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, double& rdr) VL_MT_SAFE {
-    WData rwp[2];
-    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
-    if (got) rdr = VL_CVT_D_Q(VL_SET_QW(rwp));
-    return got;
-}
-extern IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE;
-
-//======================================================================
-// Strings
-
-extern std::string VL_PUTC_N(const std::string& lhs, IData rhs, CData ths) VL_PURE;
-extern CData VL_GETC_N(const std::string& lhs, IData rhs) VL_PURE;
-extern std::string VL_SUBSTR_N(const std::string& lhs, IData rhs, IData ths) VL_PURE;
-
-inline IData VL_CMP_NN(const std::string& lhs, const std::string& rhs, bool ignoreCase) VL_PURE {
-    // SystemVerilog does not allow a string variable to contain '\0'.
-    // So C functions such as strcmp() can correctly compare strings.
-    if (ignoreCase) {
-        return VL_STRCASECMP(lhs.c_str(), rhs.c_str());
-    } else {
-        return std::strcmp(lhs.c_str(), rhs.c_str());
-    }
-}
-
-extern IData VL_ATOI_N(const std::string& str, int base) VL_PURE;
-
-extern IData VL_FGETS_NI(std::string& dest, IData fpi);
-
 #endif  // Guard

include/verilated_imp.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -30,13 +30,17 @@
 
 #include "verilatedos.h"
 #include "verilated.h"
-#include "verilated_heavy.h"
 #include "verilated_syms.h"
 
+#include <algorithm>
 #include <deque>
-#include <set>
-#include <vector>
+#include <limits>
+#include <map>
 #include <numeric>
+#include <set>
+#include <string>
+#include <utility>
+#include <vector>
 #ifdef VL_THREADED
 # include <functional>
 # include <queue>
@@ -61,7 +65,7 @@ public:
 
 private:
     // MEMBERS
-    vluint32_t m_mtaskId;  // MTask that did enqueue
+    uint32_t m_mtaskId;  // MTask that did enqueue
     std::function<void()> m_cb;  // Lambda to execute when message received
 public:
     // CONSTRUCTORS
@@ -74,7 +78,7 @@ public:
     VerilatedMsg& operator=(const VerilatedMsg&) = default;
     VerilatedMsg& operator=(VerilatedMsg&&) = default;
     // METHODS
-    vluint32_t mtaskId() const { return m_mtaskId; }
+    uint32_t mtaskId() const { return m_mtaskId; }
     // Execute the lambda function
     void run() const { m_cb(); }
 };
@@ -85,7 +89,7 @@ public:
 class VerilatedEvalMsgQueue final {
     using VerilatedThreadQueue = std::multiset<VerilatedMsg, VerilatedMsg::Cmp>;
 
-    std::atomic<vluint64_t> m_depth;  // Current depth of queue (see comments below)
+    std::atomic<uint64_t> m_depth;  // Current depth of queue (see comments below)
 
     VerilatedMutex m_mutex;  // Mutex protecting queue
     VerilatedThreadQueue m_queue VL_GUARDED_BY(m_mutex);  // Message queue
@@ -104,7 +108,7 @@ public:
     // METHODS
     // Add message to queue (called by producer)
     void post(const VerilatedMsg& msg) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         m_queue.insert(msg);  // Pass by value to copy the message into queue
         ++m_depth;
     }
@@ -124,7 +128,7 @@ public:
             const VerilatedMsg msg = *(it);
             m_queue.erase(it);
             m_mutex.unlock();
-            m_depth--;  // Ok if outside critical section as only this code checks the value
+            --m_depth;  // Ok if outside critical section as only this code checks the value
             {
                 VL_DEBUG_IF(VL_DBG_MSGF("Executing callback from mtaskId=%d\n", msg.mtaskId()););
                 msg.run();
@@ -179,7 +183,7 @@ public:
 
 // FILE* list constructed from a file-descriptor
 class VerilatedFpList final {
-    FILE* m_fp[31];
+    FILE* m_fp[31] = {};
     std::size_t m_sz = 0;
 
 public:
@@ -241,8 +245,8 @@ public:  // But only for verilated*.cpp
     // METHODS - extending into VerilatedContext, call via impp()->
 
     // Random seed handling
-    vluint64_t randSeedDefault64() const VL_MT_SAFE;
-    static vluint32_t randSeedEpoch() VL_MT_SAFE { return s().s_randSeedEpoch; }
+    uint64_t randSeedDefault64() const VL_MT_SAFE;
+    static uint32_t randSeedEpoch() VL_MT_SAFE { return s().s_randSeedEpoch; }
 
     // METHODS - timeformat
     int timeFormatUnits() const VL_MT_SAFE {
@@ -256,11 +260,11 @@ public:  // But only for verilated*.cpp
     int timeFormatWidth() const VL_MT_SAFE { return m_s.m_timeFormatWidth; }
     void timeFormatWidth(int value) VL_MT_SAFE { m_s.m_timeFormatWidth = value; }
     std::string timeFormatSuffix() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) {
-        const VerilatedLockGuard lock(m_timeDumpMutex);
+        const VerilatedLockGuard lock{m_timeDumpMutex};
         return m_timeFormatSuffix;
     }
     void timeFormatSuffix(const std::string& value) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) {
-        const VerilatedLockGuard lock(m_timeDumpMutex);
+        const VerilatedLockGuard lock{m_timeDumpMutex};
         m_timeFormatSuffix = value;
     }
 
@@ -276,19 +280,19 @@ public:  // But only for verilated*.cpp
 public:  // But only for verilated*.cpp
     // METHODS - file IO
     IData fdNewMcd(const char* filenamep) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         if (m_fdFreeMct.empty()) return 0;
-        IData idx = m_fdFreeMct.back();
+        const IData idx = m_fdFreeMct.back();
         m_fdFreeMct.pop_back();
         m_fdps[idx] = std::fopen(filenamep, "w");
         if (VL_UNLIKELY(!m_fdps[idx])) return 0;
         return (1 << idx);
     }
     IData fdNew(const char* filenamep, const char* modep) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        FILE* fp = std::fopen(filenamep, modep);
+        FILE* const fp = std::fopen(filenamep, modep);
         if (VL_UNLIKELY(!fp)) return 0;
         // Bit 31 indicates it's a descriptor not a MCD
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         if (m_fdFree.empty()) {
             // Need to create more space in m_fdps and m_fdFree
             const std::size_t start = std::max<std::size_t>(31UL + 1UL + 3UL, m_fdps.size());
@@ -300,31 +304,31 @@ public:  // But only for verilated*.cpp
                 m_fdFree[i] = id;
             }
         }
-        IData idx = m_fdFree.back();
+        const IData idx = m_fdFree.back();
         m_fdFree.pop_back();
         m_fdps[idx] = fp;
         return (idx | (1UL << 31));  // bit 31 indicates not MCD
     }
     void fdFlush(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         const VerilatedFpList fdlist = fdToFpList(fdi);
         for (const auto& i : fdlist) std::fflush(i);
     }
     IData fdSeek(IData fdi, IData offset, IData origin) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         const VerilatedFpList fdlist = fdToFpList(fdi);
-        if (VL_UNLIKELY(fdlist.size() != 1)) return 0;
+        if (VL_UNLIKELY(fdlist.size() != 1)) return ~0U;  // -1
         return static_cast<IData>(
             std::fseek(*fdlist.begin(), static_cast<long>(offset), static_cast<int>(origin)));
     }
     IData fdTell(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         const VerilatedFpList fdlist = fdToFpList(fdi);
-        if (VL_UNLIKELY(fdlist.size() != 1)) return 0;
+        if (VL_UNLIKELY(fdlist.size() != 1)) return ~0U;  // -1
         return static_cast<IData>(std::ftell(*fdlist.begin()));
     }
     void fdWrite(IData fdi, const std::string& output) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         const VerilatedFpList fdlist = fdToFpList(fdi);
         for (const auto& i : fdlist) {
             if (VL_UNLIKELY(!i)) continue;
@@ -332,10 +336,10 @@ public:  // But only for verilated*.cpp
         }
     }
     void fdClose(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         if (VL_BITISSET_I(fdi, 31)) {
             // Non-MCD case
-            IData idx = VL_MASK_I(31) & fdi;
+            const IData idx = VL_MASK_I(31) & fdi;
             if (VL_UNLIKELY(idx >= m_fdps.size())) return;
             if (VL_UNLIKELY(idx <= 2)) return;  // stdout/stdin/stderr
             if (VL_UNLIKELY(!m_fdps[idx])) return;  // Already free
@@ -356,7 +360,7 @@ public:  // But only for verilated*.cpp
         }
     }
     inline FILE* fdToFp(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) {
-        const VerilatedLockGuard lock(m_fdMutex);
+        const VerilatedLockGuard lock{m_fdMutex};
         const VerilatedFpList fdlist = fdToFpList(fdi);
         if (VL_UNLIKELY(fdlist.size() != 1)) return nullptr;
         return *fdlist.begin();
@@ -391,7 +395,11 @@ protected:
     // METHODS - protected
     void commandArgsAddGuts(int argc, const char** argv);
     void commandArgVl(const std::string& arg);
-    bool commandArgVlValue(const std::string& arg, const std::string& prefix, std::string& valuer);
+    bool commandArgVlString(const std::string& arg, const std::string& prefix,
+                            std::string& valuer);
+    bool commandArgVlUint64(const std::string& arg, const std::string& prefix, uint64_t& valuer,
+                            uint64_t min = std::numeric_limits<uint64_t>::min(),
+                            uint64_t max = std::numeric_limits<uint64_t>::max());
     void commandArgDump() const VL_MT_SAFE_EXCLUDES(m_argMutex);
 };
 
@@ -463,7 +471,7 @@ public:
     // per map overhead * N scopes would take much more space and cache thrashing.
     // As scopep's are pointers, this implicitly handles multiple Context's
     static inline void userInsert(const void* scopep, void* userKey, void* userData) VL_MT_SAFE {
-        const VerilatedLockGuard lock(s().m_userMapMutex);
+        const VerilatedLockGuard lock{s().m_userMapMutex};
         const auto it = s().m_userMap.find(std::make_pair(scopep, userKey));
         if (it != s().m_userMap.end()) {
             it->second = userData;
@@ -472,7 +480,7 @@ public:
         }
     }
     static inline void* userFind(const void* scopep, void* userKey) VL_MT_SAFE {
-        const VerilatedLockGuard lock(s().m_userMapMutex);
+        const VerilatedLockGuard lock{s().m_userMapMutex};
         const auto& it = vlstd::as_const(s().m_userMap).find(std::make_pair(scopep, userKey));
         if (VL_UNLIKELY(it == s().m_userMap.end())) return nullptr;
         return it->second;
@@ -481,8 +489,8 @@ public:
 public:  // But only for verilated.cpp
     // Symbol table destruction cleans up the entries for each scope.
     static void userEraseScope(const VerilatedScope* scopep) VL_MT_SAFE {
-        // Slow ok - called once/scope on destruction, so we simply iterate.
-        const VerilatedLockGuard lock(s().m_userMapMutex);
+        // Slow ok - called once/scope on destruction, so we only iterate.
+        const VerilatedLockGuard lock{s().m_userMapMutex};
         for (auto it = s().m_userMap.begin(); it != s().m_userMap.end();) {
             if (it->first.first == scopep) {
                 s().m_userMap.erase(it++);
@@ -492,7 +500,7 @@ public:  // But only for verilated.cpp
         }
     }
     static void userDump() VL_MT_SAFE {
-        const VerilatedLockGuard lock(s().m_userMapMutex);  // Avoid it changing in middle of dump
+        const VerilatedLockGuard lock{s().m_userMapMutex};  // Avoid it changing in middle of dump
         bool first = true;
         for (const auto& i : s().m_userMap) {
             if (first) {
@@ -508,13 +516,13 @@ public:  // But only for verilated*.cpp
     // METHODS - hierarchy
     static void hierarchyAdd(const VerilatedScope* fromp, const VerilatedScope* top) VL_MT_SAFE {
         // Slow ok - called at construction for VPI accessible elements
-        const VerilatedLockGuard lock(s().m_hierMapMutex);
+        const VerilatedLockGuard lock{s().m_hierMapMutex};
         s().m_hierMap[fromp].push_back(top);
     }
     static void hierarchyRemove(const VerilatedScope* fromp,
                                 const VerilatedScope* top) VL_MT_SAFE {
         // Slow ok - called at destruction for VPI accessible elements
-        const VerilatedLockGuard lock(s().m_hierMapMutex);
+        const VerilatedLockGuard lock{s().m_hierMapMutex};
         VerilatedHierarchyMap& map = s().m_hierMap;
         if (map.find(fromp) == map.end()) return;
         auto& scopes = map[fromp];
@@ -537,7 +545,7 @@ public:  // But only for verilated*.cpp
     // miss at the cost of a multiply, and all lookups move to slowpath.
     static int exportInsert(const char* namep) VL_MT_SAFE {
         // Slow ok - called once/function at creation
-        const VerilatedLockGuard lock(s().m_exportMutex);
+        const VerilatedLockGuard lock{s().m_exportMutex};
         const auto it = s().m_exportMap.find(namep);
         if (it == s().m_exportMap.end()) {
             s().m_exportMap.emplace(namep, s().m_exportNext++);
@@ -547,24 +555,24 @@ public:  // But only for verilated*.cpp
         }
     }
     static int exportFind(const char* namep) VL_MT_SAFE {
-        const VerilatedLockGuard lock(s().m_exportMutex);
+        const VerilatedLockGuard lock{s().m_exportMutex};
         const auto& it = s().m_exportMap.find(namep);
         if (VL_LIKELY(it != s().m_exportMap.end())) return it->second;
-        std::string msg = (std::string("%Error: Testbench C called ") + namep
-                           + " but no such DPI export function name exists in ANY model");
+        const std::string msg = (std::string{"%Error: Testbench C called "} + namep
+                                 + " but no such DPI export function name exists in ANY model");
         VL_FATAL_MT("unknown", 0, "", msg.c_str());
         return -1;
     }
     static const char* exportName(int funcnum) VL_MT_SAFE {
         // Slowpath; find name for given export; errors only so no map to reverse-map it
-        const VerilatedLockGuard lock(s().m_exportMutex);
+        const VerilatedLockGuard lock{s().m_exportMutex};
         for (const auto& i : s().m_exportMap) {
             if (i.second == funcnum) return i.first;
         }
         return "*UNKNOWN*";
     }
     static void exportsDump() VL_MT_SAFE {
-        const VerilatedLockGuard lock(s().m_exportMutex);
+        const VerilatedLockGuard lock{s().m_exportMutex};
         bool first = true;
         for (const auto& i : s().m_exportMap) {
             if (first) {

include/verilated_intrinsics.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_profiler.cpp

@@ -0,0 +1,191 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//=============================================================================
+//
+// Code available from: https://verilator.org
+//
+// Copyright 2012-2022 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//=============================================================================
+///
+/// \file
+/// \brief Verilated run-time profiling implementation code
+///
+//=============================================================================
+
+#include "verilatedos.h"
+#include "verilated_profiler.h"
+
+#if VL_THREADED
+#include "verilated_threads.h"
+#endif
+
+#include <fstream>
+#include <string>
+
+//=============================================================================
+// Globals
+
+// Internal note: Globals may multi-construct, see verilated.cpp top.
+
+VL_THREAD_LOCAL VlExecutionProfiler::ExecutionTrace VlExecutionProfiler::t_trace;
+
+constexpr const char* const VlExecutionRecord::s_ascii[];
+
+//=============================================================================
+// VlPgoProfiler implementation
+
+uint16_t VlExecutionRecord::getcpu() {
+#if defined(__linux)
+    return sched_getcpu();  // TODO: this is a system call. Not exactly cheap.
+#elif defined(__APPLE__) && !defined(__arm64__)
+    uint32_t info[4];
+    __cpuid_count(1, 0, info[0], info[1], info[2], info[3]);
+    // info[1] is EBX, bits 24-31 are APIC ID
+    if ((info[3] & (1 << 9)) == 0) {
+        return -1;  // no APIC on chip
+    } else {
+        return (unsigned)info[1] >> 24;
+    }
+#elif defined(_WIN32)
+    return GetCurrentProcessorNumber();
+#else
+    return 0;
+#endif
+}
+
+//=============================================================================
+// VlExecutionProfiler implementation
+
+template <size_t N> size_t roundUptoMultipleOf(size_t value) {
+    static_assert((N & (N - 1)) == 0, "'N' must be a power of 2");
+    size_t mask = N - 1;
+    return (value + mask) & ~mask;
+}
+
+VlExecutionProfiler::VlExecutionProfiler() {
+    // Setup profiling on main thread
+    setupThread(0);
+}
+
+void VlExecutionProfiler::configure(const VerilatedContext& context) {
+    if (VL_UNLIKELY(m_enabled)) {
+        --m_windowCount;
+        if (VL_UNLIKELY(m_windowCount == context.profExecWindow())) {
+            VL_DEBUG_IF(VL_DBG_MSGF("+ profile start collection\n"););
+            clear();  // Clear the profile after the cache warm-up cycles.
+            m_tickBegin = VL_CPU_TICK();
+        } else if (VL_UNLIKELY(m_windowCount == 0)) {
+            const uint64_t tickEnd = VL_CPU_TICK();
+            VL_DEBUG_IF(VL_DBG_MSGF("+ profile end\n"););
+            const std::string& fileName = context.profExecFilename();
+            dump(fileName.c_str(), tickEnd);
+            m_enabled = false;
+        }
+        return;
+    }
+
+    const uint64_t startReq = context.profExecStart() + 1;  // + 1, so we can start at time 0
+
+    if (VL_UNLIKELY(m_lastStartReq < startReq && VL_TIME_Q() >= context.profExecStart())) {
+        VL_DEBUG_IF(VL_DBG_MSGF("+ profile start warmup\n"););
+        VL_DEBUG_IF(assert(m_windowCount == 0););
+        m_enabled = true;
+        m_windowCount = context.profExecWindow() * 2;
+        m_lastStartReq = startReq;
+    }
+}
+
+void VlExecutionProfiler::setupThread(uint32_t threadId) {
+    // Reserve some space in the thread-local profiling buffer, in order to try to avoid malloc
+    // while profiling.
+    t_trace.reserve(RESERVED_TRACE_CAPACITY);
+    // Register thread-local buffer in list of all buffers
+    {
+        const VerilatedLockGuard lock{m_mutex};
+        bool exists = !m_traceps.emplace(threadId, &t_trace).second;
+        assert(!exists);
+    }
+}
+
+void VlExecutionProfiler::clear() VL_MT_SAFE_EXCLUDES(m_mutex) {
+    const VerilatedLockGuard lock{m_mutex};
+    for (const auto& pair : m_traceps) {
+        ExecutionTrace* const tracep = pair.second;
+        const size_t reserve = roundUptoMultipleOf<RESERVED_TRACE_CAPACITY>(tracep->size());
+        tracep->clear();
+        tracep->reserve(reserve);
+    }
+}
+
+void VlExecutionProfiler::dump(const char* filenamep, uint64_t tickEnd)
+    VL_MT_SAFE_EXCLUDES(m_mutex) {
+    const VerilatedLockGuard lock{m_mutex};
+    VL_DEBUG_IF(VL_DBG_MSGF("+prof+exec writing to '%s'\n", filenamep););
+
+    FILE* const fp = std::fopen(filenamep, "w");
+    if (VL_UNLIKELY(!fp)) { VL_FATAL_MT(filenamep, 0, "", "+prof+exec+file file not writable"); }
+
+    // TODO Perhaps merge with verilated_coverage output format, so can
+    // have a common merging and reporting tool, etc.
+    fprintf(fp, "VLPROFVERSION 2.0 # Verilator execution profile version 2.0\n");
+    fprintf(fp, "VLPROF arg +verilator+prof+exec+start+%" PRIu64 "\n",
+            Verilated::threadContextp()->profExecStart());
+    fprintf(fp, "VLPROF arg +verilator+prof+exec+window+%u\n",
+            Verilated::threadContextp()->profExecWindow());
+    const unsigned threads = static_cast<unsigned>(m_traceps.size());
+    fprintf(fp, "VLPROF stat threads %u\n", threads);
+#ifdef VL_THREADED
+    fprintf(fp, "VLPROF stat yields %" PRIu64 "\n", VlMTaskVertex::yields());
+#endif
+
+    // Copy /proc/cpuinfo into this output so verilator_gantt can be run on
+    // a different machine
+    {
+        const std::unique_ptr<std::ifstream> ifp{new std::ifstream("/proc/cpuinfo")};
+        if (!ifp->fail()) {
+            std::string line;
+            while (std::getline(*ifp, line)) { fprintf(fp, "VLPROFPROC %s\n", line.c_str()); }
+        }
+    }
+
+    for (const auto& pair : m_traceps) {
+        const uint32_t threadId = pair.first;
+        ExecutionTrace* const tracep = pair.second;
+        fprintf(fp, "VLPROFTHREAD %" PRIu32 "\n", threadId);
+
+        for (const VlExecutionRecord& er : *tracep) {
+            const char* const name = VlExecutionRecord::s_ascii[static_cast<uint8_t>(er.m_type)];
+            const uint64_t time = er.m_tick - m_tickBegin;
+            fprintf(fp, "VLPROFEXEC %s %" PRIu64, name, time);
+
+            switch (er.m_type) {
+            case VlExecutionRecord::Type::EVAL_BEGIN:
+            case VlExecutionRecord::Type::EVAL_END:
+            case VlExecutionRecord::Type::EVAL_LOOP_BEGIN:
+            case VlExecutionRecord::Type::EVAL_LOOP_END:
+                // No payload
+                fprintf(fp, "\n");
+                break;
+            case VlExecutionRecord::Type::MTASK_BEGIN: {
+                const auto& payload = er.m_payload.mtaskBegin;
+                fprintf(fp, " id %u predictStart %u cpu %u\n", payload.m_id,
+                        payload.m_predictStart, payload.m_cpu);
+                break;
+            }
+            case VlExecutionRecord::Type::MTASK_END: {
+                const auto& payload = er.m_payload.mtaskEnd;
+                fprintf(fp, " id %u predictCost %u\n", payload.m_id, payload.m_predictCost);
+                break;
+            }
+            default: abort();  // LCOV_EXCL_LINE
+            }
+        }
+    }
+    fprintf(fp, "VLPROF stat ticks %" PRIu64 "\n", tickEnd - m_tickBegin);
+
+    std::fclose(fp);
+}

include/verilated_profiler.h

@@ -0,0 +1,256 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//=============================================================================
+//
+// Code available from: https://verilator.org
+//
+// Copyright 2012-2022 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//=============================================================================
+///
+/// \file
+/// \brief Verilated run-time profiling header
+///
+/// This file is not part of the Verilated public-facing API.
+/// It is only for internal use by Verilated library routines.
+///
+//=============================================================================
+
+#ifndef VERILATOR_VERILATED_PROFILER_H_
+#define VERILATOR_VERILATED_PROFILER_H_
+
+#include "verilatedos.h"
+
+#ifndef VL_PROFILER
+#error "verilated_profiler.h/cpp expects VL_PROFILER (from --prof-{exec, pgo}"
+#endif
+
+#include "verilated.h"
+
+#include <array>
+#include <atomic>
+#include <cassert>
+#include <string>
+#include <type_traits>
+#include <vector>
+
+class VlExecutionProfiler;
+
+//=============================================================================
+// Macros to simplify generated code
+
+#define VL_EXEC_TRACE_ADD_RECORD(vlSymsp) \
+    if (VL_UNLIKELY((vlSymsp)->__Vm_executionProfiler.enabled())) \
+    (vlSymsp)->__Vm_executionProfiler.addRecord()
+
+//=============================================================================
+// Return high-precision counter for profiling, or 0x0 if not available
+VL_ATTR_ALWINLINE
+inline QData VL_CPU_TICK() {
+    uint64_t val;
+    VL_GET_CPU_TICK(val);
+    return val;
+}
+
+//=============================================================================
+// Private class used by VlExecutionProfiler
+
+#define _VL_FOREACH_APPLY(macro, arg) macro(arg, #arg)
+
+// clang-format off
+#define FOREACH_VlExecutionRecord_TYPE(macro) \
+    _VL_FOREACH_APPLY(macro, EVAL_BEGIN) \
+    _VL_FOREACH_APPLY(macro, EVAL_END) \
+    _VL_FOREACH_APPLY(macro, EVAL_LOOP_BEGIN) \
+    _VL_FOREACH_APPLY(macro, EVAL_LOOP_END) \
+    _VL_FOREACH_APPLY(macro, MTASK_BEGIN) \
+    _VL_FOREACH_APPLY(macro, MTASK_END)
+// clang-format on
+
+class VlExecutionRecord final {
+    friend class VlExecutionProfiler;
+
+    // TYPES
+    enum class Type : uint8_t {
+#define VL_FOREACH_MACRO(id, name) id,
+        FOREACH_VlExecutionRecord_TYPE(VL_FOREACH_MACRO)
+#undef VL_FOREACH_MACRO
+    };
+
+    static constexpr const char* const s_ascii[] = {
+#define VL_FOREACH_MACRO(id, name) name,
+        FOREACH_VlExecutionRecord_TYPE(VL_FOREACH_MACRO)
+#undef VL_FOREACH_MACRO
+    };
+
+    union Payload {
+        struct {
+            uint32_t m_id;  // MTask id
+            uint32_t m_predictStart;  // Time scheduler predicted would start
+            uint32_t m_cpu;  // Executing CPU id
+        } mtaskBegin;
+        struct {
+            uint32_t m_id;  // MTask id
+            uint32_t m_predictCost;  // How long scheduler predicted would take
+        } mtaskEnd;
+    };
+
+    // STATE
+    // Layout below allows efficient packing.
+    const uint64_t m_tick = VL_CPU_TICK();  // Tick at construction
+    Payload m_payload;  // The record payload
+    Type m_type;  // The record type
+    static_assert(alignof(uint64_t) >= alignof(Payload), "Padding not allowed");
+    static_assert(alignof(Payload) >= alignof(Type), "Padding not allowed");
+
+    static uint16_t getcpu();  // Return currently executing CPU id
+
+public:
+    // CONSTRUCTOR
+    VlExecutionRecord() = default;
+
+    // METHODS
+    void evalBegin() { m_type = Type::EVAL_BEGIN; }
+    void evalEnd() { m_type = Type::EVAL_END; }
+    void evalLoopBegin() { m_type = Type::EVAL_LOOP_BEGIN; }
+    void evalLoopEnd() { m_type = Type::EVAL_LOOP_END; }
+    void mtaskBegin(uint32_t id, uint32_t predictStart) {
+        m_payload.mtaskBegin.m_id = id;
+        m_payload.mtaskBegin.m_predictStart = predictStart;
+        m_payload.mtaskBegin.m_cpu = getcpu();
+        m_type = Type::MTASK_BEGIN;
+    }
+    void mtaskEnd(uint32_t id, uint32_t predictCost) {
+        m_payload.mtaskEnd.m_id = id;
+        m_payload.mtaskEnd.m_predictCost = predictCost;
+        m_type = Type::MTASK_END;
+    }
+};
+
+static_assert(std::is_trivially_destructible<VlExecutionRecord>::value,
+              "VlExecutionRecord should be trivially destructible for fast buffer clearing");
+
+//=============================================================================
+// VlExecutionProfiler is for collecting profiling data about model execution
+
+class VlExecutionProfiler final {
+    // CONSTANTS
+
+    // In order to try to avoid dynamic memory allocations during the actual profiling phase,
+    // trace buffers are pre-allocated to be able to hold [a multiple] of this many records.
+    static constexpr size_t RESERVED_TRACE_CAPACITY = 4096;
+
+    // TYPES
+
+    // Execution traces are recorded into thread local vectors. We can append records of profiling
+    // events to this vector with very low overhead, and then dump them out later. This prevents
+    // the overhead of printf/malloc/IO from corrupting the profiling data. It's super cheap to
+    // append a VlProfileRec struct on the end of a pre-allocated vector; this is the only cost we
+    // pay in real-time during a profiling cycle. Internal note: Globals may multi-construct, see
+    // verilated.cpp top.
+    using ExecutionTrace = std::vector<VlExecutionRecord>;
+
+    // STATE
+    static VL_THREAD_LOCAL ExecutionTrace t_trace;  // thread-local trace buffers
+    VerilatedMutex m_mutex;
+    // Map from thread id to &t_trace of given thread
+    std::map<uint32_t, ExecutionTrace*> m_traceps VL_GUARDED_BY(m_mutex);
+
+    bool m_enabled = false;  // Is profiling currently enabled
+
+    uint64_t m_tickBegin = 0;  // Sample time (rdtsc() on x86) at beginning of collection
+    uint64_t m_lastStartReq = 0;  // Last requested profiling start (in simulation time)
+    uint32_t m_windowCount = 0;  // Track our position in the cache warmup and profile window
+
+public:
+    // CONSTRUCTOR
+    VlExecutionProfiler();
+
+    // METHODS
+
+    // Is profiling enabled
+    inline bool enabled() const { return m_enabled; }
+    // Append a trace record to the trace buffer of the current thread
+    inline VlExecutionRecord& addRecord() {
+        t_trace.emplace_back();
+        return t_trace.back();
+    }
+    // Configure profiler (called in beginning of 'eval')
+    void configure(const VerilatedContext&);
+    // Setup profiling on a particular thread;
+    void setupThread(uint32_t threadId);
+    // Clear all profiling data
+    void clear() VL_MT_SAFE_EXCLUDES(m_mutex);
+    // Write profiling data into file
+    void dump(const char* filenamep, uint64_t tickEnd) VL_MT_SAFE_EXCLUDES(m_mutex);
+};
+
+//=============================================================================
+// VlPgoProfiler is for collecting profiling data for PGO
+
+template <std::size_t T_Entries> class VlPgoProfiler final {
+    // TYPES
+    struct Record final {
+        const std::string m_name;  // Hashed name of mtask/etc
+        const size_t m_counterNumber = 0;  // Which counter has data
+    };
+
+    // Counters are stored packed, all together to reduce cache effects
+    std::array<uint64_t, T_Entries> m_counters;  // Time spent on this record
+    std::vector<Record> m_records;  // Record information
+
+public:
+    // METHODS
+    VlPgoProfiler() = default;
+    ~VlPgoProfiler() = default;
+    void write(const char* modelp, const std::string& filename) VL_MT_SAFE;
+    void addCounter(size_t counter, const std::string& name) {
+        VL_DEBUG_IF(assert(counter < T_Entries););
+        m_records.emplace_back(Record{name, counter});
+    }
+    void startCounter(size_t counter) {
+        // -= so when we add end time in stopCounter, the net effect is adding the difference,
+        // without needing to hold onto a temporary
+        m_counters[counter] -= VL_CPU_TICK();
+    }
+    void stopCounter(size_t counter) { m_counters[counter] += VL_CPU_TICK(); }
+};
+
+template <std::size_t T_Entries>
+void VlPgoProfiler<T_Entries>::write(const char* modelp, const std::string& filename) VL_MT_SAFE {
+    static VerilatedMutex s_mutex;
+    const VerilatedLockGuard lock{s_mutex};
+
+    // On the first call we create the file.  On later calls we append.
+    // So when we have multiple models in an executable, possibly even
+    // running on different threads, each will have a different symtab so
+    // each will collect is own data correctly.  However when each is
+    // destroid we need to get all the data, not keep overwriting and only
+    // get the last model's data.
+    static bool s_firstCall = true;
+
+    VL_DEBUG_IF(VL_DBG_MSGF("+prof+vlt+file writing to '%s'\n", filename.c_str()););
+
+    FILE* const fp = std::fopen(filename.c_str(), s_firstCall ? "w" : "a");
+    if (VL_UNLIKELY(!fp)) {
+        VL_FATAL_MT(filename.c_str(), 0, "", "+prof+vlt+file file not writable");
+    }
+    s_firstCall = false;
+
+    // TODO Perhaps merge with verilated_coverage output format, so can
+    // have a common merging and reporting tool, etc.
+    fprintf(fp, "// Verilated model profile-guided optimization data dump file\n");
+    fprintf(fp, "`verilator_config\n");
+
+    for (const Record& rec : m_records) {
+        fprintf(fp, "profile_data -model \"%s\" -mtask \"%s\" -cost 64'd%" PRIu64 "\n", modelp,
+                rec.m_name.c_str(), m_counters[rec.m_counterNumber]);
+    }
+
+    std::fclose(fp);
+}
+
+#endif

include/verilated_save.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -63,8 +63,8 @@ static const char* const VLTSAVE_TRAILER_STR = "vltsaved";
 bool VerilatedDeserialize::readDiffers(const void* __restrict datap,
                                        size_t size) VL_MT_UNSAFE_ONE {
     bufferCheck();
-    const vluint8_t* __restrict dp = static_cast<const vluint8_t* __restrict>(datap);
-    vluint8_t miss = 0;
+    const uint8_t* __restrict dp = static_cast<const uint8_t* __restrict>(datap);
+    uint8_t miss = 0;
     while (size--) miss |= (*dp++ ^ *m_cp++);
     return (miss != 0);
 }
@@ -72,9 +72,10 @@ bool VerilatedDeserialize::readDiffers(const void* __restrict datap,
 VerilatedDeserialize& VerilatedDeserialize::readAssert(const void* __restrict datap,
                                                        size_t size) VL_MT_UNSAFE_ONE {
     if (VL_UNLIKELY(readDiffers(datap, size))) {
-        std::string fn = filename();
-        std::string msg = "Can't deserialize save-restore file as was made from different model: "
-                          + filename();
+        const std::string fn = filename();
+        const std::string msg
+            = "Can't deserialize save-restore file as was made from different model: "
+              + filename();
         VL_FATAL_MT(fn.c_str(), 0, "", msg.c_str());
         // Die before we close() as close would infinite loop
     }
@@ -90,10 +91,10 @@ void VerilatedSerialize::header() VL_MT_UNSAFE_ONE {
 void VerilatedDeserialize::header() VL_MT_UNSAFE_ONE {
     VerilatedDeserialize& os = *this;  // So can cut and paste standard >> code below
     if (VL_UNLIKELY(os.readDiffers(VLTSAVE_HEADER_STR, std::strlen(VLTSAVE_HEADER_STR)))) {
-        std::string fn = filename();
-        std::string msg
-            = std::string(
-                  "Can't deserialize; file has wrong header signature, or file not found: ")
+        const std::string fn = filename();
+        const std::string msg
+            = std::
+                  string{"Can't deserialize; file has wrong header signature, or file not found: "}
               + filename();
         VL_FATAL_MT(fn.c_str(), 0, "", msg.c_str());
         // Die before we close() as close would infinite loop
@@ -109,9 +110,10 @@ void VerilatedSerialize::trailer() VL_MT_UNSAFE_ONE {
 void VerilatedDeserialize::trailer() VL_MT_UNSAFE_ONE {
     VerilatedDeserialize& os = *this;  // So can cut and paste standard >> code below
     if (VL_UNLIKELY(os.readDiffers(VLTSAVE_TRAILER_STR, std::strlen(VLTSAVE_TRAILER_STR)))) {
-        std::string fn = filename();
-        std::string msg = std::string("Can't deserialize; file has wrong end-of-file signature: ")
-                          + filename();
+        const std::string fn = filename();
+        const std::string msg
+            = std::string{"Can't deserialize; file has wrong end-of-file signature: "}
+              + filename();
         VL_FATAL_MT(fn.c_str(), 0, "", msg.c_str());
         // Die before we close() as close would infinite loop
     }
@@ -190,19 +192,19 @@ void VerilatedRestore::close() VL_MT_UNSAFE_ONE {
 void VerilatedSave::flush() VL_MT_UNSAFE_ONE {
     m_assertOne.check();
     if (VL_UNLIKELY(!isOpen())) return;
-    vluint8_t* wp = m_bufp;
+    const uint8_t* wp = m_bufp;
     while (true) {
-        ssize_t remaining = (m_cp - wp);
+        const ssize_t remaining = (m_cp - wp);
         if (remaining == 0) break;
         errno = 0;
-        ssize_t got = ::write(m_fd, wp, remaining);
+        const ssize_t got = ::write(m_fd, wp, remaining);
         if (got > 0) {
             wp += got;
         } else if (VL_UNCOVERABLE(got < 0)) {
             if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) {
                 // LCOV_EXCL_START
                 // write failed, presume error (perhaps out of disk space)
-                std::string msg = std::string(__FUNCTION__) + ": " + std::strerror(errno);
+                const std::string msg = std::string{__FUNCTION__} + ": " + std::strerror(errno);
                 VL_FATAL_MT("", 0, "", msg.c_str());
                 close();
                 break;
@@ -217,23 +219,23 @@ void VerilatedRestore::fill() VL_MT_UNSAFE_ONE {
     m_assertOne.check();
     if (VL_UNLIKELY(!isOpen())) return;
     // Move remaining characters down to start of buffer.  (No memcpy, overlaps allowed)
-    vluint8_t* rp = m_bufp;
-    for (vluint8_t* sp = m_cp; sp < m_endp; *rp++ = *sp++) {}  // Overlaps
+    uint8_t* rp = m_bufp;
+    for (uint8_t* sp = m_cp; sp < m_endp; *rp++ = *sp++) {}  // Overlaps
     m_endp = m_bufp + (m_endp - m_cp);
     m_cp = m_bufp;  // Reset buffer
     // Read into buffer starting at m_endp
     while (true) {
-        ssize_t remaining = (m_bufp + bufferSize() - m_endp);
+        const ssize_t remaining = (m_bufp + bufferSize() - m_endp);
         if (remaining == 0) break;
         errno = 0;
-        ssize_t got = ::read(m_fd, m_endp, remaining);
+        const ssize_t got = ::read(m_fd, m_endp, remaining);
         if (got > 0) {
             m_endp += got;
         } else if (VL_UNCOVERABLE(got < 0)) {
             if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) {
                 // LCOV_EXCL_START
                 // write failed, presume error (perhaps out of disk space)
-                std::string msg = std::string(__FUNCTION__) + ": " + std::strerror(errno);
+                const std::string msg = std::string{__FUNCTION__} + ": " + std::strerror(errno);
                 VL_FATAL_MT("", 0, "", msg.c_str());
                 close();
                 break;

include/verilated_save.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2000-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2000-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -23,7 +23,7 @@
 #define VERILATOR_VERILATED_SAVE_C_H_
 
 #include "verilatedos.h"
-#include "verilated_heavy.h"
+#include "verilated.h"
 
 #include <string>
 
@@ -40,8 +40,8 @@ class VerilatedSerialize VL_NOT_FINAL {
 protected:
     // MEMBERS
     // For speed, keep m_cp as the first member of this structure
-    vluint8_t* m_cp;  // Current pointer into m_bufp buffer
-    vluint8_t* m_bufp;  // Output buffer
+    uint8_t* m_cp;  // Current pointer into m_bufp buffer
+    uint8_t* m_bufp;  // Output buffer
     bool m_isOpen = false;  // True indicates open file/stream
     std::string m_filename;  // Filename, for error messages
     VerilatedAssertOneThread m_assertOne;  // Assert only called from single thread
@@ -58,7 +58,7 @@ protected:
 public:
     /// Construct
     VerilatedSerialize() {
-        m_bufp = new vluint8_t[bufferSize()];
+        m_bufp = new uint8_t[bufferSize()];
         m_cp = m_bufp;
     }
     /// Flish, close, and destruct
@@ -77,12 +77,12 @@ public:
     virtual void flush() VL_MT_UNSAFE_ONE {}
     /// Write data to stream
     VerilatedSerialize& write(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE {
-        const vluint8_t* __restrict dp = (const vluint8_t* __restrict)datap;
+        const uint8_t* __restrict dp = (const uint8_t* __restrict)datap;
         while (size) {
             bufferCheck();
             size_t blk = size;
             if (blk > bufferInsertSize()) blk = bufferInsertSize();
-            const vluint8_t* __restrict maxp = dp + blk;
+            const uint8_t* __restrict maxp = dp + blk;
             for (; dp < maxp; *m_cp++ = *dp++) {}
             size -= blk;
         }
@@ -111,9 +111,9 @@ class VerilatedDeserialize VL_NOT_FINAL {
 protected:
     // MEMBERS
     // For speed, keep m_cp as the first member of this structure
-    vluint8_t* m_cp;  // Current pointer into m_bufp buffer
-    vluint8_t* m_bufp;  // Output buffer
-    vluint8_t* m_endp = nullptr;  // Last valid byte in m_bufp buffer
+    uint8_t* m_cp;  // Current pointer into m_bufp buffer
+    uint8_t* m_bufp;  // Output buffer
+    uint8_t* m_endp = nullptr;  // Last valid byte in m_bufp buffer
     bool m_isOpen = false;  // True indicates open file/stream
     std::string m_filename;  // Filename, for error messages
     VerilatedAssertOneThread m_assertOne;  // Assert only called from single thread
@@ -131,7 +131,7 @@ protected:
 public:
     /// Construct
     VerilatedDeserialize() {
-        m_bufp = new vluint8_t[bufferSize()];
+        m_bufp = new uint8_t[bufferSize()];
         m_cp = m_bufp;
     }
     /// Destruct
@@ -150,12 +150,12 @@ public:
     virtual void flush() VL_MT_UNSAFE_ONE {}
     /// Read data from stream
     VerilatedDeserialize& read(void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE {
-        vluint8_t* __restrict dp = static_cast<vluint8_t* __restrict>(datap);
+        uint8_t* __restrict dp = static_cast<uint8_t* __restrict>(datap);
         while (size) {
             bufferCheck();
             size_t blk = size;
             if (blk > bufferInsertSize()) blk = bufferInsertSize();
-            const vluint8_t* __restrict maxp = dp + blk;
+            const uint8_t* __restrict maxp = dp + blk;
             for (; dp < maxp; *dp++ = *m_cp++) {}
             size -= blk;
         }
@@ -165,7 +165,7 @@ public:
     // Internal use:
     // Read a datum and compare with expected value
     VerilatedDeserialize& readAssert(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE;
-    VerilatedDeserialize& readAssert(vluint64_t data) VL_MT_UNSAFE_ONE {
+    VerilatedDeserialize& readAssert(uint64_t data) VL_MT_UNSAFE_ONE {
         return readAssert(&data, sizeof(data));
     }
 
@@ -236,55 +236,55 @@ public:
 
 //=============================================================================
 
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint64_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint64_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
-inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint64_t& rhs) {
+inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint64_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint32_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint32_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
-inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint32_t& rhs) {
+inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint32_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint16_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint16_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
-inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint16_t& rhs) {
+inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint16_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint8_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint8_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
-inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint8_t& rhs) {
+inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint8_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, bool& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const bool& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, bool& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, double& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const double& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, double& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize& operator<<(VerilatedSerialize& os, float& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const float& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, float& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
 inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const std::string& rhs) {
-    vluint32_t len = rhs.length();
+    const uint32_t len = rhs.length();
     os << len;
     return os.write(rhs.data(), len);
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, std::string& rhs) {
-    vluint32_t len = 0;
+    uint32_t len = 0;
     os >> len;
     rhs.resize(len);
     return os.read((void*)rhs.data(), len);
@@ -295,11 +295,11 @@ VerilatedDeserialize& operator>>(VerilatedDeserialize& os, VerilatedContext* rhs
 template <class T_Key, class T_Value>
 VerilatedSerialize& operator<<(VerilatedSerialize& os, VlAssocArray<T_Key, T_Value>& rhs) {
     os << rhs.atDefault();
-    vluint32_t len = rhs.size();
+    const uint32_t len = rhs.size();
     os << len;
     for (const auto& i : rhs) {
-        T_Key index = i.first;  // Copy to get around const_iterator
-        T_Value value = i.second;
+        const T_Key index = i.first;  // Copy to get around const_iterator
+        const T_Value value = i.second;
         os << index << value;
     }
     return os;
@@ -307,10 +307,10 @@ VerilatedSerialize& operator<<(VerilatedSerialize& os, VlAssocArray<T_Key, T_Val
 template <class T_Key, class T_Value>
 VerilatedDeserialize& operator>>(VerilatedDeserialize& os, VlAssocArray<T_Key, T_Value>& rhs) {
     os >> rhs.atDefault();
-    vluint32_t len = 0;
+    uint32_t len = 0;
     os >> len;
     rhs.clear();
-    for (vluint32_t i = 0; i < len; ++i) {
+    for (uint32_t i = 0; i < len; ++i) {
         T_Key index;
         T_Value value;
         os >> index;

include/verilated_sc.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -39,10 +39,10 @@
 // This class is thread safe (though most of SystemC is not).
 class VlScBvExposer final : public sc_bv_base {
 public:
-    static const vluint32_t* sp_datap(const sc_bv_base& base) VL_MT_SAFE {
+    static const uint32_t* sp_datap(const sc_bv_base& base) VL_MT_SAFE {
         return static_cast<const VlScBvExposer*>(&base)->sp_datatp();
     }
-    const vluint32_t* sp_datatp() const { return reinterpret_cast<vluint32_t*>(m_data); }
+    const uint32_t* sp_datatp() const { return reinterpret_cast<uint32_t*>(m_data); }
     // Above reads this protected element in sc_bv_base:
     //   sc_digit* m_data; // data array
 };

include/verilated_sym_props.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -69,9 +69,9 @@ public:
 
 class VerilatedVarProps VL_NOT_FINAL {
     // TYPES
-    static constexpr vluint32_t MAGIC = 0xddc4f829UL;
+    static constexpr uint32_t MAGIC = 0xddc4f829UL;
     // MEMBERS
-    const vluint32_t m_magic;  // Magic number
+    const uint32_t m_magic;  // Magic number
     const VerilatedVarType m_vltype;  // Data type
     const VerilatedVarFlags m_vlflags;  // Direction
     const int m_pdims;  // Packed dimensions, 0 = none
@@ -142,7 +142,7 @@ public:
     VerilatedVarFlags vldir() const {
         return static_cast<VerilatedVarFlags>(static_cast<int>(m_vlflags) & VLVF_MASK_DIR);
     }
-    vluint32_t entSize() const;
+    uint32_t entSize() const;
     bool isPublicRW() const { return ((m_vlflags & VLVF_PUB_RW) != 0); }
     // DPI compatible C standard layout
     bool isDpiCLayout() const { return ((m_vlflags & VLVF_DPI_CLAY) != 0); }
@@ -152,30 +152,34 @@ public:
     const VerilatedRange& unpacked() const { return m_unpacked[0]; }
     // DPI accessors
     int left(int dim) const {
-        return dim == 0 ? m_packed.left()
-                        : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].left() : 0;
+        return dim == 0                                ? m_packed.left()
+               : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].left()
+                                                       : 0;
     }
     int right(int dim) const {
-        return dim == 0 ? m_packed.right()
-                        : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].right() : 0;
+        return dim == 0                                ? m_packed.right()
+               : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].right()
+                                                       : 0;
     }
     int low(int dim) const {
-        return dim == 0 ? m_packed.low()
-                        : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].low() : 0;
+        return dim == 0                                ? m_packed.low()
+               : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].low()
+                                                       : 0;
     }
     int high(int dim) const {
-        return dim == 0 ? m_packed.high()
-                        : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].high() : 0;
+        return dim == 0                                ? m_packed.high()
+               : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].high()
+                                                       : 0;
     }
     int increment(int dim) const {
-        return dim == 0
-                   ? m_packed.increment()
-                   : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].increment() : 0;
+        return dim == 0                                ? m_packed.increment()
+               : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].increment()
+                                                       : 0;
     }
     int elements(int dim) const {
-        return dim == 0
-                   ? m_packed.elements()
-                   : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].elements() : 0;
+        return dim == 0                                ? m_packed.elements()
+               : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].elements()
+                                                       : 0;
     }
     // Total size in bytes (note DPI limited to 4GB)
     size_t totalSize() const;
@@ -188,8 +192,8 @@ public:
 
 class VerilatedDpiOpenVar final {
     // MEMBERS
-    const VerilatedVarProps* m_propsp;  // Variable properties
-    void* m_datap;  // Location of data (local to thread always, so safe)
+    const VerilatedVarProps* const m_propsp;  // Variable properties
+    void* const m_datap;  // Location of data (local to thread always, so safe)
 public:
     // CONSTRUCTORS
     VerilatedDpiOpenVar(const VerilatedVarProps* propsp, void* datap)
@@ -226,10 +230,10 @@ public:
 
 class VerilatedVar final : public VerilatedVarProps {
     // MEMBERS
-    void* m_datap;  // Location of data
-    const char* m_namep;  // Name - slowpath
+    void* const m_datap;  // Location of data
+    const char* const m_namep;  // Name - slowpath
 protected:
-    bool m_isParam;
+    const bool m_isParam;
     friend class VerilatedScope;
     // CONSTRUCTORS
     VerilatedVar(const char* namep, void* datap, VerilatedVarType vltype,