Tests: Add difftree test.

test_regress/driver.pl

@@ -2179,6 +2179,8 @@ sub files_identical {
                     && !/^dot [^\n]+\n/
                     && !/^In file: .*\/sc_.*:\d+/
                     && !/^libgcov.*/
+                    && !/--- \/tmp\//  # t_difftree.pl
+                    && !/\+\+\+ \/tmp\//  # t_difftree.pl
             } @l1;
             @l1 = map {
                 s/(Internal Error: [^\n]+\.cpp):[0-9]+:/$1:#:/;

test_regress/t/t_difftree.a.tree

@@ -0,0 +1,11 @@
+Verilator Tree Dump (format 0x3900) from <e0> to <e663>
+     NETLIST 0x555556bb6000 <e1#> {a0aa}  $root [1ps/1ps]
+    1: MODULE 0x555556bc0120 <e661#> {d19ai}  t  L2 [1ps]
+    1:2: PORT 0x555556bc60d0 <e8#> {d21ae}  clk
+    1:2: VAR 0x555556bbe180 <e572#> {d23ak} @dt=0@  clk INPUT PORT
+    1:2:1: BASICDTYPE 0x555556bc61a0 <e12#> {d23ak} @dt=this@(nw0)  LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT
+    3: TYPETABLE 0x555556bbc000 <e2#> {a0aa}
+                   logic  -> BASICDTYPE 0x555556c71a00 <e426#> {d55ap} @dt=this@(G/nw1)  logic [GENERIC] kwd=logic
+    3: CONSTPOOL 0x555556bbe000 <e6#> {a0aa}
+    3:1: MODULE 0x555556bc0000 <e4#> {a0aa}  @CONST-POOL@  L0 [NONE]
+    3:1:2: SCOPE 0x555556bb60f0 <e5#> {a0aa}  @CONST-POOL@ [abovep=0] [cellp=0] [modp=0x555556bc0000]

test_regress/t/t_difftree.b.tree

@@ -0,0 +1,11 @@
+Verilator Tree Dump (format 0x3900) from <e0> to <e663>
+     NETLIST 0x55d6994da000 <e1#> {a0aa}  $root [1ps/1ps]
+    1: MODULE 0x55d6994e4120 <e661#> {d19ai}  t  L2 [1ps]
+    1:2: PORT 0x55d6994ea0d0 <e8#> {d21ae}  clk
+    1:2: VAR 0x55d6994e2180 <e572#> {d23ak} @dt=0@  clkmod INPUT PORT
+    1:2:1: BASICDTYPE 0x55d6994ea1a0 <e12#> {d23ak} @dt=this@(nw0)  LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT
+    3: TYPETABLE 0x55d6994e0000 <e2#> {a0aa}
+                   logic  -> BASICDTYPE 0x55d699595a00 <e426#> {d55ap} @dt=this@(G/nw1)  logic [GENERIC] kwd=logic
+    3: CONSTPOOL 0x55d6994e2000 <e6#> {a0aa}
+    3:1: MODULE 0x55d6994e4000 <e4#> {a0aa}  @CONST-POOL@  L0 [NONE]
+    3:1:2: SCOPE 0x55d6994da0f0 <e5#> {a0aa}  @CONST-POOL@ [abovep=0] [cellp=0] [modp=0x55d6994e4000]

test_regress/t/t_difftree.out

@@ -0,0 +1,8 @@
+@@ -2,7 +2,7 @@
+      NETLIST 0x <e> {a0aa}  $root [1ps/1ps]
+     1: MODULE 0x <e> {d19ai}  t  L2 [1ps]
+     1:2: PORT 0x <e> {d21ae}  clk
++    1:2: VAR 0x <e> {d23ak} @dt=0@  clkmod INPUT PORT
+     1:2:1: BASICDTYPE 0x <e> {d23ak} @dt=this@(nw0)  LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT
+     3: TYPETABLE 0x <e> {a0aa}
+                    logic  -> BASICDTYPE 0x <e> {d55ap} @dt=this@(G/nw1)  logic [GENERIC] kwd=logic

test_regress/t/t_difftree.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt_all => 1);
+
+run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_difftree"
+            ." $Self->{t_dir}/t_difftree.a.tree $Self->{t_dir}/t_difftree.b.tree > diff.log"],
+    check_finished => 0);
+
+files_identical("$Self->{obj_dir}/diff.log", $Self->{golden_filename}, 'logfile');
+
+ok(1);
+
+1;