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Add XML ccall, constpool, initarray, and if/while begins (#3080) 

* EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity
* EmitXml: added signed="true" to signed basicdtypes
This commit is contained in:
Steven Hugg 2021-07-24 20:06:06 -05:00 committed by GitHub
parent 43ecaec9a0
commit 18b0f6387d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 1761 additions and 80 deletions
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1
docs/CONTRIBUTORS
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@ -83,6 +83,7 @@ Sebastien Van Cauwenberghe
Sergi Granell
Stefan Wallentowitz
Stephen Henry
Steven Hugg
Tim Snyder
Tobias Rosenkranz
Tobias Wölfel

67
src/V3EmitXml.cpp
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@ -112,12 +112,67 @@ class EmitXmlFileVisitor final : public AstNVisitor {
putsQuoted(nodep->origName());
outputChildrenEnd(nodep, "instance");
}
virtual void visit(AstNodeIf* nodep) override {
outputTag(nodep, "if");
puts(">\n");
iterateAndNextNull(nodep->op1p());
puts("<begin>\n");
iterateAndNextNull(nodep->op2p());
puts("</begin>\n");
if (nodep->op3p()) {
puts("<begin>\n");
iterateAndNextNull(nodep->op3p());
puts("</begin>\n");
}
puts("</if>\n");
}
virtual void visit(AstWhile* nodep) override {
outputTag(nodep, "while");
puts(">\n");
puts("<begin>\n");
iterateAndNextNull(nodep->op1p());
puts("</begin>\n");
if (nodep->op2p()) {
puts("<begin>\n");
iterateAndNextNull(nodep->op2p());
puts("</begin>\n");
}
if (nodep->op3p()) {
puts("<begin>\n");
iterateAndNextNull(nodep->op3p());
puts("</begin>\n");
}
if (nodep->op4p()) {
puts("<begin>\n");
iterateAndNextNull(nodep->op4p());
puts("</begin>\n");
}
puts("</while>\n");
}
virtual void visit(AstNetlist* nodep) override {
puts("<netlist>\n");
iterateChildren(nodep);
puts("</netlist>\n");
}
virtual void visit(AstConstPool*) override {}
virtual void visit(AstConstPool* nodep) override {
if (!v3Global.opt.xmlOnly()) {
puts("<constpool>\n");
iterateChildren(nodep);
puts("</constpool>\n");
}
}
virtual void visit(AstInitArray* nodep) override {
puts("<initarray>\n");
const AstInitArray::KeyItemMap& map = nodep->map();
for (AstInitArray::KeyItemMap::const_iterator it = map.begin(); it != map.end(); ++it) {
puts("<inititem index=\"");
puts(cvtToStr(it->first));
puts("\">\n");
iterateChildren(it->second);
puts("</inititem>\n");
}
puts("</initarray>\n");
}
virtual void visit(AstNodeModule* nodep) override {
outputTag(nodep, "");
puts(" origName=");
@ -195,6 +250,12 @@ class EmitXmlFileVisitor final : public AstNVisitor {
putsQuoted(nodep->dotted());
outputChildrenEnd(nodep, "");
}
virtual void visit(AstNodeCCall* nodep) override {
outputTag(nodep, "");
puts(" func=");
putsQuoted(nodep->funcp()->name());
outputChildrenEnd(nodep, "");
}
// Data types
virtual void visit(AstBasicDType* nodep) override {
@ -203,6 +264,9 @@ class EmitXmlFileVisitor final : public AstNVisitor {
puts(" left=\"" + cvtToStr(nodep->left()) + "\"");
puts(" right=\"" + cvtToStr(nodep->right()) + "\"");
}
if (nodep->isSigned()) {
puts(" signed=\"true\"");
}
puts("/>\n");
}
virtual void visit(AstIfaceRefDType* nodep) override {
@ -319,6 +383,7 @@ private:
// VISITORS
virtual void visit(AstConstPool*) override {}
virtual void visit(AstNodeModule* nodep) override {
if (nodep->level() >= 0
&& nodep->level() <= 2) { // ==2 because we don't add wrapper when in XML mode

1
test_regress/t/t_dist_error_format.pl
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@ -40,6 +40,7 @@ sub formats {
++$lineno;
$line =~ s/(\$display|\$write).*\".*%(Error|Warning)//;
if ($line =~ /(Error|Warning)/
&& $line !~ /^\s*<sformatf / # skip XML tag
&& $line !~ /Error-internal-contents-bad/) {
# These formats are documented in bin/verilator
# Error with fileline

6
test_regress/t/t_var_port_xml.out
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@ -121,9 +121,9 @@
</range>
</unpackarraydtype>
<basicdtype fl="d38" loc="d,38,17,38,18" id="4" name="logic" left="5" right="0"/>
<basicdtype fl="d34" loc="d,34,27,34,28" id="3" name="logic" left="5" right="0"/>
<basicdtype fl="d18" loc="d,18,19,18,26" id="1" name="integer" left="31" right="0"/>
<basicdtype fl="d40" loc="d,40,37,40,38" id="7" name="logic" left="31" right="0"/>
<basicdtype fl="d34" loc="d,34,27,34,28" id="3" name="logic" left="5" right="0" signed="true"/>
<basicdtype fl="d18" loc="d,18,19,18,26" id="1" name="integer" left="31" right="0" signed="true"/>
<basicdtype fl="d40" loc="d,40,37,40,38" id="7" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

3
test_regress/t/t_var_xref_gen.pl
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@ -8,11 +8,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
scenarios(vlt => 1);
compile(
verilator_flags2 => ["--debug-check"],
);
ok(1);
1;

1560
test_regress/t/t_xml_debugcheck.out Normal file
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File diff suppressed because it is too large Load Diff

37
test_regress/t/t_xml_debugcheck.pl Executable file
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@ -0,0 +1,37 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2012 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml";
top_filename("t/t_enum_type_methods.v");
compile(
verilator_flags2 => ['--debug-check', '--flatten'],
verilator_make_gmake => 0,
make_top_shell => 0,
make_main => 0,
);
files_identical("$out_filename", $Self->{golden_filename});
# make sure that certain tags are present in --debug-check
# that would not be present in --xml-only
file_grep("$out_filename", qr/<constpool /x);
file_grep("$out_filename", qr/<inititem /x);
file_grep("$out_filename", qr/<if /x);
file_grep("$out_filename", qr/<while /x);
file_grep("$out_filename", qr/<begin>/x); # for <if> and <while>
file_grep("$out_filename", qr/ signed=/x); # for <basicdtype>
file_grep("$out_filename", qr/ func=/x); # for <ccall>
ok(1);
1;

2
test_regress/t/t_xml_first.out
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@ -79,7 +79,7 @@
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d48" loc="d,48,10,48,13" id="1" name="logic"/>
<basicdtype fl="d14" loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype fl="d19" loc="d,19,18,19,19" id="3" name="logic" left="31" right="0"/>
<basicdtype fl="d19" loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

2
test_regress/t/t_xml_flat.out
View File

@ -108,7 +108,7 @@
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d48" loc="d,48,10,48,13" id="1" name="logic"/>
<basicdtype fl="d14" loc="d,14,10,14,11" id="2" name="logic" left="3" right="0"/>
<basicdtype fl="d19" loc="d,19,18,19,19" id="3" name="logic" left="31" right="0"/>
<basicdtype fl="d19" loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>

160
test_regress/t/t_xml_flat_vlvbound.out
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@ -68,43 +68,51 @@
<varref fl="d18" loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</assign>
<while fl="d18" loc="d,18,5,18,8">
<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
<const fl="d18" loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</gts>
<assign fl="d19" loc="d,19,14,19,15" dtype_id="6">
<eq fl="d19" loc="d,19,31,19,33" dtype_id="6">
<const fl="d19" loc="d,19,34,19,39" name="2&apos;h0" dtype_id="7"/>
<sel fl="d19" loc="d,19,20,19,21" dtype_id="7">
<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<sel fl="d19" loc="d,19,22,19,23" dtype_id="8">
<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
<const fl="d19" loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</muls>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h4" dtype_id="9"/>
<begin>
</begin>
<begin>
<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
<const fl="d18" loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</gts>
</begin>
<begin>
<assign fl="d19" loc="d,19,14,19,15" dtype_id="6">
<eq fl="d19" loc="d,19,31,19,33" dtype_id="6">
<const fl="d19" loc="d,19,34,19,39" name="2&apos;h0" dtype_id="7"/>
<sel fl="d19" loc="d,19,20,19,21" dtype_id="7">
<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<sel fl="d19" loc="d,19,22,19,23" dtype_id="8">
<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
<const fl="d19" loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</muls>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h4" dtype_id="9"/>
</sel>
<const fl="d19" loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
</sel>
<const fl="d19" loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
</eq>
<sel fl="d19" loc="d,19,10,19,11" dtype_id="6">
<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<sel fl="d19" loc="d,19,11,19,12" dtype_id="10">
<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h3" dtype_id="9"/>
</sel>
<const fl="d19" loc="d,19,10,19,11" name="32&apos;h1" dtype_id="9"/>
</sel>
</eq>
<sel fl="d19" loc="d,19,10,19,11" dtype_id="6">
<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<sel fl="d19" loc="d,19,11,19,12" dtype_id="10">
<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h3" dtype_id="9"/>
</sel>
<const fl="d19" loc="d,19,10,19,11" name="32&apos;h1" dtype_id="9"/>
</sel>
</assign>
<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
<add fl="d18" loc="d,18,24,18,26" dtype_id="9">
<const fl="d18" loc="d,18,24,18,26" name="32&apos;h1" dtype_id="9"/>
</assign>
</begin>
<begin>
<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
<add fl="d18" loc="d,18,24,18,26" dtype_id="9">
<const fl="d18" loc="d,18,24,18,26" name="32&apos;h1" dtype_id="9"/>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</add>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</add>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
</assign>
</assign>
</begin>
</while>
<assign fl="d21" loc="d,21,5,21,11" dtype_id="2">
<varref fl="d21" loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
@ -126,43 +134,51 @@
<varref fl="d18" loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</assign>
<while fl="d18" loc="d,18,5,18,8">
<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
<const fl="d18" loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</gts>
<assign fl="d19" loc="d,19,14,19,15" dtype_id="6">
<eq fl="d19" loc="d,19,31,19,33" dtype_id="6">
<const fl="d19" loc="d,19,34,19,39" name="2&apos;h0" dtype_id="7"/>
<sel fl="d19" loc="d,19,20,19,21" dtype_id="7">
<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<sel fl="d19" loc="d,19,22,19,23" dtype_id="8">
<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
<const fl="d19" loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</muls>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h4" dtype_id="9"/>
<begin>
</begin>
<begin>
<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
<const fl="d18" loc="d,18,20,18,21" name="32&apos;sh7" dtype_id="4"/>
<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</gts>
</begin>
<begin>
<assign fl="d19" loc="d,19,14,19,15" dtype_id="6">
<eq fl="d19" loc="d,19,31,19,33" dtype_id="6">
<const fl="d19" loc="d,19,34,19,39" name="2&apos;h0" dtype_id="7"/>
<sel fl="d19" loc="d,19,20,19,21" dtype_id="7">
<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
<sel fl="d19" loc="d,19,22,19,23" dtype_id="8">
<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
<const fl="d19" loc="d,19,23,19,24" name="32&apos;sh2" dtype_id="4"/>
<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</muls>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,22,19,23" name="32&apos;h4" dtype_id="9"/>
</sel>
<const fl="d19" loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
</sel>
<const fl="d19" loc="d,19,28,19,29" name="32&apos;sh2" dtype_id="4"/>
</eq>
<sel fl="d19" loc="d,19,10,19,11" dtype_id="6">
<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<sel fl="d19" loc="d,19,11,19,12" dtype_id="10">
<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h3" dtype_id="9"/>
</sel>
<const fl="d19" loc="d,19,10,19,11" name="32&apos;h1" dtype_id="9"/>
</sel>
</eq>
<sel fl="d19" loc="d,19,10,19,11" dtype_id="6">
<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<sel fl="d19" loc="d,19,11,19,12" dtype_id="10">
<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h0" dtype_id="9"/>
<const fl="d19" loc="d,19,11,19,12" name="32&apos;h3" dtype_id="9"/>
</sel>
<const fl="d19" loc="d,19,10,19,11" name="32&apos;h1" dtype_id="9"/>
</sel>
</assign>
<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
<add fl="d18" loc="d,18,24,18,26" dtype_id="9">
<const fl="d18" loc="d,18,24,18,26" name="32&apos;h1" dtype_id="9"/>
</assign>
</begin>
<begin>
<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
<add fl="d18" loc="d,18,24,18,26" dtype_id="9">
<const fl="d18" loc="d,18,24,18,26" name="32&apos;h1" dtype_id="9"/>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</add>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</add>
<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
</assign>
</assign>
</begin>
</while>
<assign fl="d21" loc="d,21,5,21,11" dtype_id="2">
<varref fl="d21" loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
@ -189,11 +205,11 @@
<basicdtype fl="d19" loc="d,19,34,19,39" id="7" name="logic" left="1" right="0"/>
<basicdtype fl="d9" loc="d,9,11,9,16" id="1" name="logic" left="15" right="0"/>
<basicdtype fl="d11" loc="d,11,12,11,17" id="2" name="logic" left="6" right="0"/>
<basicdtype fl="d17" loc="d,17,5,17,12" id="3" name="integer" left="31" right="0"/>
<basicdtype fl="d19" loc="d,19,10,19,11" id="10" name="logic" left="2" right="0"/>
<basicdtype fl="d17" loc="d,17,5,17,12" id="3" name="integer" left="31" right="0" signed="true"/>
<basicdtype fl="d19" loc="d,19,10,19,11" id="10" name="logic" left="2" right="0" signed="true"/>
<basicdtype fl="d19" loc="d,19,11,19,12" id="9" name="logic" left="31" right="0"/>
<basicdtype fl="d19" loc="d,19,20,19,21" id="8" name="logic" left="3" right="0"/>
<basicdtype fl="d18" loc="d,18,12,18,13" id="4" name="logic" left="31" right="0"/>
<basicdtype fl="d19" loc="d,19,20,19,21" id="8" name="logic" left="3" right="0" signed="true"/>
<basicdtype fl="d18" loc="d,18,12,18,13" id="4" name="logic" left="31" right="0" signed="true"/>
<basicdtype fl="d18" loc="d,18,18,18,19" id="5" name="logic"/>
</typetable>
</netlist>

2
test_regress/t/t_xml_tag.out
View File

@ -55,7 +55,7 @@
</modport>
</iface>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d8" loc="d,8,4,8,11" id="6" name="integer" left="31" right="0"/>
<basicdtype fl="d8" loc="d,8,4,8,11" id="6" name="integer" left="31" right="0" signed="true"/>
<basicdtype fl="d14" loc="d,14,11,14,17" id="1" name="logic"/>
<basicdtype fl="d21" loc="d,21,7,21,12" id="8" name="logic"/>
<basicdtype fl="d22" loc="d,22,7,22,12" id="9" name="logic"/>