Version bump (Changes update)

This disables code motion during V3MergeCond, for debugging.

.clang-format

@@ -108,4 +108,3 @@ Standard:        Cpp11
 TabWidth:        8
 UseTab:          Never
 ...
-

.github/ISSUE_TEMPLATE/bug_report.md

@@ -1,6 +1,6 @@
 ---
 name: Bug report
-about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to report that something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -13,4 +13,6 @@ Can you attach an example that shows the issue?  (Must be openly licensed, ideal
 
 What 'verilator --version' are you using?  Did you try it with the git master version?
 
-Would you be willing to try to fix Verilator yourself with assistance?
+What OS and distribution are you using?
+
+May we assist you in trying to fix this in Verilator yourself?

.github/ISSUE_TEMPLATE/feature.md

@@ -1,6 +1,6 @@
 ---
 name: Feature Request
-about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -13,4 +13,4 @@ What would you like added/supported?
 
 Can you attach an example that runs on other simulators?  (Must be openly licensed, ideally in test_regress format.)
 
-May we assist you in trying to fix this yourself?
+May we assist you in trying to fix this in Verilator yourself?

.github/ISSUE_TEMPLATE/questions.md

@@ -1,6 +1,6 @@
 ---
 name: Q and A, or Other
-about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to ask a question, not related to a specific bug nor feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''

.github/workflows/build.yml

@@ -16,120 +16,143 @@ env:
   CI_COMMIT: ${{ github.sha }}
   CCACHE_COMPRESS: 1
   CCACHE_DIR: ${{ github.workspace }}/.ccache
-  CCACHE_MAXSIZE: 2Gi  # 2GiB for clang and gcc, 4GiB in total
+  CCACHE_LIMIT_MULTIPLE: 0.95
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
 
 jobs:
 
-
-  Matrix:
-    runs-on: ubuntu-latest
-    name: Generate Build matrix
-    outputs:
-      matrix: ${{ steps.generate.outputs.matrix }}
-    steps:
-    - uses: actions/checkout@v2
-    - id: generate
-      name: Run 'generate_matrix.sh'
-      run: |
-        if [ '${{ github.event_name}}' = 'pull_request' ]; then
-          matrix='[ "ubuntu-20.04" ]'
-        else
-          matrix='[ "ubuntu-16.04", "ubuntu-18.04", "ubuntu-20.04" ]'
-        fi
-        echo "::set-output name=matrix::$matrix"
-
-
-  Build:
-    needs: Matrix
+  build:
     strategy:
       fail-fast: false
       matrix:
-        os: ${{ fromJson(needs.Matrix.outputs.matrix) }}
-        debug: [ opt, dbg ]
+        os: [ubuntu-22.04, ubuntu-20.04, ubuntu-18.04]
         compiler:
           - { cc: clang, cxx: clang++ }
           - { cc: gcc,   cxx: g++     }
+        m32: [0, 1]
+        exclude:
+          # Build pull requests only with ubuntu-20.04 and without m32
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-22.04' || 'do-not-exclude' }}
+          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
+          # Build -m32 only on ubuntu-20.04
+          - {os: ubuntu-18.04, m32: 1}
+          - {os: ubuntu-22.04, m32: 1}
+        include:
+          # Build GCC 10 on ubuntu-20.04
+          - os: ubuntu-20.04
+            compiler: { cc: gcc-10, cxx: g++-10 }
+            m32: 0
     runs-on: ${{ matrix.os }}
-    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.debug }}
+    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} ${{ matrix.m32 && '| -m32' || '' }}
     env:
       CI_BUILD_STAGE_NAME: build
       CI_RUNS_ON: ${{ matrix.os }}
-      CI_MAKE_SRC_TARGET: ${{ matrix.debug }}
+      CI_M32: ${{ matrix.m32 }}
       CC: ${{ matrix.compiler.cc }}
       CXX: ${{ matrix.compiler.cxx }}
-      CACHE_KEY: ${{ matrix.os }}-${{ matrix.compiler.cc }}
+      CACHE_BASE_KEY: build-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}
+      CCACHE_MAXSIZE: 250M # Per build matrix entry (2000M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
     steps:
 
     - name: Checkout
       uses: actions/checkout@v2
+      with:
+        path: repo
 
-    - name: Cache
+    - name: Cache $CCACHE_DIR
       uses: actions/cache@v2
       env:
-        cache-name: ccache
+        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: ${{ env.CACHE_KEY }}-${{ env.cache-name }}
+        path: ${{ env.CCACHE_DIR }}
+        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+        restore-keys: |
+          ${{ env.CACHE_KEY }}-
 
     - name: Install packages for build
       run: ./ci/ci-install.bash
 
     - name: Build
-      run: |
-        ./ci/ci-script.bash
-        tar cvzf verilator-${{ matrix.os}}-${CI_COMMIT}-${{ matrix.compiler.cc }}-${{ matrix.debug }}.tgz ./bin
+      run: ./ci/ci-script.bash
 
-    - uses: actions/upload-artifact@v2
+    - name: Tar up repository
+      working-directory: ${{ github.workspace }}
+      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+    - name: Upload tar archive
+      uses: actions/upload-artifact@v2
       with:
-        path: verilator-${{ matrix.os}}-${{ env.CI_COMMIT }}-${{ matrix.compiler.cc }}-${{ matrix.debug }}.tgz
+        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
 
 
-  Test:
-    needs: [ Matrix, Build ]
+  test:
+    needs: build
     strategy:
       fail-fast: false
-      max-parallel: 8
       matrix:
-        os: ${{ fromJson(needs.Matrix.outputs.matrix) }}
+        os: [ubuntu-22.04, ubuntu-20.04, ubuntu-18.04]
         compiler:
           - { cc: clang, cxx: clang++ }
           - { cc: gcc,   cxx: g++     }
-        suite:
-          - dist-vlt-0
-          - dist-vlt-1
-          - vltmt-0
-          - vltmt-1
+        m32: [0, 1]
+        suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, vltmt-0, vltmt-1]
+        exclude:
+          # Build pull requests only with ubuntu-20.04 and without m32
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-22.04' || 'do-not-exclude' }}
+          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
+          # Build -m32 only on ubuntu-20.04
+          - {os: ubuntu-18.04, m32: 1}
+          - {os: ubuntu-22.04, m32: 1}
+        include:
+          # Test with GCC 10 on ubuntu-20.04 without m32
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-0}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-1}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-2}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-0}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-1}
     runs-on: ${{ matrix.os }}
-    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }}
+    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }} ${{ matrix.m32 && '| -m32' || '' }}
     env:
       CI_BUILD_STAGE_NAME: test
       CI_RUNS_ON: ${{ matrix.os }}
+      CI_M32: ${{ matrix.m32 }}
       CC: ${{ matrix.compiler.cc }}
       CXX: ${{ matrix.compiler.cxx }}
-      CACHE_KEY: ${{ matrix.os }}-${{ matrix.compiler.cc }}
+      CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}-${{ matrix.suite }}
+      CCACHE_MAXSIZE: 64M # Per build matrix entry (2160M in total)
+      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
     steps:
 
-    - name: Checkout
-      uses: actions/checkout@v2
+    - name: Download tar archive
+      uses: actions/download-artifact@v2
+      with:
+        name: ${{ env.VERILATOR_ARCHIVE }}
+        path: ${{ github.workspace }}
 
-    - name: Cache
+    - name: Unpack tar archive
+      working-directory: ${{ github.workspace }}
+      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
+
+    - name: Cache $CCACHE_DIR
       uses: actions/cache@v2
       env:
-        cache-name: ccache
+        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: ${{ env.CACHE_KEY }}-${{ env.cache-name }}
+        path: ${{ env.CCACHE_DIR }}
+        key: ${{ env.CACHE_KEY }}-${{ github.sha }}
+        restore-keys: |
+          ${{ env.CACHE_KEY }}-
 
-    - uses: actions/download-artifact@v2
-
-    - name: Install Verilator and test dependencies
-      run: |
-        tar xvzf artifact/verilator-${{ matrix.os}}-${CI_COMMIT}-${{ matrix.compiler.cc }}-opt.tgz
-        tar xvzf artifact/verilator-${{ matrix.os}}-${CI_COMMIT}-${{ matrix.compiler.cc }}-dbg.tgz
-        rm -rf artifact
-        ./ci/ci-install.bash
+    - name: Install test dependencies
+      run: ./ci/ci-install.bash
 
     - name: Test
       env:

.github/workflows/coverage.yml

@@ -11,10 +11,14 @@ on:
 env:
   CI_OS_NAME: linux
   CI_COMMIT: ${{ github.sha }}
-  CCACHE_COMPRESS: 1
-  CCACHE_DIR: ${{ github.workspace }}/.ccache
-  CCACHE_MAXSIZE: 2Gi  # 2GiB for clang and gcc, 4GiB in total
+  CI_M32: 0
   COVERAGE: 1
+  VERILATOR_ARCHIVE: verilator-coverage-${{ github.sha }}.tar.gz
+
+defaults:
+  run:
+    shell: bash
+    working-directory: repo
 
 jobs:
 
@@ -24,34 +28,28 @@ jobs:
     env:
       CI_BUILD_STAGE_NAME: build
       CI_RUNS_ON: ubuntu-20.04
-      CACHE_KEY: ubuntu-20.04-${{ matrix.compiler.cc }}-coverage
     steps:
 
     - name: Checkout
       uses: actions/checkout@v2
-
-    - name: Cache
-      uses: actions/cache@v2
-      env:
-        cache-name: ccache
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: coverage-${{ env.cache-name }}
+        path: repo
 
     - name: Install packages for build
-      env:
-        CI_BUILD_STAGE_NAME: build
       run: ./ci/ci-install.bash
 
     - name: Build
-      run: |
-        ./ci/ci-script.bash
-        tar cvzf verilator-${CI_COMMIT}-coverage.tgz bin src/obj*/*.o src/obj*/*.gcno
+      run: ./ci/ci-script.bash
 
-    - uses: actions/upload-artifact@v2
+    - name: Tar up repository
+      working-directory: ${{ github.workspace }}
+      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo
+
+    - name: Upload tar archive
+      uses: actions/upload-artifact@v2
       with:
-        path: verilator-${{ env.CI_COMMIT }}-coverage.tgz
+        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
 
 
   Test:
@@ -80,28 +78,20 @@ jobs:
     env:
       CI_BUILD_STAGE_NAME: test
       CI_RUNS_ON: ubuntu-20.04
-      CACHE_KEY: ubuntu-20.04-${{ matrix.compiler.cc }}-coverage
     steps:
 
-    - name: Checkout
-      uses: actions/checkout@v2
-
-    - name: Cache
-      uses: actions/cache@v2
-      env:
-        cache-name: ccache
+    - name: Download tar archive
+      uses: actions/download-artifact@v2
       with:
-        path: ${{ github.workspace }}/.ccache
-        key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }}
-        restore-keys: coverage-${{ env.cache-name }}
+        name: ${{ env.VERILATOR_ARCHIVE }}
+        path: ${{ github.workspace }}
 
-    - uses: actions/download-artifact@v2
+    - name: Unpack tar archive
+      working-directory: ${{ github.workspace }}
+      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}
 
-    - name: Install Verilator and test dependencies
-      run: |
-        tar xvzf artifact/verilator-${CI_COMMIT}-coverage.tgz
-        touch src/obj*/*.o src/obj*/*.gcno
-        ./ci/ci-install.bash
+    - name: Install test dependencies
+      run: ./ci/ci-install.bash
 
     - name: Test
       env:

.github/workflows/format.yml

@@ -1,7 +1,7 @@
 # DESCRIPTION: Github actions config
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-name: clang-format
+name: format
 
 on:
   push:
@@ -16,6 +16,7 @@ jobs:
       CI_OS_NAME: linux
       CI_RUNS_ON: ubuntu-20.04
       CI_COMMIT: ${{ github.sha }}
+      CI_M32: 0
     steps:
       - name: Checkout
         uses: actions/checkout@v2
@@ -26,18 +27,18 @@ jobs:
           CI_BUILD_STAGE_NAME: build
         run: |
           bash ci/ci-install.bash &&
-          sudo apt-get install clang-10 yapf3 &&
+          sudo apt-get install clang-format-11 yapf3 &&
           git config --global user.email "[email protected]" &&
           git config --global user.name "github action"
       - name: Format code
         run: |
           autoconf &&
           ./configure &&
-          make -j 2 format CLANGFORMAT=clang-format-10 &&
+          make -j 2 format CLANGFORMAT=clang-format-11 &&
           git status
       - name: Push
         run: |
           if [ -n "$(git status --porcelain)" ]; then
-            git commit . -m "Apply clang-format" &&
+            git commit . -m "Apply 'make format'" &&
             git push origin
           fi

.gitignore

@@ -39,3 +39,4 @@ verilator-config-version.cmake
 **/__pycache__/*
 **/_build/*
 **/obj_dir/*
+/.vscode/

CPPLINT.cfg

@@ -0,0 +1,17 @@
+set noparent
+linelength=100
+filter=-build/c++11
+filter=-build/header_guard
+filter=-build/include_order
+filter=-build/include_subdir
+filter=-readability/inheritance
+filter=-readability/nolint
+filter=-readability/todo
+filter=-runtime/references
+filter=-whitespace/blank_line
+filter=-whitespace/empty_if_body
+filter=-whitespace/indent
+filter=-whitespace/newline
+filter=-whitespace/braces
+filter=-whitespace/parens
+filter=-whitespace/todo

Changes

@@ -8,6 +8,273 @@ The changes in each Verilator version are described below.  The
 contributors that suggested a given feature are shown in []. Thanks!
 
 
+Verilator 4.224 2022-06-19
+==========================
+
+**Major:**
+
+* VCD tracing is now parallelized with --threads (#3449). [Geza Lore, Shunyao CAD]
+
+**Minor:**
+
+* Add -f<optimization> options to replace -O<letter> options (#3436).
+* Changed --no-merge-const-pool to -fno-merge-const-pool (#3436).
+* Changed --no-decoration to remove output whitespace (#3460). [Kamil Rakoczy]
+* Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
+* Support non-ANSI interface port declarations (#3439). [Geza Lore, Shunyao CAD]
+* Support concat assignment to packed array (#3446).
+* Improve conditional merging optimization (#3125). [Geza Lore, Shunyao CAD]
+* Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
+* Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
+* Internal prep work towards timing control. [Krzysztof Bieganski]
+* Fix hang with large case statement optimization (#3405). [Mike Urbach]
+* Fix UNOPTFLAT warning from initial static var (#3406). [Kamil Rakoczy]
+* Fix compile error when enable VL_LEAK_CHECKS (#3411). [HungMingWu]
+* Fix cmake rules to support higher-level targets (#3377) (#3386). [Martin Stadler]
+* Fix BLKANDNBLK on $readmem/$writemem (#3379). [Alex Solomatnikov]
+* Fix 'with' operator with type casting (#3387). [xiak95]
+* Fix incorrect conditional merging (#3409). [Raynard Qiao]
+* Fix passing VL_TRACE_FST_WRITER_THREAD in CMake build. [Geza Lore, Shunyao CAD]
+* Fix compile error under strict C++11 mode (#3463). [Kevin Kiningham]
+* Fix public unpacked input ports (#3465). [Todd Strader]
+
+
+Verilator 4.222 2022-05-02
+==========================
+
+**Minor:**
+
+* Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD]
+* Deprecate 'vluint64_t' and similar types (#3255).
+* Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD]
+* Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD]
+* Support LoongArch ISA multithreading (#3353) (#3354). [Xi Zhang]
+* Fix MSVC localtime_s (#3124).
+* Fix Bison 3.8.2 error (#3366). [elike-ypq]
+* Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD]
+* Fix tracing interfaces inside interfaces (#3309). [Kevin Millis]
+* Fix filenames with dots overwriting debug .vpp files (#3373).
+* Fix including VK_USER_OBJS in make library (#3370) (#3382). [Julien Margetts]
+* Fix hang in generate symbol references (#3391) (#3398). [Yoda Lee]
+* Fix missing #include <memory> (#3392). [Aliaksei Chapyzhenka]
+* Fix crash in recursive module inlining (#3393). [david-sawatzke]
+* Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD]
+* Fix foreach segmentation fault (#3400). [Kamil Rakoczy]
+
+
+Verilator 4.220 2022-03-12
+==========================
+
+**Minor:**
+
+* Removed the deprecated lint_off flag -msg; use -rule instead.
+* Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
+* Suppress WIDTH warning on negate using carry bit (#3295). [Peter Monsson]
+* Add trace dumpvars() call for selective runtime tracing (#3322). [Shunyao CAD]
+* Add VERILATOR_VERSION_INTEGER for determining API (#3343). [Larry Doolittle]
+* Improve various V3Combine algorithm details (#3328). [Yutetsu TAKATSUKASA]
+* Improve various V3Order algorithm details. [Geza Lore]
+* Fix MacOS arm64 build (#3285) (#3291). [Guokai Chen]
+* Fix signed number operation (#3294) (#3308). [Raynard Qiao]
+* Fix FST traces to include vector range (#3296) (#3297). [Jamie Iles]
+* Fix skipping public enum values with four-state values (#3303).
+* Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman]
+* Fix class stringification on wide arrays (#3312). [Iru Cai]
+* Fix $fscanf etc to return -1 on EOF (#3313). [Jose Tejada]
+* Fix public function arguments that are arrayed (#3316). [pawel256]
+* Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka]
+* Fix crash in recursive module inlining (#3324). [Larry Doolittle]
+* Fix VL_RESTORER behavior on passing a lvalue reference (#3326). [HungMingWu]
+* Fix compile error with --trace-fst --sc (#3332). [leavinel]
+* Fix cast to array types (#3333). [Todd Strader]
+* Fix Vdeeptemp error with --threads and --compiler clang (#3338). [Per Karlsson]
+
+
+Verilator 4.218 2022-01-17
+==========================
+
+**Major:**
+
+* Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type.
+  In general this should be backward compatible, but may lead to some
+  wrapper code needing changes.
+* Option --cdc is deprecated and is planned for removal,
+  file a bug if this is still being used.
+
+**Minor:**
+
+* Support class static members (#2233).
+* Support force/release (#2431) (#2593). [Shunyao CAD]
+* Add 'forceable' attribute to allow forcing from C++. (#3272). [Geza Lore, Shunyao CAD]
+* Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim]
+* Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman]
+* Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD]
+* Support FST tracing in hierarchical Verilation (#3251). [Yutetsu TAKATSUKASA]
+* Use C++11 standard types for MacOS portability (#3254) (#3257). [Adrien Le Masle]
+* Fix make support for BSD ar (#2999) (#3256). [Julie Schwartz]
+* Fix bad ending address on $readmem (#3205). [Julie Schwartz]
+* Fix MSWIN compile error (#2681). [Unai Martinez-Corral]
+* Fix break under foreach loop (#3230).
+* Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235). [Adrien Le Masle]
+* Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle]
+* Fix associative array first method as statement (#3228). [Adrien Le Masle]
+* Fix associative array foreach loop (#3229).
+* Fix $fclose not accepting expressions (#3237). [Julie Schwartz]
+* Fix $random not updating seed (#3238). [Julie Schwartz]
+* Fix top level param overwrite when package has same param (#3241) (#3247). [Adrien Le Masle]
+* Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz]
+* Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD]
+* Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA]
+* Fix GCC 11 compile error (#3273). [HungMingWu]
+
+
+Verilator 4.216 2021-12-05
+==========================
+
+**Major:**
+
+* Add --lib-create, similar to --protect-lib but without protections.
+* Support tracing through --hierarchical/--lib-create libraries (#3200).
+
+**Minor:**
+
+* Internal code cleanups and improvements. [Geza Lore]
+* Improve --thread Verilation-time performance.
+* Support task name in $display %m (#3211). [Julie Schwartz]
+* Make 'bit', 'logic' and 'time' types unsigned by default. [Geza Lore]
+* Optimize $random concatenates/selects (#3114).
+* Fix array method names with parenthesis (#3181) (#3183). [Teng Huang]
+* Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA]
+* Fix wrong bit op tree optimization (#3185). [Yutetsu TAKATSUKASA]
+* Fix some SliceSels not being constants (#3186) (#3218). [Michaël Lefebvre]
+* Fix nested generate if genblk naming (#3189). [yanx21]
+* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
+* Fix display of signed without format (#3204). [Julie Schwartz]
+* Fix display of empty string constant (#3207) (#3215). [Julie Schwartz]
+* Fix incorrect width after and-or optimization (#3208). [Julie Schwartz]
+* Fix $fopen etc on integer arrays (#3214). [adrienlemasle]
+* Fix $size on dynamic strings (#3216).
+* Fix %0 format on $value$plusargs (#3217).
+* Fix timescale portability on Arm64 (#3222).
+
+
+Verilator 4.214 2021-10-17
+==========================
+
+**Major:**
+
+* Add profile-guided optimization of mtasks (#3150).
+
+**Minor:**
+
+* Verilator_gantt has removed the ASCII graphics, use the VCD output instead.
+* Verilator_gantt now shows the predicted mtask times, eval times, and additional statistics.
+* Verilator_gantt data files now include processor information, to allow later processing.
+* Support displaying x and z in $display task (#3107) (#3109). [Iru Cai]
+* Fix verilator_profcfunc profile accounting (#3115).
+* Fix display has no time units on class function (#3116). [Damien Pretet]
+* Fix removing if statement with side effect in condition (#3131). [Alexander Grobman]
+* Fix --waiver-output for multiline warnings (#2429) (#3141). [Keith Colbert]
+* Fix internal error on bad widths (#3140) (#3145). [Zhanglei Wang]
+* Fix crash on clang 12/13 (#3148). [Kouping Hsu]
+* Fix cygwin compile error due to missing -std=gnu++14 (#3149). [Sun Kim]
+* Fix $urandom_range when the range is 0 ... UINT_MAX (#3161). [Iru Cai]
+* Fix constructor-parameter argument comma-separation in C++ (#3162). [Matthew Ballance]
+* Fix missing install of vl_file_copy/vl_hier_graph (#3165). [Popolon]
+* Fix calling new with arguments in same class (#3166). [Matthew Ballance]
+* Fix false EOFNEWLINE warning when DOS carriage returns present (#3171).
+
+
+Verilator 4.212 2021-09-01
+==========================
+
+**Minor:**
+
+* Fix re-evaluation of logic dependent on state set in DPI exports (#3091). [Geza Lore]
+* Support unpacked array localparams in tasks/functions (#3078). [Geza Lore]
+* Support timeunit/timeprecision in $unit.
+* Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski]
+* Add --instr-count-dpi to tune assumed DPI import cost for multithreaded
+  model scheduling. Default value changed to 200 (#3068). [Yinan Xu]
+* Output files are split based on the set of headers required
+  in order to aid incremental compilation via ccache (#3071). [Geza Lore]
+* Parameter values are now emitted as 'static constexpr' instead of enum.
+  C++ direct references to parameters might require updating (#3077). [Geza Lore]
+* Refactored Verilated include files; include verilated.h not verilated_heavy.h.
+* Add header guards on Dpi.h generated files (#2979). [Tood Strader]
+* Add XML ccall, constpool, initarray, and if/while begins (#3080). [Steven Hugg]
+* Add error when constant function under a generate (#3103). [Don Owen]
+* Fix -G to treat simple integer literals as signed (#3060). [Anikin1610]
+* Fix emitted string array initializers (#2895). [Iztok Jeras]
+* Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt]
+* Fix internal error on wide -x-initial unique (#3106). [Alexandre Joannou]
+* Fix traces to show array instances with brackets (#3092) (#3095). [Pieter Kapsenberg]
+
+
+Verilator 4.210 2021-07-07
+==========================
+
+**Major:**
+
+* Generated code is now emitted as global functions rather than methods. '$c'
+  contents might need to be updated, see the docs (#3006). [Geza Lore]
+* The generated model class instantiated by the user is now an interface
+  object and no longer the TOP module instance.  User code with direct
+  C++ member access to model internals, including verilator public_flat
+  items will likely need to be updated. See the manual for instructions:
+  https://verilator.org/guide/latest/connecting.html#porting-from-pre-4-210
+  (#3036). [Geza Lore]
+
+**Minor:**
+
+* Add --prof-c to pass profiling to compiler (#3059). [Alexander Grobman]
+* Optimize a lot more model variables into function locals (#3027). [Geza Lore]
+* Support middle-of-design nested top modules (#3026). [Dan Petrisko]
+* Remove deprecated --no-relative-cfuncs option (#3024). [Geza Lore]
+* Remove deprecated --inhibit-sim option (#3035). [Geza Lore]
+* Merge const static data globally into a new constant pool (#3013). [Geza Lore]
+* Allow configure override of AR program (#2999). [ahouska]
+* In XML, show pinIndex information (#2877). [errae233]
+* Fix error on unsupported recursive functions (#2957). [Trefor Southwell]
+* Fix type parameter specialization when struct names are same (#3055). [7FM]
+* Improve speed of table optimization (-OA) pass. [Geza Lore]
+
+
+Verilator 4.204 2021-06-12
+==========================
+
+**Minor:**
+
+* Add 'make ccache-report' (#3011). [Geza Lore]
+* Add --reloop-limit argument (#2943) (#2960). [Geza Lore]
+* Add --expand-limit argument (#3005). [Julien Margetts]
+* Add TRACE_THREADS to CMake (#2934). [Jonathan Drolet]
+* Optimize large lookup tables to static data (#2925). [Geza Lore]
+* Optimize reloop to accept constant index offsets (#2939). [Geza Lore]
+* Split always blocks to better respect --output-split-cfuncs. [Geza Lore]
+* Support ignoring "`pragma protect ..." (#2886). [Udi Finkelstein]
+* Support --trace-fst for SystemC with CMake (#2927). [Jonathan Drolet]
+* Update cmake latest C++ Standard Compilation flag (#2951). [Ameya Vikram Singh]
+* Prep work towards better ccache hashing/performance. [Geza Lore]
+* Fix assertion failure in bitOpTree optimization (#2891) (#2899). [Raynard Qiao]
+* Fix DPI functions not seen as vpiModule (#2893). [Todd Strader]
+* Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski]
+* Fix slowdown in elaboration (#2911). [Nathan Graybeal]
+* Fix initialization of assoc in assoc array (#2914). [myftptoyman]
+* Fix make support for gmake 3.x (#2920) (#2921). [Philipp Wagner]
+* Fix VPI memory access for packed arrays (#2922). [Todd Strader]
+* Fix MCD close also closing stdout (#2931). [Alexander Grobman]
+* Fix split procedures to better respect --output-split-cfuncs (#2942). [Geza Lore]
+* Fix to emit 'else if' without nesting (#2944). [Geza Lore]
+* Fix part select issues in LATCH warning (#2948) (#2938). [Julien Margetts]
+* Fix to not emit empty files with low split limits (#2961). [Geza Lore]
+* Fix merging of assignments in C++ code (#2970). [Rupert Swarbrick]
+* Fix unused variable warnings (#2991). [Pieter Kapsenberg]
+* Fix --protect-ids when using SV classes (#2994). [Geza Lore]
+* Fix constant function calls with uninitialized value (#2995). [yanx21]
+* Fix Makefiles to support Windows EXEEXT usage (#3008). [Miodrag Milanovic]
+
+
 Verilator 4.202 2021-04-24
 ==========================
 
@@ -42,7 +309,7 @@ Verilator 4.202 2021-04-24
 * Fix Cygwin example compile issues (#2856). [Mark Shaw]
 * Fix select of with index variable (#2880). [Alexander Grobman]
 * Fix cmake version number to be numeric (#2881). [Yuri Victorovich]
-* Fix MinGW not supportting 'localtime_r' (#2882). [HyungKi Jeong]
+* Fix MinGW not supporting 'localtime_r' (#2882). [HyungKi Jeong]
 * Fix cast from packed, typedef'ed interface signal (#2884). [Todd Strader]
 * Fix VPI package reported as vpiModule (#2885). [Todd Strader]
 * Fix dumping waveforms to multiple FST files (#2889). [David Metz]
@@ -189,7 +456,7 @@ Verilator 4.102 2020-10-15
 * Support # as a comment in -f files (#2497). [phantom-killua]
 * Support 'this' (#2585). [Rafal Kapuscik]
 * Support defines for FST tracing (#2592). [Markus Krause]
-* Support non-overapping implication inside properties (#1292). [Peter Monsson]
+* Support non-overlapping implication inside properties (#1292). [Peter Monsson]
 * Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA]
 * Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA]
 * Fix -G dropping public indication (#2561). [Andrew Goessling]
@@ -215,7 +482,7 @@ Verilator 4.100 2020-09-07
 * Support (with limitations) class extern, class extends, virtual class.
 * Support $urandom, $urandom_range without stability.
 * Support assume property. [Peter Monsson]
-* Support non-overapping implication inside properties (#1292). [Peter Monsson]
+* Support non-overlapping implication inside properties (#1292). [Peter Monsson]
 * Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner]
 * Fix naming of "id : begin" blocks.
 * Fix class constructor error on assignments to const.
@@ -331,7 +598,7 @@ Verilator 4.034 2020-05-03
 * Support event data type (with some restrictions).
 * Support $root. (#2150) [Keyi Zhang]
 * Add error if use SystemC 2.2 and earlier (pre-2011) as is deprecated.
-* Fix build of fast path tracing code to use OPT_FAST. (#2245) [Geza Lore]
+* Add support of --trace-structs for CMake (#2986). [Martin Schmidt]
 * Fix arrayed instances connecting to slices. (#2263) [Don/engr248]
 * Fix error on unpacked connecting to packed. (#2288) [Joseph Shaker]
 * Fix logical not optimization with empty begin. (#2291) [Baltazar Ortiz]
@@ -3615,7 +3882,7 @@ Verilator 0.0 1994-07-08
 Copyright
 =========
 
-Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

MANIFEST.SKIP

@@ -1,76 +0,0 @@
-\.ccache/
-\.clang-format
-\.clang-tidy
-\.git/
-\.git$
-\.github/
-\.svn/
-\.(bak|old)/
-\.(bak|old)$
-\.tar\.
-.*\.tgz
-.*\.log
-\..*\.swp
-.*\.tmp
-.*\.tidy
-.*\.tex
-.*\.key
-.*\.vcd
-.*\.1
-\.codacy\.yml
-\.travis\.yml
-/_build/
-/build/
-/obj_dbg/
-/obj_dir/
-/obj_dist/
-/obj_iv/
-/obj_ms/
-/obj_nc/
-/obj_opt/
-/obj_vcs/
-/obj_vlt/
-/obj_vltmt/
-INCA_libs/
-/cov_work/
-/logs/
-^Makefile$
-README.html
-bin/verilator_bin.*
-bin/verilator_coverage_bin.*
-docs/.*\.html$
-docs/_build/
-docs/clang-format.txt$
-docs/doxygen-doc/.*
-docs/spelling.txt
-examples/xml_py/copied/
-examples/xml_py/graph.*
-sonar-project.properties
-src/Makefile$
-src/Makefile_obj$
-include/verilated.mk$
-test_regress/.gdbinit$
-test_regress/transcript
-codecov.yml
-config.cache$
-config.status$
-verilator\.log
-verilator\.tex
-verilator-config.cmake$
-verilator-config-version.cmake$
-verilator.pc$
-verilator_bin.*
-verilator_coverage_bin.*
-.vcsmx_rebuild$
-ncverilog.history
-autom4te\.cache/
-nodist/
-ci/
-/simv$
-/simv.daidir/
-/vc_hdrs.h$
-/csrc/
-obj_dir.*
-TAGS
-gmon.out
-.*~

Makefile.in

@@ -7,7 +7,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -44,6 +44,7 @@
 srcdir = @srcdir@
 VPATH = @srcdir@
 HOST = @HOST@
+EXEEXT = @EXEEXT@
 
 DOXYGEN = doxygen
 INSTALL = @INSTALL@
@@ -117,96 +118,6 @@ INFOS = verilator.html verilator.pdf
 
 INFOS_OLD = README README.html README.pdf
 
-# Files that can be generated, but should be up to date for a distribution.
-DISTDEP = info Makefile
-
-DISTFILES1 = $(INFOS) .gitignore \
-	*.in *.ac \
-	Artistic \
-	Changes \
-	LICENSE \
-	MANIFEST.SKIP \
-	README.rst \
-	verilator-config.cmake.in \
-	verilator-config-version.cmake.in \
-	bin/verilator \
-	bin/verilator_coverage \
-	bin/verilator_difftree \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	docs/.gitignore \
-	docs/CONTRIBUTING.rst \
-	docs/CONTRIBUTORS \
-	docs/Makefile \
-	docs/_static/*.png \
-	docs/_static/css/* \
-	docs/bin/* \
-	docs/gen/* \
-	docs/guide/*.py \
-	docs/guide/*.rst \
-	docs/guide/figures/* \
-	docs/install.rst \
-	docs/internals.rst \
-	docs/internals.rst \
-	docs/verilated.dox \
-	docs/xml.rst \
-	install-sh configure *.pod \
-	include/*.[chv]* \
-	include/*.in \
-	include/.*ignore \
-	include/gtkwave/*.[chv]* \
-	include/vltstd/*.[chv]* \
-	.*attributes */.*attributes  */*/.*attributes \
-	src/.*ignore src/*.in src/*.cpp src/*.[chly] \
-	src/astgen src/bisonpre src/*fix src/cppcheck_filtered \
-	src/config_rev \
-	src/vlcovgen src/mkinstalldirs \
-	src/.gdbinit \
-	src/*.pl src/*.pod \
-	examples/*/.*ignore examples/*/Makefile* \
-	examples/*/*.[chv]* examples/*/vl_* \
-	examples/*/CMakeLists.txt \
-
-DISTFILES2 = \
-	test_*/.*ignore test_*/Makefile* test_*/*.cpp \
-	test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \
-	test_regress/*.pl \
-	test_regress/Makefile \
-	test_regress/Makefile_obj \
-	test_regress/input.vc \
-	test_regress/CMakeLists.txt \
-	test_regress/t/t*/*.sv* \
-	test_regress/t/t*/*.v* \
-	test_regress/t/t*/*/*.sv* \
-	test_regress/t/t*/*/*.v* \
-	test_regress/t/t*/*.cpp \
-	test_regress/t/t*/CMakeLists.txt \
-	test_regress/t/*.cpp \
-	test_regress/t/*.h \
-	test_regress/t/*.dat \
-	test_regress/t/*.mem \
-	test_regress/t/*.out \
-	test_regress/t/*.pl \
-	test_regress/t/*.pf \
-	test_regress/t/*.v* \
-
-INST_PROJ_FILES = \
-	bin/verilator \
-	bin/verilator_coverage \
-	bin/verilator_gantt \
-	bin/verilator_includer \
-	bin/verilator_profcfunc \
-	include/verilated.mk \
-	include/*.[chv]* \
-	include/gtkwave/*.[chv]* \
-	include/vltstd/*.[chv]* \
-
-INST_PROJ_BIN_FILES = \
-	bin/verilator_bin \
-	bin/verilator_bin_dbg \
-	bin/verilator_coverage_bin_dbg \
-
 EXAMPLES_FIRST = \
 	examples/make_hello_c \
 	examples/make_hello_sc \
@@ -214,20 +125,20 @@ EXAMPLES_FIRST = \
 EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*)))
 
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_MAN_FILES = verilator.1 verilator_coverage.1 verilator_gantt.1 verilator_profcfunc.1
+VL_INST_MAN_FILES = verilator.1 verilator_coverage.1
 
 default: all
 all: all_nomsg msg_test
 all_nomsg: verilator_exe $(VL_INST_MAN_FILES)
 
 .PHONY:verilator_exe
-.PHONY:verilator_bin
-.PHONY:verilator_bin_dbg
-.PHONY:verilator_coverage_bin_dbg
-verilator_exe verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg:
+.PHONY:verilator_bin$(EXEEXT)
+.PHONY:verilator_bin_dbg$(EXEEXT)
+.PHONY:verilator_coverage_bin_dbg$(EXEEXT)
+verilator_exe verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT):
 	@echo ------------------------------------------------------------
 	@echo "making verilator in src"
-	$(MAKE) -C src $(OBJCACHE_JOBS) $(CI_MAKE_SRC_TARGET)
+	$(MAKE) -C src $(OBJCACHE_JOBS)
 
 .PHONY:msg_test
 msg_test: all_nomsg
@@ -280,8 +191,8 @@ verilator.pdf: Makefile
 	$(MAKE) -C docs verilator.pdf
 
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg \
-	verilator_coverage verilator_gantt verilator_includer verilator_profcfunc
+VL_INST_BIN_FILES = verilator verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT) \
+	verilator_ccache_report verilator_coverage verilator_gantt verilator_includer verilator_profcfunc
 # Some scripts go into both the search path and pkgdatadir,
 # so they can be found by the user, and under $VERILATOR_ROOT.
 
@@ -296,8 +207,10 @@ VL_INST_INC_SRCDIR_FILES = \
 	include/vltstd/*.[chv]* \
 
 VL_INST_DATA_SRCDIR_FILES = \
-	examples/*/*.[chv]*  examples/*/Makefile* \
-	examples/*/CMakeLists.txt
+	examples/*/*.[chv]* \
+	examples/*/CMakeLists.txt \
+	examples/*/Makefile* \
+	examples/*/vl_* \
 
 installbin:
 	$(MKINSTALLDIRS) $(DESTDIR)$(bindir)
@@ -305,11 +218,12 @@ installbin:
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_coverage $(DESTDIR)$(bindir)/verilator_coverage )
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_gantt $(DESTDIR)$(bindir)/verilator_gantt )
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg )
-	( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_bin$(EXEEXT) $(DESTDIR)$(bindir)/verilator_bin$(EXEEXT) )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_bin_dbg$(EXEEXT) $(DESTDIR)$(bindir)/verilator_bin_dbg$(EXEEXT) )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_coverage_bin_dbg$(EXEEXT) $(DESTDIR)$(bindir)/verilator_coverage_bin_dbg$(EXEEXT) )
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer )
+	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_ccache_report $(DESTDIR)$(pkgdatadir)/bin/verilator_ccache_report )
 
 # Man files can either be part of the original kit, or built in current directory
 # So important we use $^ so VPATH is searched
@@ -382,44 +296,7 @@ uninstall:
 install: all_nomsg install-all
 install-all: installbin installman installdata install-msg
 
-install-here: installman ftp
-
-ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
-DISTNAMEREV = $(shell sed -e '/DTVERSION/!d' -e 's/.*verilator_\([^"]*\).*/\1/' -e q ${srcdir}/src/config_rev.h)
-
-VERILATOR_CAD_DIR = $(CAD_DIR)/verilator/$(DISTNAMEREV)/$(DIRPROJECT_ARCH)
-INST_PROJ_CVS = cp_if_cvs_diff
-
-install-cadtools: dist
-	@echo "Install-project to $(CAD_DIR)"
-	strip bin/verilator_bin*
-	strip bin/verilator_coverage_bin*
-	$(MAKE) install-cadtools-quick
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/man/man1
-	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_DATA) $$p $(VERILATOR_CAD_DIR)/man/man1/$$p; \
-	done
-	$(INST_PROJ_CVS) $(DISTNAME).tgz $(VERILATOR_CAD_DIR)/verilator.tgz
-	rm $(DISTNAME).tgz
-
-install-cadtools-quick:
-ifeq ($(CFG_WITH_DEFENV),yes)
-	@echo "%Error: Reconfigure with './configure --disable-defenv' to avoid hardcoded paths."
-	false
-endif
-	@echo "Install-cadtools-quick (no strip) to $(VERILATOR_CAD_DIR)"
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/include/gtkwave
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/include/vltstd
-	$(MKINSTALLDIRS) $(VERILATOR_CAD_DIR)/bin
-	for p in $(INST_PROJ_FILES) ; do \
-	  $(INST_PROJ_CVS) $$p $(VERILATOR_CAD_DIR)/$$p; \
-	done
-	for p in $(INST_PROJ_BIN_FILES) ; do \
-	  $(INST_PROJ_CVS) $$p $(VERILATOR_CAD_DIR)/$$p; \
-	done
-
-# VERILATOR_AUTHOR_SITE
-endif
+install-here: installman info
 
 # Use --xml flag to see the cppcheck code to use for suppression
 CPPCHECK_CPP = $(wildcard \
@@ -458,7 +335,7 @@ clang-tidy: $(CLANGTIDY_DEP)
 
 analyzer-src:
 	-rm -rf src/obj_dbg
-	scan-build $(MAKE) -k verilator_coverage_bin_dbg verilator_bin_dbg
+	scan-build $(MAKE) -k verilator_coverage_bin_dbg$(EXEEXT) verilator_bin_dbg$(EXEEXT)
 
 analyzer-include:
 	-rm -rf examples/*/obj*
@@ -466,28 +343,32 @@ analyzer-include:
 
 format: clang-format yapf format-pl-exec
 
-CLANGFORMAT = clang-format
+CLANGFORMAT = clang-format-11
 CLANGFORMAT_FLAGS = -i
 CLANGFORMAT_FILES = $(CPPCHECK_CPP) $(CPPCHECK_H) $(CPPCHECK_YL) test_regress/t/*.c* test_regress/t/*.h
 
 clang-format:
-	@$(CLANGFORMAT) --version | egrep 10.0 > /dev/null \
-		|| echo "*** You are not using clang-format 10.0, indents may differ from master's ***"
+	@$(CLANGFORMAT) --version | egrep 11.0 > /dev/null \
+		|| echo "*** You are not using clang-format 11.0, indents may differ from master's ***"
 	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)
 
 PY_PROGRAMS = \
+	bin/verilator_ccache_report \
+	bin/verilator_difftree \
+	bin/verilator_gantt \
+	bin/verilator_profcfunc \
 	examples/xml_py/vl_file_copy \
 	examples/xml_py/vl_hier_graph \
 	docs/guide/conf.py \
-	docs/guide/vl_sphinx_extract \
-	docs/guide/vl_sphinx_extract \
-	docs/guide/vl_doxygen_filter \
+	docs/bin/vl_sphinx_extract \
+	docs/bin/vl_sphinx_fix \
 	src/astgen \
 	src/bisonpre \
 	src/config_rev \
 	src/cppcheck_filtered \
 	src/flexfix \
 	src/vlcovgen \
+	test_regress/t/*.pf \
 	nodist/code_coverage \
 	nodist/dot_importer \
 	nodist/fuzzer/actual_fail \
@@ -519,9 +400,6 @@ lint-py:
 format-pl-exec:
 	-chmod a+x test_regress/t/*.pl
 
-
-ftp: info
-
 install-msg:
 	@echo
 	@echo "Installed binaries to $(DESTDIR)$(bindir)/verilator"
@@ -592,15 +470,6 @@ TAGS:	$(TAGFILES)
 doxygen:
 	$(MAKE) -C docs doxygen
 
-######################################################################
-# Test targets
-
-dist-file-list:
-	@echo "begin-dist-file-list:";  # Scripts look for this
-	@echo $(wildcard $(DISTFILES1))
-	@echo $(wildcard $(DISTFILES2))
-	@echo "end-dist-file-list:";  # Scripts look for this
-
 ######################################################################
 # Distributions
 
@@ -608,36 +477,16 @@ DISTTITLE := Verilator $(word 1,$(PACKAGE_VERSION))
 DISTNAME := verilator-$(word 1,$(PACKAGE_VERSION))
 DISTDATEPRE := $(word 2,$(PACKAGE_VERSION))
 DISTDATE := $(subst /,-,$(DISTDATEPRE))
-
 DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME)))
 
 tag:
 	svnorcvs tag $(DISTTAGNAME)
 
-# Don't depend on DISTFILES because there's no rule for "standards.info*".
-dist: $(DISTDEP) maintainer-copy
-	-rm -fr $(DISTNAME)
-	for file in $(DISTFILES1); do \
-	  mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \
-	  ln $$file $(DISTNAME)/$$file \
-	  || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \
-	done; true;
-	for file in $(DISTFILES2); do \
-	  mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \
-	  ln $$file $(DISTNAME)/$$file \
-	  || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \
-	done; true;
-	chmod -R a+r $(DISTNAME)
-	tar chf $(DISTNAME).tar $(DISTNAME)
-	gzip --force --best $(DISTNAME).tar
-	mv $(DISTNAME).tar.gz $(DISTNAME).tgz
-	rm -fr $(DISTNAME)
-
 maintainer-diff:
 	svnorcvs diff $(DISTTAGNAME)
 
 preexist:
 	svnorcvs nexists $(DISTTAGNAME)
 
-maintainer-dist: preexist dist tag
-	svnorcvs release $(DISTNAME).tgz
+maintainer-dist: preexist tag
+	svnorcvs release $(DISTTAGNAME)

README.rst

@@ -5,6 +5,8 @@
     :target: https://www.gnu.org/licenses/lgpl-3.0]
 .. image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg
     :target: https://opensource.org/licenses/Artistic-2.0
+.. image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages
+    :target: https://repology.org/project/verilator/versions
 .. image:: https://api.codacy.com/project/badge/Grade/fa78caa433c84a4ab9049c43e9debc6f
     :target: https://www.codacy.com/gh/verilator/verilator
 .. image:: https://codecov.io/gh/verilator/verilator/branch/master/graph/badge.svg
@@ -12,13 +14,14 @@
 .. image:: https://github.com/verilator/verilator/workflows/build/badge.svg
     :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild
 
+
 Welcome to Verilator
 ====================
 
 .. list-table::
 
    * - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**
-        * Accepts synthesizable Verilog or SystemVerilog
+        * Accepts Verilog or SystemVerilog
         * Performs lint code-quality checks
         * Compiles into multithreaded C++, or SystemC
         * Creates XML to front-end your own tools
@@ -54,23 +57,24 @@ files, the "Verilated" code.
 
 The user writes a little C++/SystemC wrapper file, which instantiates the
 "Verilated" model of the user's top level module. These C++/SystemC files
-are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting
-executable performs the design simulation. Verilator also supports linking
-its generated libraries, optionally encrypted, into other simulators.
+are then compiled by a C++ compiler (gcc/clang/MSVC++). Executing the
+resulting executable performs the design simulation. Verilator also
+supports linking Verilated generated libraries, optionally encrypted, into
+other simulators.
 
 Verilator may not be the best choice if you are expecting a full featured
-replacement for NC-Verilog, VCS or another commercial Verilog simulator, or
-if you are looking for a behavioral Verilog simulator e.g. for a quick
-class project (we recommend `Icarus Verilog`_ for this.) However, if you
-are looking for a path to migrate SystemVerilog to C++ or SystemC, or your
-team is comfortable writing just a touch of C++ code, Verilator is the tool
-for you.
+replacement for Incisive, ModelSim/Questa, VCS or another commercial
+Verilog simulator, or if you are looking for a behavioral Verilog simulator
+e.g. for a quick class project (we recommend `Icarus Verilog`_ for this.)
+However, if you are looking for a path to migrate SystemVerilog to C++ or
+SystemC, or your team is comfortable writing just a touch of C++ code,
+Verilator is the tool for you.
 
 
 Performance
 ===========
 
-Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather,
+Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
 Verilator compiles your code into a much faster optimized and optionally
 thread-partitioned model, which is in turn wrapped inside a C++/SystemC
 module. The results are a compiled Verilog model that executes even on a
@@ -134,7 +138,7 @@ Related Projects
 Open License
 ============
 
-Verilator is Copyright 2003-2021 by Wilson Snyder. (Report bugs to
+Verilator is Copyright 2003-2022 by Wilson Snyder. (Report bugs to
 `Verilator Issues <https://verilator.org/issues>`_.)
 
 Verilator is free software; you can redistribute it and/or modify it under

bin/verilator

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -34,11 +34,11 @@ my $opt_quiet_exit;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # Insert debugging options up front
-push @ARGV, (split ' ',$ENV{VERILATOR_TEST_FLAGS}||"");
+push @ARGV, (split ' ', $ENV{VERILATOR_TEST_FLAGS} || "");
 
 # We sneak a look at the flags so we can do some pre-environment checks
 # All flags will hit verilator...
@@ -46,7 +46,7 @@ foreach my $sw (@ARGV) {
     push @Opt_Verilator_Sw, $sw;
 }
 
-Getopt::Long::config("no_auto_abbrev","pass_through");
+Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions(
           # Major operating modes
           "help"        => \&usage,
@@ -60,7 +60,7 @@ if (! GetOptions(
           # Additional parameters
           "<>"          => sub {},      # Ignored
     )) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 if ($opt_gdbbt && !gdb_works()) {
@@ -73,12 +73,12 @@ if ($opt_gdbbt && !gdb_works()) {
 # Starting with that, escape all special chars for the shell;
 # The shell will undo the escapes and the verilator binary should
 # then see exactly the contents of @Opt_Verilator_Sw.
-my @quoted_sw = map {sh_escape($_)} @Opt_Verilator_Sw;
+my @quoted_sw = map { sh_escape($_) } @Opt_Verilator_Sw;
 if ($opt_gdb) {
     # Generic GDB interactive
     run (aslr_off()
-         .($ENV{VERILATOR_GDB}||"gdb")
-         ." ".verilator_bin()
+         . ($ENV{VERILATOR_GDB} || "gdb")
+         . " " . verilator_bin()
          # Note, uncomment to set breakpoints before running:
          #  ." -ex 'break main'"
 
@@ -87,42 +87,41 @@ if ($opt_gdb) {
          # escapes as you would expect in a double-quoted string.
          # That's not true for a single-quoted string, where \'
          # actually terminates the string -- not what we want!
-         ." -ex \"run ".join(' ', @quoted_sw)."\""
-         ." -ex 'set width 0'"
-         ." -ex 'bt'");
+         . " -ex \"run " . join(' ', @quoted_sw) . "\""
+         . " -ex 'set width 0'"
+         . " -ex 'bt'");
 } elsif ($opt_rr) {
     # Record with rr
     run (aslr_off()
-         ."rr record ".verilator_bin()
-         ." ".join(' ', @quoted_sw));
+         . "rr record " . verilator_bin()
+         . " " . join(' ', @quoted_sw));
 } elsif ($opt_gdbbt && $Debug) {
     # Run under GDB to get gdbbt
     run (aslr_off()
-         ."gdb"
-         ." ".verilator_bin()
-         ." --batch --quiet --return-child-result"
-         ." -ex \"run ".join(' ', @quoted_sw)."\""
-         ." -ex 'set width 0'"
-         ." -ex 'bt' -ex 'quit'");
+         . "gdb"
+         . " " . verilator_bin()
+         . " --batch --quiet --return-child-result"
+         . " -ex \"run " . join(' ', @quoted_sw)."\""
+         . " -ex 'set width 0'"
+         . " -ex 'bt' -ex 'quit'");
 } elsif ($Debug) {
     # Debug
-    run(aslr_off()
-        .verilator_bin()." ".join(' ',@quoted_sw));
+    run(aslr_off() . verilator_bin() . " " . join(' ', @quoted_sw));
 } else {
     # Normal, non gdb
-    run(verilator_bin()." ".join(' ',@quoted_sw));
+    run(verilator_bin() . " " . join(' ', @quoted_sw));
 }
 
 #----------------------------------------------------------------------
 
 sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
+    pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT);
 }
 
 sub debug {
     shift;
     my $level = shift;
-    $Debug = $level||3;
+    $Debug = $level || 3;
 }
 
 #######################################################################
@@ -163,13 +162,13 @@ sub verilator_bin {
 sub gdb_works {
     $! = undef;  # Cleanup -x
     system("gdb /bin/echo"
-           ." --batch-silent --quiet --return-child-result"
-           ." -ex 'run -n'"  # `echo -n`
-           ." -ex 'set width 0'"
-           ." -ex 'bt'"
-           ." -ex 'quit'");
+           . " --batch-silent --quiet --return-child-result"
+           . " -ex 'run -n'"  # `echo -n`
+           . " -ex 'set width 0'"
+           . " -ex 'bt'"
+           . " -ex 'quit'");
     my $status = $?;
-    return $status==0;
+    return $status == 0;
 }
 
 sub aslr_off {
@@ -185,7 +184,7 @@ sub run {
     # Run command, check errors
     my $command = shift;
     $! = undef;  # Cleanup -x
-    print "\t$command\n" if $Debug>=3;
+    print "\t$command\n" if $Debug >= 3;
     system($command);
     my $status = $?;
     if ($status) {
@@ -193,7 +192,7 @@ sub run {
             warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
         }
         if ($Debug) {  # For easy rerunning
-            warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
+            warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n";
             warn "%Error: $command\n";
         }
         if ($status & 127) {
@@ -201,13 +200,13 @@ sub run {
                 || ($status & 127) == 8  # SIGFPA
                 || ($status & 127) == 11) {  # SIGSEGV
                 warn "%Error: Verilator internal fault, sorry. "
-                    ."Suggest trying --debug --gdbbt\n" if !$Debug;
+                    . "Suggest trying --debug --gdbbt\n" if !$Debug;
             } elsif (($status & 127) == 6) {  # SIGABRT
                 warn "%Error: Verilator aborted. "
-                    ."Suggest trying --debug --gdbbt\n" if !$Debug;
+                    . "Suggest trying --debug --gdbbt\n" if !$Debug;
             } else {
                 warn "%Error: Verilator threw signal $status. "
-                    ."Suggest trying --debug --gdbbt\n" if !$Debug;
+                    . "Suggest trying --debug --gdbbt\n" if !$Debug;
             }
         }
         if (!$opt_quiet_exit && ($status != 256 || $Debug)) {  # i.e. not normal exit(1)
@@ -315,10 +314,12 @@ detailed descriptions of these arguments.
      -E                         Preprocess, but do not compile
     --error-limit <value>       Abort after this number of errors
     --exe                       Link to create executable
+    --expand-limit <value>      Set expand optimization limit
      -F <file>                  Parse arguments from a file, relatively
      -f <file>                  Parse arguments from a file
      -FI <file>                 Force include of a file
     --flatten                   Force inlining of all modules, tasks and functions
+     -fno-<optimization>        Disable internal optimization stage
      -G<name>=<value>           Overwrite top-level parameter
     --gdb                       Run Verilator under GDB interactively
     --gdbbt                     Run Verilator under GDB for backtrace
@@ -331,11 +332,12 @@ detailed descriptions of these arguments.
     --gate-stmts <value>        Tune gate optimizer depth
     --if-depth <value>          Tune IFDEPTH warning
      +incdir+<dir>              Directory to search for includes
-    --inhibit-sim               Create function to turn off sim
     --inline-mult <value>       Tune module inlining
+    --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
      -LDFLAGS <flags>           Linker pre-object arguments for makefile
     --l2-name <value>           Verilog scope name of the top module
     --language <lang>           Default language standard to parse
+    --lib-create <name>         Create a DPI library
      +libext+<ext>+[ext]...     Extensions for finding modules
     --lint-only                 Lint, but do not make output
      -MAKEFLAGS <flags>         Arguments to pass to make during --build
@@ -346,7 +348,7 @@ detailed descriptions of these arguments.
     --mod-prefix <topname>      Name to prepend to lower classes
     --no-clk <signal-name>      Prevent marking specified signal as clock
     --no-decoration             Disable comments and symbol decorations
-    --no-pins64                 Don't use vluint64_t's for 33-64 bit sigs
+    --no-pins64                 Don't use uint64_t's for 33-64 bit sigs
     --no-skip-identical         Disable skipping identical output
      +notimingchecks            Ignored
      -O0                        Disable optimizations
@@ -366,8 +368,10 @@ detailed descriptions of these arguments.
     --pipe-filter <command>     Filter all input through a script
     --pp-comments               Show preprocessor comments with -E
     --prefix <topname>          Name of top level class
+    --prof-c                    Compile C++ code with profiling
     --prof-cfuncs               Name functions for profiling
-    --prof-threads              Enable generating gantt chart data for threads
+    --prof-exec                 Enable generating execution profile for gantt chart
+    --prof-pgo                  Enable generating profiling data for PGO
     --protect-key <key>         Key for symbol protection
     --protect-ids               Hash identifier names for obscurity
     --protect-lib <name>        Create a DPI protected library
@@ -377,7 +381,7 @@ detailed descriptions of these arguments.
      -pvalue+<name>=<value>     Overwrite toplevel parameter
     --quiet-exit                Don't print the command on failure
     --relative-includes         Resolve includes relative to current file
-    --no-relative-cfuncs        Disallow 'this->' in generated functions
+    --reloop-limit              Minimum iterations for forming loops
     --report-unoptflat          Extra diagnostics for UNOPTFLAT
     --rr                        Run Verilator and record with rr
     --savable                   Enable model save-restore
@@ -401,7 +405,7 @@ detailed descriptions of these arguments.
     --trace-max-width <width>   Maximum array depth for tracing
     --trace-params              Enable tracing of parameters
     --trace-structs             Enable tracing structure names
-    --trace-threads <threads>   Enable waveform creation on separate threads
+    --trace-threads <threads>   Enable FST waveform creation on separate threads
     --trace-underscore          Enable tracing of _signals
      -U<var>                    Undefine preprocessor define
     --unroll-count <loops>      Tune maximum loop iterations
@@ -442,9 +446,10 @@ description of these arguments.
      +verilator+error+limit+<value>    Set error limit
      +verilator+help                   Display help
      +verilator+noassert               Disable assert checking
-     +verilator+prof+threads+file+<filename>  Set profile filename
-     +verilator+prof+threads+start+<value>    Set profile starting point
-     +verilator+prof+threads+window+<value>   Set profile duration
+     +verilator+prof+exec+file+<filename>  Set execution profile filename
+     +verilator+prof+exec+start+<value>    Set execution profile starting point
+     +verilator+prof+exec+window+<value>   Set execution profile duration
+     +verilator+prof+vlt+file+<filename>   Set PGO profile filename
      +verilator+rand+reset+<value>     Set random reset technique
      +verilator+seed+<value>           Set random seed
      +verilator+V                      Verbose version and config
@@ -455,7 +460,7 @@ description of these arguments.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.

bin/verilator_ccache_report

@@ -0,0 +1,94 @@
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0301,R0902,R0913,R0914,R0912,R0915,W0621
+######################################################################
+
+import argparse
+import collections
+import pathlib
+import re
+
+from datetime import datetime
+
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Report ccache behavior of a Verilated model build.""",
+    epilog=
+    """Copyright 2002-2022 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+
+parser.add_argument('-o',
+                    type=argparse.FileType('w'),
+                    metavar="OUTFILE",
+                    required=True,
+                    help='output file')
+parser.add_argument('logdir', type=pathlib.Path, help='log directory')
+
+args = parser.parse_args()
+
+results = {}
+elapsed = {}
+
+
+def toDateTime(s):
+    return datetime.strptime(s, "%Y-%m-%dT%H:%M:%S.%f")
+
+
+for logfile in args.logdir.iterdir():
+    with logfile.open() as fh:
+        start = None
+        obj = None
+        for line in fh:
+            line = line.strip()
+            match = re.match(r'\[(\S+)\s.*Object file: (.*)$', line)
+            if match:
+                start = toDateTime(match.group(1))
+                obj = match.group(2)
+            match = re.match(r'\[(\S+)\s.*Result: (.*)$', line)
+            if match:
+                assert obj is not None
+                elapsed[obj] = toDateTime(match.group(1)) - start
+                results[obj] = match.group(2)
+
+args.o.write("#" * 80 + "\n")
+args.o.write("ccache report (from verilator_ccache_report) :\n")
+
+if not results:
+    args.o.write("\nAll object files up to date\n")
+else:
+    args.o.write("\nCompiled object files:\n")
+    wnames = max(len(_) for _ in results) + 1
+    wresults = max(len(_) for _ in results.values()) + 1
+    for k in sorted(results.keys()):
+        args.o.write("{:{wnames}} : {:{wresults}} : {}s\n".format(
+            k,
+            results[k],
+            elapsed[k].total_seconds(),
+            wnames=wnames,
+            wresults=wresults))
+
+    args.o.write("\nSummary:\n")
+    counts = collections.Counter(_ for _ in results.values())
+    total = sum(counts.values())
+    for k in sorted(counts.keys()):
+        c = counts[k]
+        args.o.write("{:{width}}| {} ({:.2%})\n".format(k,
+                                                        c,
+                                                        c / total,
+                                                        width=wresults))
+
+    args.o.write("\nLongest:\n")
+    longest = sorted(list(elapsed.items()),
+                     key=lambda kv: -kv[1].total_seconds())
+    for i, (k, v) in enumerate(longest):
+        args.o.write("{:{width}}| {}s\n".format(k,
+                                                v.total_seconds(),
+                                                width=wnames))
+        if i > 4:
+            break
+
+args.o.write("#" * 80 + "\n")

bin/verilator_coverage

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -30,7 +30,7 @@ $Debug = 0;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # We sneak a look at the flags so we can do some pre-environment checks
@@ -40,7 +40,7 @@ foreach my $sw (@ARGV) {
     push @Opt_Verilator_Sw, $sw;
 }
 
-Getopt::Long::config("no_auto_abbrev","pass_through");
+Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions (
           # Major operating modes
           "help"        => \&usage,
@@ -49,23 +49,23 @@ if (! GetOptions (
           # Additional parameters
           "<>"          => sub {},      # Ignored
     )) {
-    pod2usage(-exitstatus=>2, -verbose=>0);
+    pod2usage(-exitstatus => 2, -verbose => 0);
 }
 
 # Normal, non gdb
 run(verilator_coverage_bin()
-    ." ".join(' ',@Opt_Verilator_Sw));
+    . " " . join(' ', @Opt_Verilator_Sw));
 
 #----------------------------------------------------------------------
 
 sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
+    pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT);
 }
 
 sub debug {
     shift;
     my $level = shift;
-    $Debug = $level||3;
+    $Debug = $level || 3;
 }
 
 #######################################################################
@@ -107,7 +107,7 @@ sub run {
     # Run command, check errors
     my $command = shift;
     $! = undef;  # Cleanup -x
-    print "\t$command\n" if $Debug>=3;
+    print "\t$command\n" if $Debug >= 3;
     system($command);
     my $status = $?;
     if ($status) {
@@ -115,11 +115,11 @@ sub run {
             warn "%Error: verilator_coverage: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
         }
         if ($Debug) {  # For easy rerunning
-            warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
+            warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n";
             warn "%Error: $command\n";
         }
         if ($status & 127) {
-            if (($status & 127) == 8 || ($status & 127) == 11) { # SIGFPA or SIGSEGV
+            if (($status & 127) == 8 || ($status & 127) == 11) {  # SIGFPA or SIGSEGV
                 warn "%Error: Verilator_coverage internal fault, sorry.\n" if !$Debug;
             } elsif (($status & 127) == 6) {  # SIGABRT
                 warn "%Error: Verilator_coverage aborted.\n" if !$Debug;
@@ -187,7 +187,7 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

bin/verilator_difftree

@@ -1,233 +1,139 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116
 ######################################################################
 
-use warnings;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-use strict;
-use vars qw($Debug);
+import argparse
+import collections
+import glob
+import os.path
+import re
+import sys
 
-#======================================================================
-# main
 
-$Debug = 0;
-my $Opt_A;
-my $Opt_B;
-my $Opt_Lineno = 1;
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          "<>"          => \&parameter,
-          "lineno!"     => \$Opt_Lineno,
-    )) {
-    die "%Error: Bad usage, try 'verilator_difftree --help'\n";
-}
+def diff(a, b):
 
-defined $Opt_A or die "%Error: No old diff filename\n";
-defined $Opt_B or die "%Error: No new diff filename\n";
+    if not os.path.exists(a):
+        sys.exit("%Error: No old diff filename found: " + a)
+    if not os.path.exists(b):
+        sys.exit("%Error: No new diff filename found: " + b)
 
--e $Opt_A or die "%Error: No old diff filename found: $Opt_A\n";
--e $Opt_B or die "%Error: No new diff filename found: $Opt_B\n";
+    if os.path.isdir(a) and os.path.isdir(b):
+        diff_dir(a, b)
+    elif os.path.isfile(a) and os.path.isfile(b):
+        diff_file(a, b)
+    else:
+        sys.exit("%Error: Mix of files and dirs")
 
-if (-d $Opt_A && -d $Opt_B) {
-    diff_dir($Opt_A, $Opt_B);
-} elsif (-f $Opt_A && -f $Opt_B) {
-    diff_file($Opt_A, $Opt_B);
-} else {
-    die "%Error: Mix of files and dirs\n";
-}
 
-sub diff_dir {
-    my $a = shift;
-    my $b = shift;
+def diff_dir(a, b):
     # Diff all files under two directories
-    my %files;
+    files = collections.defaultdict(lambda: {})
 
-    foreach my $fn (glob("$a/*.tree")) {
-        (my $base = $fn) =~ s!.*/!!;
-        $files{$base}{a} = $fn;
-    }
-    foreach my $fn (glob("$b/*.tree")) {
-        (my $base = $fn) =~ s!.*/!!;
-        $files{$base}{b} = $fn;
-    }
-    my $any;
-    foreach my $base (sort (keys %files)) {
-        my $a = $files{$base}{a};
-        my $b = $files{$base}{b};
-        next if !$a || !$b;
-        print "="x70,"\n";
-        print "= $a <-> $b\n";
-        diff_file($a,$b);
-        $any = 1;
-    }
-    $any or warn("%Warning: No .tree files found that have similar base names:\n    "
-                 .join("\n    ", sort keys %files),"\n");
-}
+    for fn in glob.glob(a + "/*.tree"):
+        base = re.sub(r'.*/', '', fn)
+        files[base]['a'] = fn
+    for fn in glob.glob(b + "/*.tree"):
+        base = re.sub(r'.*/', '', fn)
+        files[base]['b'] = fn
 
-sub diff_file {
-    my $a = shift;
-    my $b = shift;
+    anyfile = False
+    for base in sorted(files.keys()):
+        if (not 'a' in files[base]) or (not 'b' in files[base]):
+            continue
+        a = files[base]['a']
+        b = files[base]['b']
+        print("=" * 70)
+        print("= %s <-> %s" % (a, b))
+        diff_file(a, b)
+        anyfile = True
+    if not anyfile:
+        sys.stderr.write(
+            "%Warning: No .tree files found that have similar base names\n")
+
+
+def diff_file(a, b):
     # Compare the two tree files
-    (my $short_a = $a) =~ s/[^a-zA-Z0-9.]+/_/g;
-    (my $short_b = $b) =~ s/[^a-zA-Z0-9.]+/_/g;
-    my $tmp_a = "/tmp/${$}_${short_a}.a";
-    my $tmp_b = "/tmp/${$}_${short_b}.b";
+    short_a = re.sub(r'[^a-zA-Z0-9.]+', '_', a)
+    short_b = re.sub(r'[^a-zA-Z0-9.]+', '_', b)
+    tmp_a = "/tmp/%s_%s.a" % (os.getpid(), short_a)
+    tmp_b = "/tmp/%s_%s.b" % (os.getpid(), short_b)
 
-    my $vera = version_from($a);
-    my $verb = version_from($b);
-    my $verCvt = (($vera < 0x3900 && $verb >= 0x3900)
-                  || ($vera >= 0x3900 && $verb < 0x3900));
+    # Version conversion deprecated, but for future...
+    # vera = version_from(a)
+    # verb = version_from(b)
+    # verCvt = ((vera < 0x3900 and verb >= 0x3900)
+    #            or (vera >= 0x3900 and verb < 0x3900))
 
-    filter($a, $tmp_a, $verCvt);
-    filter($b, $tmp_b, $verCvt);
-    system("diff -u $tmp_a $tmp_b");
-    unlink $tmp_a;
-    unlink $tmp_b;
-}
+    filterf(a, tmp_a)
+    filterf(b, tmp_b)
+    os.system("diff -u " + tmp_a + " " + tmp_b)
+    os.unlink(tmp_a)
+    os.unlink(tmp_b)
 
-sub version_from {
-    my $fn = shift;
+
+def version_from(filename):
     # Return dump format
-    my $f1 = IO::File->new ($fn) or die "%Error: $! $fn,";
-    while (defined (my $line=$f1->getline())) {
-        last if $. > 10;
-        return hex $1 if $line =~ /\(format (0x[0-9.]+)\)/;
-    }
-    return 1.0;
-}
+    with open(filename) as fh:
+        lineno = 0
+        for line in fh:
+            if lineno > 10:
+                break
+            match = re.search(r'format (0x[0-9.]+)', line)
+            if match:
+                return hex(match.group(1))
+    return 1.0
 
-sub filter {
-    my $fn1 = shift;
-    my $fn2 = shift;
-    my $verCvt = shift;
+
+def filterf(fn1, fn2):
     # Remove hex numbers before diffing
-    my $f1 = IO::File->new ($fn1) or die "%Error: $! $fn1,";
-    my $f2 = IO::File->new ($fn2,"w") or die "%Error: $! $fn2,";
-    while (defined (my $line=$f1->getline())) {
-      same_line:
-        next if $line =~ / This=/;
-        $line =~ s/0x[a-f0-9]+/0x/g;
-        $line =~ s/<e[0-9]+\#?>/<e>/g;
-        $line =~ s/{[a-z]*\d+}/{}/g if !$Opt_Lineno;
-        if ($verCvt) {
-            next if $line =~ /^     NETLIST/;
-            if ($line =~ /: ([A-Z]+) /) {
-                my $type = $1;
-                next if $type =~ 'DTYPE';
-                if ($type eq 'TYPETABLE' || $type eq 'RANGE') {
-                    $line =~ /^(\s+\S+:) /; my $prefix = $1;
-                    while (defined ($line=$f1->getline())) {
-                        next if $line =~ /^\s+[a-z]/;  # Table body
-                        next if $line =~ /^${prefix}[0-9]:/;
-                        goto same_line;
-                    }
-                    next;
-                }
-            }
-        }
-        print $f2 $line;
-    }
-    $f1->close;
-    $f2->close;
-}
+    with open(fn1) as fh1:
+        with open(fn2, "w") as fh2:
+            for line in fh1:
+                if re.search(r' This=', line):
+                    continue
+                line = re.sub(r'0x[a-f0-9]+', '0x', line)
+                line = re.sub(r'<e[0-9]+\#?>', '<e>', line)
+                if not Args.no_lineno:
+                    line = re.sub(r'{[a-z]*\d+}', '{}', line)
+                fh2.write(line)
 
-#----------------------------------------------------------------------
 
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
+######################################################################
+######################################################################
 
-sub debug {
-    $Debug = 1;
-}
-
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_A) {
-        $Opt_A = $param;
-    } elsif (!defined $Opt_B) {
-        $Opt_B = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
-
-#######################################################################
-
-sub run {
-    # Run a system command, check errors
-    my $command = shift;
-    print "\t$command\n";
-    system "$command";
-    my $status = $?;
-    ($status == 0) or die "%Error: Command Failed $command, $status, stopped";
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_difftree - Compare two Verilator debugging trees
-
-=head1 SYNOPSIS
-
-  verilator_difftree .../a/a.tree  .../b/a.tree
-  verilator_difftree .../a         .../b
-
-=head1 DESCRIPTION
-
-Verilator_difftree is used for debugging Verilator tree output files.  It
-performs a diff between two files, or all files common between two
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Compare two Verilator debugging trees""",
+    epilog=
+    """Verilator_difftree is used for debugging Verilator tree output files.
+It performs a diff between two files, or all files common between two
 directories, ignoring irrelevant pointer differences.
 
-=head1 ARGUMENTS
+For documentation see
+https://verilator.org/guide/latest/exe_verilator_difftree.html
 
-=over 4
-
-=item --help
-
-Displays this message and program version and exits.
-
-=item --nolineno
-
-Do not show differences in line numbering.
-
-=back
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2005-2021 by Wilson Snyder. This program is free software; you
+Copyright 2005-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 AUTHORS
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('--no-lineno',
+                    action='store_false',
+                    help='do not show differences in line numbering')
+parser.add_argument('filea', help='input file a to diff')
+parser.add_argument('fileb', help='input file b to diff')
 
-Wilson Snyder <[email protected]>
-
-=head1 SEE ALSO
-
-C<verilator>
-
-and L<https://verilator.org/verilator_doc.html> for detailed documentation.
-
-=cut
+Args = parser.parse_args()
+diff(Args.filea, Args.fileb)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_difftree  {$V4D,$V4}/test_regress/obj_dir/t_EXAMPLE/V*_03_*.tree"
-### End:
+# Local Variables:
+# compile-command: "./verilator_difftree ../test_regress/t/t_difftree.{a,b}.tree"
+# End:

bin/verilator_includer

@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 # DESCRIPTION: Print include statements for each ARGV
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,11 +10,11 @@
 
 require 5.005;
 use warnings;
-print "// DESCR"."IPTION: Generated by verilator_includer via makefile\n";
+print "// DESCR" . "IPTION: Generated by verilator_includer via makefile\n";
 foreach my $param (@ARGV) {
     if ($param =~ /^-D([^=]+)=(.*)/) {
-        print "#define $1 $2\n"
+        print "#define $1 $2\n";
     } else {
-        print "#include \"$param\"\n"
+        print "#include \"$param\"\n";
     }
 }

bin/verilator_profcfunc

@@ -1,248 +1,204 @@
-#!/usr/bin/env perl
-# See copyright, etc in below POD section.
+#!/usr/bin/env python3
+# pylint: disable=C0103,C0114,C0116,R0914,R0912,R0915,eval-used
 ######################################################################
 
-require 5.006_001;
-use warnings;
-use Getopt::Long;
-use IO::File;
-use Pod::Usage;
-eval { use Data::Dumper;  $Data::Dumper::Indent = 1; }; # Debug, ok if missing
-use strict;
-use vars qw($Debug);
+import argparse
+import collections
+import re
+# from pprint import pprint
 
-#======================================================================
+######################################################################
 
 
-#======================================================================
-# main
+def profcfunc(filename):
+    funcs = {}
 
-$Debug = 0;
-my $Opt_File;
-autoflush STDOUT 1;
-autoflush STDERR 1;
-Getopt::Long::config("no_auto_abbrev");
-if (! GetOptions(
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          "<>"          => \&parameter,
-    )) {
-    die "%Error: Bad usage, try 'verilator_profcfunc --help'\n";
-}
+    with open(filename) as fh:
 
-defined $Opt_File or die "%Error: No filename given\n";
+        for line in fh:
+            #                  %time      cumesec   selfsec     calls     {stuff}   name
+            match = re.match(
+                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                line)
+            if match:
+                pct = float(match.group(1))
+                sec = float(match.group(2))
+                calls = float(match.group(3))
+                func = match.group(4)
+                if func not in funcs:
+                    funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
+                funcs[func]['pct'] += pct
+                funcs[func]['sec'] += sec
+                funcs[func]['calls'] += calls
+                continue
 
-profcfunc($Opt_File);
-
-#----------------------------------------------------------------------
-
-sub usage {
-    pod2usage(-verbose=>2, -exitval=>0, -output=>\*STDOUT);
-    exit(1);  # Unreachable
-}
-
-sub debug {
-    $Debug = 1;
-}
-
-sub parameter {
-    my $param = shift;
-    if (!defined $Opt_File) {
-        $Opt_File = $param;
-    } else {
-        die "%Error: Unknown parameter: $param\n";
-    }
-}
-
-#######################################################################
-
-sub profcfunc {
-    my $filename = shift;
-    # Remove hex numbers before diffing
-    my $fh = IO::File->new ($filename) or die "%Error: $! $filename,";
-
-    my %funcs;
-
-    while (defined (my $line=$fh->getline())) {
-        #                  %time      cumesec   selfsec     calls     {stuff}   name
-        if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
-            my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
-            $funcs{$func}{pct} += $pct;
-            $funcs{$func}{sec} += $sec;
-            $funcs{$func}{calls} += $calls;
-        }
-        # Older gprofs have no call column for single-call functions
-        #                  %time      cumesec   selfsec      {stuff}   name
-        elsif ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$/) {
-            my $pct=$1; my $sec=$2; my $calls=1; my $func=$3;
-            $funcs{$func}{pct} += $pct;
-            $funcs{$func}{sec} += $sec;
-            $funcs{$func}{calls} += $calls;
-        }
-    }
-    $fh->close;
+            # Older gprofs have no call column for single-call functions
+            #                  %time      cumesec   selfsec      {stuff}   name
+            match = re.match(
+                r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
+                line)
+            if match:
+                pct = float(match.group(1))
+                sec = float(match.group(2))
+                calls = 1
+                func = match.group(3)
+                if func not in funcs:
+                    funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
+                funcs[func]['pct'] += pct
+                funcs[func]['sec'] += sec
+                funcs[func]['calls'] += calls
+                continue
 
     # Find modules
-    my %pointer_mods;
-    my %verilated_mods;
-    foreach my $func (keys %funcs) {
-        if ($func =~ /(.*)::_eval\(([a-zA-Z_0-9]+__Syms).*\)$/) {
-            $verilated_mods{$1} = qr/^$1/;
-            $pointer_mods{$2} = $1;
-        }
-    }
-    #print Dumper(\%pointer_mods, \%verilated_mods);
+    verilated_mods = {}
+    for func in funcs:
+        match = re.search(r'(.*)::eval(_step)?\(', func)
+        if match:
+            prefix = match.group(1)
+            if Args.debug:
+                print("-got _eval %s   prefix=%s" % (func, prefix))
+            verilated_mods[prefix] = re.compile(r'^' + prefix)
+    # pprint(verilated_mods)
 
-    # Resort by Verilog name
-    my %vfuncs;
-    my %groups;
-    foreach my $func (keys %funcs) {
-        my $pct = $funcs{$func}{pct};
-        my $vfunc = $func;
-        my $design;
+    # Sort by Verilog name
+    vfuncs = {}
+    groups = {}
+    groups['type'] = collections.defaultdict(lambda: 0)
+    groups['design'] = collections.defaultdict(lambda: 0)
+    groups['module'] = collections.defaultdict(lambda: 0)
 
-        if ($func =~ /\(([a-zA-Z_0-9]+__Syms)/) {
-            $design = $pointer_mods{$1};
-        }
+    for func in funcs:
+        pct = funcs[func]['pct']
+        vfunc = func
 
-        foreach my $vde (keys %verilated_mods) {
-            last if $design;
-            if ($func =~ /$verilated_mods{$vde}/) {
-                $design=$vde;
-                last;
-            }
-        }
+        funcarg = re.sub(r'^.*\(', '', func)
 
-        if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(/) {
-            $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
-            $groups{type}{"Verilog Blocks under $design"} += $pct;
-            $groups{design}{$design} += $pct;
-            $groups{module}{$1} += $pct;
-        } else {
-            if ($design) {
-                $vfunc = sprintf("VCommon   %s", $func);
-                $groups{type}{"Common code under $design"} += $pct;
-                $groups{design}{$design} += $pct;
-                $groups{module}{$design." common code"} += $pct;
-            } elsif ($func =~ /^VL_[A-Z0-9_]+/
-                     || $func =~ /^_?vl_[a-zA-Z0-9_]+/
-                     || $func =~ /^verilated/i) {
-                $vfunc = sprintf("VLib      %s", $func);
-                $groups{type}{'VLib'} += $pct;
-                $groups{design}{'VLib'} += $pct;
-                $groups{module}{'VLib'} += $pct;
-            } elsif ($func =~ /^_mcount_private/) {
-                $vfunc = sprintf("Prof      %s", $func);
-                $groups{type}{'Prof'} += $pct;
-                $groups{design}{'Prof'} += $pct;
-                $groups{module}{'Prof'} += $pct;
-            } else {
-                $vfunc = sprintf("C++       %s", $func);
-                $groups{type}{'C++'} += $pct;
-                $groups{design}{'C++'} += $pct;
-                $groups{module}{'C++'} += $pct;
-            }
-        }
-        $vfuncs{$vfunc} = $funcs{$func};
-    }
+        design = None
+        for vde in verilated_mods:
+            if verilated_mods[vde].match(func) or verilated_mods[vde].match(
+                    funcarg):
+                design = vde
+                break
+
+        vdesign = "-"
+
+        prof_match = re.search(r'__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(', vfunc)
+        if design and prof_match:
+            linefunc = prof_match.group(1)
+            lineno = int(prof_match.group(2))
+            vfunc = "VBlock    %s:%d" % (linefunc, lineno)
+            vdesign = design
+            groups['type']["Verilog Blocks under " + design] += pct
+            groups['design'][design] += pct
+            groups['module'][linefunc] += pct
+        elif design:
+            vfunc = "VCommon   " + func
+            vdesign = design
+            groups['type']["Common code under " + design] += pct
+            groups['design'][design] += pct
+            groups['module'][design + " common code"] += pct
+        elif re.match(r'(VL_[A-Z0-9_]+|_?vl_[a-zA-Z0-9_]+|Verilated)', vfunc):
+            vfunc = "VLib      " + func
+            groups['type']['VLib'] += pct
+            groups['design']['VLib'] += pct
+            groups['module']['VLib'] += pct
+        elif re.match(r'^_mcount_private', vfunc):
+            vfunc = "Prof      " + func
+            groups['type']['Prof'] += pct
+            groups['design']['Prof'] += pct
+            groups['module']['Prof'] += pct
+        else:
+            vfunc = "C++       " + func
+            groups['type']['C++'] += pct
+            groups['design']['C++'] += pct
+            groups['module']['C++'] += pct
+
+        if vfunc not in vfuncs:
+            vfuncs[vfunc] = funcs[func]
+            vfuncs[vfunc]['design'] = vdesign
+        else:
+            vfuncs[vfunc]['pct'] += funcs[func]['pct']
+            vfuncs[vfunc]['calls'] += funcs[func]['calls']
+            vfuncs[vfunc]['sec'] += funcs[func]['sec']
+
+    for ftype in ['type', 'design', 'module']:
+        missing = 100
+        for item in groups[ftype].keys():
+            missing -= groups[ftype][item]
+        groups[ftype]["\377Unaccounted for/rounding error"] = missing
+
+        print("Overall summary by %s:" % ftype)
+        print("  %-6s  %s" % ("% time", ftype))
+        for what in sorted(groups[ftype].keys()):
+            # \377 used to establish sort order
+            pwhat = re.sub(r'^\377', '', what)
+            print("  %6.2f  %s" % (groups[ftype][what], pwhat))
+        print()
+
+    design_width = 1
+    for func in vfuncs:
+        if design_width < len(vfuncs[func]['design']):
+            design_width = len(vfuncs[func]['design'])
+
+    print("Verilog code profile:")
+    print("   These are split into three categories:")
+    print("      C++:     Time in non-Verilated C++ code")
+    print("      Prof:    Time in profile overhead")
+    print("      VBlock:  Time attributable to a block in a" +
+          " Verilog file and line")
+    print("      VCommon: Time in a Verilated module," +
+          " due to all parts of the design")
+    print("      VLib:    Time in Verilated common libraries," +
+          " called by the Verilated code")
+    print()
+
+    print("  %   cumulative   self              ")
+    print((" time   seconds   seconds      calls   %-" + str(design_width) +
+           "s  type      filename and line number") % "design")
+
+    cume = 0
+    for func in sorted(vfuncs.keys(),
+                       key=lambda f: vfuncs[f]['sec'],
+                       reverse=True):
+        cume += vfuncs[func]['sec']
+        print(("%6.2f %9.2f %8.2f %10d   %-" + str(design_width) + "s  %s") %
+              (vfuncs[func]['pct'], cume, vfuncs[func]['sec'],
+               vfuncs[func]['calls'], vfuncs[func]['design'], func))
 
 
-    foreach my $type (qw(type design module)) {
-        my $missing = 100;
-        foreach (sort (keys %{$groups{$type}})) {
-            $missing -= $groups{$type}{$_};
-        }
-        if ($missing) {
-            $groups{$type}{"\377Unaccounted for/rounding error"} = $missing;
-        }
+######################################################################
+######################################################################
 
-        print("Overall summary by $type:\n");
-        printf("  %-6s  %s\n","% time",$type);
-        foreach my $what (sort (keys %{$groups{$type}})) {
-            (my $pwhat = $what) =~ s/^\377//;  # Just used to establish sort order
-            printf("  %6.2f  %s\n", $groups{$type}{$what}, $pwhat);
-        }
-        print("\n");
-    }
-
-    print("Verilog code profile:\n");
-    print("   These are split into three categories:\n");
-    print("      C++:     Time in non-Verilated C++ code\n");
-    print("      Prof:    Time in profile overhead\n");
-    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
-    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
-    print("      VLib:    Time in Verilated common libraries, called by the Verilated code\n");
-    print("\n");
-
-    print("  %   cumulative   self              \n");
-    print(" time   seconds   seconds    calls   type      filename and line number\n");
-
-    my $cume = 0;
-    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
-                            || $a cmp $b}
-                      (keys %vfuncs)) {
-        $cume += $vfuncs{$func}{sec};
-        printf +("%6.2f %9.2f %8.2f %8d   %s\n",
-                 $vfuncs{$func}{pct},
-                 $cume, $vfuncs{$func}{sec},
-                 $vfuncs{$func}{calls},
-                 $func);
-    }
-}
-
-#######################################################################
-__END__
-
-=pod
-
-=head1 NAME
-
-verilator_profcfunc - Read gprof report created with --prof-cfuncs
-
-=head1 SYNOPSIS
-
-  verilator --prof-cfuncs ....
-  gcc --ggdb -pg ....
-  {run executable}
-  gprof
-  verilator_profcfuncs gprof.out
-
-=head1 DESCRIPTION
-
-Verilator_profcfunc reads a profile report created by gprof.  The names of
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""Read gprof report created with --prof-cfuncs""",
+    epilog=
+    """Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of time, etc,
 in each Verilog block.
 
 For documentation see
-L<https://verilator.org/guide/latest/exe_verilator_profcfuncs.html>.
+https://verilator.org/guide/latest/exe_verilator_profcfunc.html
 
-=head1 ARGUMENT SUMMARY
-
-    <filename>  Input file (gprof.out)
-    --help      Display this help
-
-=head1 DISTRIBUTION
-
-The latest version is available from L<https://verilator.org>.
-
-Copyright 2007-2021 by Wilson Snyder. This program is free software; you
+Copyright 2002-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
 
-SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
 
-=head1 SEE ALSO
+parser.add_argument('--debug',
+                    action='store_const',
+                    const=9,
+                    help='enable debug')
+parser.add_argument('filename', help='input gprof output to process')
 
-C<verilator>
-
-and L<https://verilator.org/guide/latest/exe_verilator_profcfuncs.html> for
-detailed documentation.
-
-=cut
+Args = parser.parse_args()
+profcfunc(Args.filename)
 
 ######################################################################
-### Local Variables:
-### compile-command: "$V4/bin/verilator_profcfunc  $V4/test_c/obj_dir/V*_03_*.tree $V4N/test_c/obj_dir/V*_03_*.tree"
-### End:
+# Local Variables:
+# compile-command: "./verilator_profcfunc ../test_regress/t/t_profcfunc.gprof"
+# End:

ci/ci-install.bash

@@ -23,6 +23,12 @@ fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
+if [ "$CI_M32" = "0" ]; then
+  unset CI_M32
+elif [ "$CI_M32" != "1" ]; then
+  fatal "\$CI_M32 must be '0' or '1'";
+fi
+
 if [ "$CI_OS_NAME" = "linux" ]; then
   MAKE=make
 elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -36,7 +42,7 @@ fi
 install-vcddiff() {
   TMP_DIR="$(mktemp -d)"
   git clone https://github.com/veripool/vcddiff "$TMP_DIR"
-  git -C "${TMP_DIR}" checkout 5112f88b7ba8818dce9dfb72619e64a1fc19542c
+  git -C "${TMP_DIR}" checkout e5664be5fe39d353bf3fcb50aa05214ab7ed4ac4
   "$MAKE" -C "${TMP_DIR}"
   sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin
 }
@@ -48,14 +54,18 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
 
   if [ "$CI_OS_NAME" = "linux" ]; then
     sudo apt-get update
-    sudo apt-get install libfl-dev libgoogle-perftools-dev ccache
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
+    sudo apt-get install libfl-dev ccache
+    if [ "$CI_RUNS_ON" != "ubuntu-22.04" ]; then
+      # Some conflict of libunwind verison on 22.04, can live without it for now
+      sudo apt-get install libgoogle-perftools-dev
+    fi
+    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
       sudo apt-get install libsystemc libsystemc-dev
     fi
     if [ "$COVERAGE" = 1 ]; then
       yes yes | sudo cpan -fi Parallel::Forker
     fi
-    if [ "$M32" = 1 ]; then
+    if [ "$CI_M32" = 1 ]; then
       sudo apt-get install gcc-multilib g++-multilib
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -79,10 +89,10 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     sudo apt-get update
     # libfl-dev needed for internal coverage's test runs
     sudo apt-get install gdb gtkwave lcov libfl-dev ccache
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
+    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
       sudo apt-get install libsystemc-dev
     fi
-    if [ "$M32" = 1 ]; then
+    if [ "$CI_M32" = 1 ]; then
       sudo apt-get install lib32z1-dev gcc-multilib g++-multilib
     fi
   elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -101,9 +111,6 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
   fi
   yes yes | sudo cpan -M $CI_CPAN_REPO -fi Parallel::Forker
   install-vcddiff
-
-  autoconf
-  ./configure --enable-longtests --enable-ccwarn
 else
   ##############################################################################
   # Unknown build stage

ci/ci-script.bash

@@ -21,6 +21,12 @@ fatal() {
   echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
 
+if [ "$CI_M32" = "0" ]; then
+  unset CI_M32
+elif [ "$CI_M32" != "1" ]; then
+  fatal "\$CI_M32 must be '0' or '1'";
+fi
+
 if [ "$CI_OS_NAME" = "linux" ]; then
   export MAKE=make
   NPROC=$(nproc)
@@ -40,8 +46,10 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
 
   if [ "$COVERAGE" != 1 ]; then
     autoconf
-    ./configure --enable-longtests --enable-ccwarn
+    ./configure --enable-longtests --enable-ccwarn ${CI_M32:+--enable-m32}
+    ccache -z
     "$MAKE" -j "$NPROC" -k
+    ccache -s
     if [ "$CI_OS_NAME" = "osx" ]; then
       file bin/verilator_bin
       file bin/verilator_bin_dbg
@@ -61,6 +69,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
 
   if [ "$CI_OS_NAME" = "osx" ]; then
     export VERILATOR_TEST_NO_GDB=1  # Pain to get GDB to work on OS X
+    # TODO below may no longer be requried as configure checks for -pg
     export VERILATOR_TEST_NO_GPROF=1  # Apple Clang has no -pg
     # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd
     file bin/verilator_bin
@@ -76,19 +85,24 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
     "$MAKE" -j "$NPROC" -k
   elif [ "$CI_OS_NAME" = "freebsd" ]; then
     export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run
+    # TODO below may no longer be requried as configure checks for -pg
     export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable
   fi
 
   # Run sanitize on Ubuntu 20.04 only
-  [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && sanitize='--sanitize' || sanitize=''
+  [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && [ "$CI_M32" = "" ] && sanitize='--sanitize' || sanitize=''
 
   # Run the specified test
+  ccache -z
   case $TESTS in
     dist-vlt-0)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=0/2
+      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=0/3
       ;;
     dist-vlt-1)
-      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=1/2
+      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=1/3
+      ;;
+    dist-vlt-2)
+      "$MAKE" -C test_regress SCENARIOS="--dist --vlt $sanitize" DRIVER_HASHSET=--hashset=2/3
       ;;
     vltmt-0)
       "$MAKE" -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=0/2
@@ -166,6 +180,8 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
       fatal "Unknown test: $TESTS"
       ;;
   esac
+  ccache -s
+
   # Upload coverage data
   if [[ $TESTS == coverage-* ]]; then
     bash <(cat ci/coverage-upload.sh) -f nodist/obj_dir/coverage/app_total.info

codecov.yml

@@ -1,6 +1,6 @@
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2020-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.

configure.ac

@@ -1,20 +1,20 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you
+# Copyright 2003-2022 by Wilson Snyder. Verilator is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[4.202 2021-04-24],
+AC_INIT([Verilator],[4.224 2022-06-19],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 # When releasing, also update header of Changes file
 # and commit using "devel release" or "Version bump" message
 # Then 'make maintainer-dist'
 
-AC_CONFIG_HEADER(src/config_build.h)
+AC_CONFIG_HEADERS(src/config_build.h)
 AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)
 
 # Version
@@ -22,6 +22,8 @@ AC_MSG_RESULT([configuring for $PACKAGE_STRING])
 PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'`
 AC_SUBST(PACKAGE_VERSION_NUMBER)
 AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number])
+VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']`
+AC_SUBST(VERILATOR_VERSION_INTEGER)
 
 # Ignore automake flags passed by Ubuntu builds
 AC_ARG_ENABLE([dependency-tracking],
@@ -35,7 +37,7 @@ AC_ARG_ENABLE([silent-rules],
 AC_MSG_CHECKING(whether to perform partial static linking of Verilator binary)
 AC_ARG_ENABLE([partial-static],
               [AS_HELP_STRING([--disable-partial-static],
-                              [By default, for Verilation peformance, Verilator
+                              [By default, for Verilation performance, Verilator
                                is linked against some of its dependencies
                                statically. Use this to link the Verilator binary
                                fully dynamically.])],
@@ -52,7 +54,7 @@ AC_MSG_CHECKING(whether to use tcmalloc)
 AC_ARG_ENABLE([tcmalloc],
               [AS_HELP_STRING([--enable-tcmalloc],
                               [Use libtcmalloc_minimal for faster dynamic memory
-                               management in Verilator binary@<:@default=check@:>@])],
+                               management in Verilator binary @<:@default=check@:>@])],
               [case "${enableval}" in
                 yes) CFG_WITH_TCMALLOC=yes ;;
                 no)  CFG_WITH_TCMALLOC=no ;;
@@ -61,6 +63,34 @@ AC_ARG_ENABLE([tcmalloc],
               [CFG_WITH_TCMALLOC=check;])
 AC_MSG_RESULT($CFG_WITH_TCMALLOC)
 
+# Flag to enable -m32 build
+AC_MSG_CHECKING(whether to use -m32)
+AC_ARG_ENABLE([m32],
+              [AS_HELP_STRING([--enable-m32],
+                              [Use -m32 for all compilation and link,
+                               including Verialtor and generated models.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_M32=yes ;;
+                no)  CFG_ENABLE_M32=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-m32]) ;;
+               esac],
+               CFG_ENABLE_M32=no)
+AC_MSG_RESULT($CFG_ENABLE_M32)
+
+# Flag to enable coverage build
+AC_MSG_CHECKING(whether to build for coverage collection)
+AC_ARG_ENABLE([coverage],
+              [AS_HELP_STRING([--enable-coverage],
+                              [Build Verilator for code coverage collection.
+                               For developers only.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_COVERAGE=yes ;;
+                no)  CFG_ENABLE_COVERAGE=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-coverage]) ;;
+               esac],
+               CFG_ENABLE_COVERAGE=no)
+AC_MSG_RESULT($CFG_ENABLE_COVERAGE)
+
 # Special Substitutions - CFG_WITH_DEFENV
 AC_MSG_CHECKING(whether to use hardcoded paths)
 AC_ARG_ENABLE([defenv],
@@ -115,10 +145,10 @@ AC_SUBST(CFG_WITH_LONGTESTS)
 AC_MSG_RESULT($CFG_WITH_LONGTESTS)
 
 # Compiler flags (ensure they are not empty to avoid configure defaults)
-CFLAGS+=" "
-CPPFLAGS+=" "
-CXXFLAGS+=" "
-LDFLAGS+=" "
+CFLAGS="$CFLAGS "
+CPPFLAGS="$CPPFLAGS "
+CXXFLAGS="$CXXFLAGS "
+LDFLAGS="$LDFLAGS "
 
 # Checks for programs.
 AC_PROG_CC
@@ -135,6 +165,11 @@ AC_RUN_IFELSE(
     AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]),
     AC_MSG_RESULT(yes))
 
+AC_CHECK_PROG(AR,ar,ar)
+if test "x$AR" = "x" ; then
+   AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it])
+fi
+
 AC_PATH_PROG(PERL,perl)
 if test "x$PERL" = "x" ; then
    AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])
@@ -211,24 +246,34 @@ AC_DEFUN([_MY_CXX_CHECK_FLAG],
     CXXFLAGS="$ACO_SAVE_CXXFLAGS"
    ])
 
+AC_DEFUN([_MY_CXX_CHECK_IFELSE],
+   [# _MY_CXX_CHECK_IFELSE(option,action-if-supported,action-if-not-supported)
+    # Check if compiler supports specific option. If it does,
+    # do action-if-supported, otherwise do action-if-not-supported
+    _MY_CXX_CHECK_FLAG($1)
+    if test "$_my_result" = "yes" ; then
+      true
+      $2
+    else
+      true
+      $3
+    fi
+   ])
+
 AC_DEFUN([_MY_CXX_CHECK_SET],
-   [# _MY_CXX_CHECK_SET(variable,flag) -- Check if compiler supports specific options
-    # If it does, set variable to flag, only if not previously set
+   [# _MY_CXX_CHECK_SET(variable,option)
+    # Check if compiler supports specific option. If it does,
+    # set variable to option, only if not previously set.
     if test "$$1" = ""; then
-       _MY_CXX_CHECK_FLAG($2)
-       if test "$_my_result" = "yes" ; then
-          $1="$2"
-       fi
+       _MY_CXX_CHECK_IFELSE($2, $1="$2")
     fi
    ])
 
 AC_DEFUN([_MY_CXX_CHECK_OPT],
-   [# _MY_CXX_CHECK_OPT(flag) -- Check if compiler supports specific options
-    # If it does, append flag to variable
-    _MY_CXX_CHECK_FLAG($2)
-    if test "$_my_result" = "yes" ; then
-       $1="$$1 $2"
-    fi
+   [# _MY_CXX_CHECK_OPT(variable,option)
+    # Check if compiler supports specific option. If it does,
+    # append option to variable
+    _MY_CXX_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
 AC_DEFUN([_MY_LDLIBS_CHECK_FLAG],
@@ -270,31 +315,56 @@ AC_DEFUN([_MY_LDLIBS_CHECK_OPT],
     _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2")
    ])
 
+# When using -m32. Check this first as later checks may fail with the -m32 flag.
+if test "$CFG_ENABLE_M32" = "yes"; then
+  _MY_CXX_CHECK_IFELSE(
+    -m32,
+    [CXX="$CXX -m32"],
+    [AC_MSG_ERROR([--enable-m32 was given but compiler does not support -m32])])
+fi
+
+# Similarly, add the coverage flags early as they influence later checks.
+if test "$CFG_ENABLE_COVERAGE" = "yes"; then
+  _MY_CXX_CHECK_OPT(CXX,--coverage)
+  # Otherwise inline may not show as uncovered
+  #  If we use this then e.g. verilated.h functions properly show up
+  #  if unused.
+  #  However, VerilatedSerialize::write then changes from covered
+  #  to uncovered (in G++ 9.3.0) even with all inlining turned off.
+  #  Having false negative coverage is more effort then missing negatives.
+  #  Also this seems to explode the runtime (since a lot more data).
+  #  _MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions)
+  # Otherwise static may not show as uncovered
+  _MY_CXX_CHECK_OPT(CXX,-fkeep-static-functions)
+  # Exceptions can pollute the branch coverage data
+  _MY_CXX_CHECK_OPT(CXX,-fno-exceptions)
+  # Define-out some impossible stuff
+  _MY_CXX_CHECK_OPT(CXX,-DVL_GCOV)
+fi
+
+# Compiler flags to enable profiling
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PROFILE,-pg)
+AC_SUBST(CFG_CXXFLAGS_PROFILE)
+
 # Flag to select newest language standard supported
 # Macros work such that first option that passes is the one we take
-# gnu++17 code is clean, but SystemC in 2018 doesn't link with it (bug1339)
-# gnu++14 is the newest that Verilator supports
-# std++03 is the oldest that Verilator supports
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
+# Currently enable c++17/c++14 due to packaged SystemC dependency
+# c++17 is the newest that Verilator is regularly tested to support
+# c++11 is the oldest that Verilator supports
+# gnu is requried for Cygwin to compile verilated.h successfully
+#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20)
+#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20)
+case "$(which lsb_release 2>&1 > /dev/null && lsb_release -d)" in
+*Ubuntu*22.04*)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
+;;
+esac
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++03)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++03)
 AC_SUBST(CFG_CXXFLAGS_STD_NEWEST)
-# And likewise oldest standard (same list above, backwards)
-# This is used for internal testing
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++03)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=c++14)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=std++17)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++03)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++11)
-_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++14)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_OLDEST,-std=gnu++17)
-AC_SUBST(CFG_CXXFLAGS_STD_OLDEST)
 
 # Flags for compiling Verilator internals including parser, and Verilated files
 # These turn on extra warnings and are only used with 'configure --enable-ccwarn'
@@ -318,6 +388,18 @@ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-parentheses-equality)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-unused)
 AC_SUBST(CFG_CXXFLAGS_PARSER)
 
+# Flags for compiling the debug version of Verilator (in addition to above CFG_CXXFLAGS_SRC)
+if test "$CFG_ENABLE_COVERAGE" = "no"; then # Do not optimize for the coverage build
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-Og)
+fi
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-ggdb)
+_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DEBUG,-gz)
+AC_SUBST(CFG_CXXFLAGS_DEBUG)
+
+# Flags for linking the debug version of Verilator (in addition to above CFG_LDFLAGS_SRC)
+_MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_DEBUG,-gz)
+AC_SUBST(CFG_LDFLAGS_DEBUG)
+
 # Flags for Verilated makefile
 # For example, -Wno-div-by-zero isn't in 4.1.2
 # Random code often does / 0.  Unfortunately VL_DIV_I(0,0) will warn

docs/.gitignore

@@ -2,3 +2,4 @@
 *.html
 *.pdf
 _build
+guide/spelling.txt

docs/CONTRIBUTORS

@@ -3,48 +3,66 @@ under the Developer Certificate of Origin (https://developercertificate.org/).
 
 Please see the Verilator manual for 200+ additional contributors. Thanks to all.
 
+Adrien Le Masle
 Ahmed El-Mahmoudy
 Alex Chadwick
 Àlex Torregrosa
+Aliaksei Chapyzhenka
+Ameya Vikram Singh
 Andreas Kuster
 Chris Randall
+Chuxuan Wang
 Conor McCullough
 Dan Petrisko
+Daniel Bates
 David Horton
 David Metz
 David Stanford
 David Turner
+Drew Ranck
 Drew Taussig
 Driss Hafdi
 Edgar E. Iglesias
 Eric Rippey
 Fan Shupei
+Felix Yan
 Garrett Smith
 Geza Lore
 Gianfranco Costamagna
 Glen Gibb
 Graham Rushton
+Guokai Chen
 Harald Heckmann
 Howard Su
 Huang Rui
+Huanghuang Zhou
+HungMingWu
 HyungKi Jeong
+Iru Cai
+Ivan Vnučec
 Iztok Jeras
 James Hanlon
 James Hutchinson
 James Pallister
 Jamey Hicks
+Jamie Iles
 Jan Van Winkel
 Jean Berniolles
 Jeremy Bennett
 John Coiner
 John Demme
+Jonathan Drolet
 Josh Redford
+Julie Schwartz
 Julien Margetts
 Kaleb Barrett
+Kamil Rakoczy
 Kanad Kanhere
+Keith Colbert
 Kevin Kiningham
 Krzysztof Bieganski
 Kuba Ober
+Larry Doolittle
 Ludwig Rogiers
 Lukasz Dalek
 Maarten De Braekeleer
@@ -53,9 +71,13 @@ Marco Widmer
 Markus Krause
 Marlon James
 Marshal Qiao
+Martin Schmidt
+Martin Stadler
 Matthew Ballance
 Michael Killough
+Michaël Lefebvre
 Mike Popoloski
+Miodrag Milanović
 Morten Borup Petersen
 Nandu Raj
 Nathan Kohagen
@@ -70,6 +92,7 @@ Pieter Kapsenberg
 Piotr Binkowski
 Qingyao Sun
 Rafal Kapuscik
+Raynard Qiao
 Richard Myers
 Rupert Swarbrick
 Samuel Riedel
@@ -78,6 +101,8 @@ Sebastien Van Cauwenberghe
 Sergi Granell
 Stefan Wallentowitz
 Stephen Henry
+Steven Hugg
+Teng Huang
 Tim Snyder
 Tobias Rosenkranz
 Tobias Wölfel
@@ -90,7 +115,10 @@ Vassilis Papaefstathiou
 Veripool API Bot
 Victor Besyakov
 Wilson Snyder
+Xi Zhang
+Yoda Lee
 Yossi Nivin
 Yuri Victorovich
 Yutetsu TAKATSUKASA
 Yves Mathieu
+Zhanglei Wang

docs/Makefile

@@ -5,7 +5,7 @@
 #
 # Code available from: https://verilator.org
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -35,6 +35,7 @@ default:
 # Intermediate rules
 
 vl-extract: ../bin/verilator ../Changes
+	ln -sf ../spelling.txt guide/spelling.txt
 	mkdir -p _build/gen
 	$(PYTHON3) bin/vl_sphinx_extract ../bin/verilator
 	sed 's/`/\&96;/g' < ../Changes > _build/gen/Changes
@@ -77,6 +78,7 @@ clean mostlyclean distclean maintainer-clean::
 	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
 	rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas
 	rm -f *.tex
+	rm -f guide/spelling.txt
 
 distclean maintainer-clean::
 	rm -f *.info* *.1 *.html *.pdf $(INFOS)

docs/_static/css/vlt_sphinx.css

@@ -1,16 +1,25 @@
-/*Verilator blue #008fd7; set in html*/
+/* Verilator blue #008fd7; set in html */
+
 .wy-side-nav-search > div.version {
-    color: #111;
+  color: #111;
 }
-.fa-github::before, .icon-github::before {
-    content: "";
+
+.fa-github::before,
+.icon-github::before {
+  content: "";
 }
-.fa-home::before, .icon-home::before {
-    content: "";
+
+.fa-home::before,
+.icon-home::before {
+  content: "";
 }
-.fa-arrow-circle-right::before, .icon-circle-arrow-right::before {
-    content: "";
+
+.fa-arrow-circle-right::before,
+.icon-circle-arrow-right::before {
+  content: "";
 }
-.fa-arrow-circle-left::before, .icon-circle-arrow-left::before {
-    content: "";
+
+.fa-arrow-circle-left::before,
+.icon-circle-arrow-left::before {
+  content: "";
 }

docs/bin/vl_sphinx_extract

@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0116,C0301,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0201,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################
 
@@ -8,6 +8,7 @@ import re
 
 #######################################################################
 
+
 class VlSphinxExtract:
     debug = 0
     SkipBasenames = {}
@@ -39,7 +40,7 @@ parser = argparse.ArgumentParser(
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Read a file and extract documentation data.""",
     epilog=
-    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+    """ Copyright 2021-2022 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

docs/bin/vl_sphinx_fix

@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0116,C0301,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################
 
@@ -55,7 +55,7 @@ parser = argparse.ArgumentParser(
     formatter_class=argparse.RawDescriptionHelpFormatter,
     description="""Post-process Sphinx HTML.""",
     epilog=
-    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+    """ Copyright 2021-2022 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.

docs/gen/ex_DIDNOTCONVERGE_faulty.rst

@@ -0,0 +1,6 @@
+.. comment: generated by t_lint_didnotconverge_bad
+.. code-block:: sv
+   :linenos:
+
+      always_comb b = ~a;
+      always_comb a = b;

docs/gen/ex_DIDNOTCONVERGE_msg.rst

@@ -0,0 +1,7 @@
+.. comment: generated by t_lint_didnotconverge_bad
+.. code-block::
+
+   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request
+   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request_1
+   -V{t#,#}        CHANGE: t/t_lint_didnotconverge_bad.v:14: a
+   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge

docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_didnotconverge_nodbg_bad
+.. code-block::
+
+   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge

docs/gen/ex_MULTIDRIVEN_faulty.rst

@@ -0,0 +1,11 @@
+.. comment: generated by t_lint_multidriven_bad
+.. code-block:: sv
+   :linenos:
+   :emphasize-lines: 2,5
+
+      always @(posedge clk) begin
+         out2[7:0] <= d0;  // <--- Warning
+      end
+      always @(negedge clk) begin
+         out2[15:8] <= d0;  // <--- Warning
+      end

docs/gen/ex_MULTIDRIVEN_msg.rst

@@ -0,0 +1,6 @@
+.. comment: generated by t_lint_multidriven_bad
+.. code-block::
+
+   %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 'out2'
+                         example.v:1:7 ... Location of first driving block
+                         example.v:1:7 ... Location of other driving block

docs/gen/ex_STMTDLY_faulty.rst

@@ -0,0 +1,5 @@
+.. comment: generated by t_lint_stmtdly_bad
+.. code-block:: sv
+   :emphasize-lines: 1
+
+         #100 $finish;  //<--- Warning

docs/gen/ex_STMTDLY_msg.rst

@@ -0,0 +1,4 @@
+.. comment: generated by t_lint_stmtdly_bad
+.. code-block::
+
+   %Warning-STMTDLY: example.v:1:8 Unsupported: Ignoring delay on this delayed statement.

docs/guide/changes.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ****************

docs/guide/conf.py

@@ -1,4 +1,4 @@
-# pylint: disable=E402
+# pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
 #
 # Configuration file for Verilator's Sphinx documentation builder.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -12,11 +12,10 @@
 from datetime import datetime
 import os
 import re
-import shutil
 import sys
 sys.path.insert(0, os.path.abspath('./_ext'))
 
-import sphinx_rtd_theme
+import sphinx_rtd_theme  # pylint: disable=wrong-import-position,
 
 
 def get_vlt_version():
@@ -37,7 +36,7 @@ def setup(app):
 # -- Project information
 
 project = 'Verilator'
-copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
+copyright = '2022 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
 author = 'Wilson Snyder'
 
 # The master toctree document.
@@ -94,7 +93,7 @@ today_fmt = datetime.now().strftime("%F")
 # If true, `todo` and `todoList` produce output, else they produce nothing.
 todo_include_todos = True
 
-# TODO could use this for internals<->guide references
+# Could use this for internals<->guide references
 # intersphinx_mapping = { 'sphinx': ('https://sphinx-doc.org/', None), }
 
 # ----------------------------------------------------------------------
@@ -208,7 +207,7 @@ spelling_ignore_contributor_names = True
 # ----------------------------------------------------------------------
 # -- Options for doxygen
 
-#if shutil.which("doxygen"):
+# if shutil.which("doxygen"):
 #    breathe_projects = {
 #        "verilated": "../_build/doxygen/verilated/xml",
 #    }

docs/guide/connecting.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Connecting:
@@ -7,22 +7,86 @@
 Connecting to Verilated Models
 ******************************
 
+Structure of the Verilated Model
+================================
+
+Verilator outputs a :file:`{prefix}.h` header file which defines a class
+named :code:`{prefix}` which represents the generated model the user is
+supposed to instantiate.  This model class defines the interface of the
+Verilated model.
+
+Verilator will additionally create a :file:`{prefix}.cpp` file, together
+with additional .h and .cpp files for internals.  See the :file:`examples`
+directory in the kit for examples.  See :ref:`Files Read/Written` for
+information on all the files Verilator might output.
+
+The output of Verilator will contain a :file:`{prefix}.mk` file that may be
+used with Make to build a :file:`{prefix}__ALL.a` library with all required
+objects in it.
+
+The generated model class file manages all internal state required by the
+model, and exposes the following interface that allows interaction with the
+model:
+
+* Top level IO ports are exposed as references to the appropriate internal
+  equivalents.
+
+* Public top level module instances are exposed as pointers to allow access
+  to :code:`/* verilator public */` items.
+
+* The root of the design hierarchy (as in SystemVerilog :code:`$root`) is
+  exposed via the :code:`rootp` member pointer to allow access to model
+  internals, including :code:`/* verilator public_flat */` items.
+
+
+.. _Porting from pre 4.210:
+
+Model interface changes in version 4.210
+------------------------------------------
+
+Starting from version 4.210, the model class is an interface object.
+
+Up until Verilator version 4.204 inclusive, the generated model class was
+also the instance of the top level instance in the design hierarchy (what
+you would refer to with :code:`$root` in SystemVerilog).  This meant that
+all internal variables that were implemented by Verilator in the root scope
+were accessible as members of the model class itself.  Note there were often
+many such variable due to module inlining, including :code:`/* verilator
+public_flat */` items.
+
+This means that user code that accesses internal signals in the model
+(likely including :code:`/* verilator public_flat */` signals, as they are
+often inlined into the root scope) will need to be updated as follows:
+
+* No change required for accessing top level IO signals. These are directly
+  accessible in the model class via references.
+
+* No change required for accessing :code:`/* verilator public */` items.
+  These are directly accessible via sub-module pointers in the model class.
+
+* Accessing any other internal members, including
+  :code:`/* verilator public_flat */` items requires the following changes:
+
+  * Additionally include :file:`{prefix}___024root.h`. This header defines
+    type of the :code:`rootp` pointer within the model class. Note the
+    :code:`__024` substring is the Verilator escape sequence for the
+    :code:`$` character, i.e.: :code:`rootp` points to the Verilated
+    SystemVerilog :code:`$root` scope.
+
+  * Replace :code:`modelp->internal->member->lookup` references with
+    :code:`modelp->rootp->internal->member->lookup` references, which
+    contain one additional indirection via the :code:`rootp` pointer.
+
+
 .. _Connecting to C++:
 
 Connecting to C++
 =================
 
-Verilator creates a :file:`{prefix}.h` and :file:`{prefix}.cpp` file for
-the top level module, together with additional .h and .cpp files for
-internals. See the :file:`examples` directory in the kit for examples.  See
-:ref:`Files Read/Written` for information on all the files it writes.
-
-After the model is created, there will be a :file:`{prefix}.mk` file that
-may be used with Make to produce a :file:`{prefix}__ALL.a` file with all
-required objects in it.
-
-The user must write a C++ wrapper and main loop for the simulation, to link
-with the Verilated model.  Here is a simple example:
+In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
+simple C++ class.  The user must write a C++ wrapper and main loop for the
+simulation, which instantiates the model class, and link with the Verilated
+model.  Here is a simple example:
 
 .. code-block:: C++
 
@@ -30,9 +94,9 @@ with the Verilated model.  Here is a simple example:
          #include <iostream>             // Need std::cout
          #include "Vtop.h"               // From Verilating "top.v"
 
-         Vtop *top;                      // Instantiation of module
+         Vtop *top;                      // Instantiation of model
 
-         vluint64_t main_time = 0;       // Current simulation time
+         uint64_t main_time = 0;       // Current simulation time
          // This is a 64-bit integer to reduce wrap over issues and
          // allow modulus.  This is in units of the timeprecision
          // used in Verilog (or from --timescale-override)
@@ -45,7 +109,10 @@ with the Verilated model.  Here is a simple example:
          int main(int argc, char** argv) {
              Verilated::commandArgs(argc, argv);   // Remember args
 
-             top = new Vtop;             // Create instance
+             top = new Vtop;             // Create model
+             // Do not instead make Vtop as a file-scope static
+             // variable, as the "C++ static initialization order fiasco"
+             // may cause a crash
 
              top->reset_l = 0;           // Set some inputs
 
@@ -70,27 +137,28 @@ with the Verilated model.  Here is a simple example:
          }
 
 
-Note signals are read and written as member variables of the model.  You
-call the :code:`eval()` method to evaluate the model.  When the simulation
-is complete call the :code:`final()` method to execute any SystemVerilog
-final blocks, and complete any assertions. See :ref:`Evaluation Loop`.
+Note top level IO signals are read and written as members of the model.  You
+call the :code:`eval()` method to evaluate the model.  When the simulation is
+complete call the :code:`final()` method to execute any SystemVerilog final
+blocks, and complete any assertions. See :ref:`Evaluation Loop`.
 
 
 Connecting to SystemC
 =====================
 
-Verilator will convert the top level module to a SC_MODULE.  This module
-will attach directly into a SystemC netlist as an instantiation.
+In SystemC output mode (:vlopt:`--sc`), the Verilator generated model class
+is a SystemC SC_MODULE.  This module will attach directly into a SystemC
+netlist as an instantiation.
 
 The SC_MODULE gets the same pinout as the Verilog module, with the
 following type conversions: Pins of a single bit become bool.  Pins 2-32
 bits wide become uint32_t's.  Pins 33-64 bits wide become sc_bv's or
-vluint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
+uint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
 become sc_bv's.  (Uints simulate the fastest so are used where possible.)
 
-Lower modules are not pure SystemC code.  This is a feature, as using the
-SystemC pin interconnect scheme everywhere would reduce performance by an
-order of magnitude.
+Model internals, including lower level sub-modules are not pure SystemC
+code.  This is a feature, as using the SystemC pin interconnect scheme
+everywhere would reduce performance by an order of magnitude.
 
 
 Direct Programming Interface (DPI)
@@ -135,7 +203,7 @@ DPI System Task/Functions
 -------------------------
 
 Verilator extends the DPI format to allow using the same scheme to
-efficiently add system functions.  Simply use a dollar-sign prefixed system
+efficiently add system functions.  Use a dollar-sign prefixed system
 function name for the import, but note it must be escaped.
 
 .. code-block:: sv
@@ -192,7 +260,9 @@ with respect to that top level module, then the scope could be set with
 
      #include "svdpi.h"
      ...
-     svSetScope(svGetScopeFromName("TOP.dut"));
+     const svScope scope = svGetScopeFromName("TOP.dut");
+     assert(scope);  // Check for nullptr if scope not found
+     svSetScope(scope);
 
 (Remember that Verilator adds a "TOP" to the top of the module hierarchy.)
 
@@ -357,12 +427,12 @@ accesses the above signal "readme" would be:
 
 .. code-block:: bash
 
-     cat >sim_main.cpp <<'<<EOF'
+     cat >sim_main.cpp <<'EOF'
        #include "Vour.h"
        #include "verilated.h"
        #include "verilated_vpi.h"  // Required to get definitions
 
-       vluint64_t main_time = 0;   // See comments in first example
+       uint64_t main_time = 0;   // See comments in first example
        double sc_time_stamp() { return main_time; }
 
        void read_and_check() {
@@ -441,7 +511,7 @@ structure.  If a ``VerilatedContext`` is not created prior to creating a
 model, a default global one is created automatically.
 
 The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
-shown above, simply call VerilatedContext methods using the default global
+shown above, call VerilatedContext methods using the default global
 VerilatedContext.  (Technically they operate on the last one used by a
 given thread.)  If you are using multiple simulation contexts you should
 not use the Verilated:: methods, and instead always use VerilatedContext

docs/guide/contributing.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************************

docs/guide/contributors.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ************************
@@ -13,7 +13,8 @@ When possible, please instead report bugs at `Verilator Issues
 
 Primary author is Wilson Snyder <[email protected]>.
 
-Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu.
+Major concepts by Paul Wasson, Duane Galbi, John Coiner, Geza Lore, Yutetsu
+Takatsukasa, and Jie Xu.
 
 
 Contributors
@@ -22,14 +23,14 @@ Contributors
 Many people have provided ideas and other assistance with Verilator.
 
 Verilator is receiving major development support from the `CHIPS Alliance
-<https://chipsalliance.org>`_.
+<https://chipsalliance.org>`_ and `Shunyao CAD <https://shunyaocad.com>`_.
 
 Previous major corporate sponsors of Verilator, by providing significant
 contributions of time or funds included include: Atmel Corporation, Cavium
 Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
 Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
 Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
-and SiCortex Inc.
+SiCortex Inc, and Shunyao CAD.
 
 The people who have contributed major functionality are: Byron Bradley,
 Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd

docs/guide/copyright.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********
@@ -8,7 +8,7 @@ Copyright
 The latest version of Verilator is available from `https://verilator.org
 <https://verilator.org>`_.
 
-Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

docs/guide/deprecations.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Deprecations
@@ -9,20 +9,29 @@ The following deprecated items are scheduled for future removal:
 C++11 compiler support
   Verilator currently requires C++11 or newer compilers.  Verilator will
   require C++14 or newer compilers for both compiling Verilator and
-  compiling Verilated models no sooner than January 2022.
+  compiling Verilated models no sooner than January 2023.
 
-No-Relative-Cfuncs Option
-  The :vlopt:`--no-relative-cfuncs` option is not be required by any C++11
-  compliant compiler and is planned for removal no sooner than July 2021.
+Verilated_heavy.h
+  The legacy "verilated_heavy.h" include was replaced with just including
+  "verilated.h". Verilated_heavy.h is planned for removal no sooner than
+  July 2022.
 
-Inhibit-Sim Option
-  The :vlopt:`--inhibit-sim` option is planned for removal no sooner than
-  July 2021.
+Option `--cdc`
+  The experimental `--cdc` option is believed to be generally unused and is
+  planned for removal no sooner than January 2023.
 
-Configuration File -msg
-  The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule"
-  option.  "-msg" is planned for removal no sooner than January 2021.
+Option `-O<letter>`
+  The debug `-O<letter>` options have been replaced with
+  `-fno-<optimization>` debug options to match GCC. The old options are
+  planned for removal no sooner than June 2023.
 
-XML locations
-  The XML "fl" attribute has been replaced with the "loc" attribute.  "fl"
-  is planned for removal no sooner than January 2021.
+Option `--prof-threads`
+  The `--prof-threads` option has been superseded by the `--prof-exec` and
+  `--prof-pgo` options and is planned for removal no sooner than April 2023.
+
+Verilated model options `+verilator+prof+threads+*`
+  The `+verilator+prof+threads+start`, `+verilator+prof+threads+window` and
+  `+verilator+prof+threads+file` options have been superseded by the
+  `+verilator+prof+exec+start`, `+verilator+prof+exec+window` and
+  `+verilator+prof+exec+file` options respectively and are planned for removal
+  no sooner than April 2023.

docs/guide/environment.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 Environment

docs/guide/example_cc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example C++ Execution:

docs/guide/example_common_install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 First you need Verilator installed, see :ref:`Installation`. In brief, if

docs/guide/example_dist.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Examples in the Distribution:

docs/guide/example_sc.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Example SystemC Execution:

docs/guide/examples.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Examples:

docs/guide/exe_sim.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Simulation Runtime Arguments:
@@ -38,30 +38,48 @@ Summary:
 
    Display help and exit.
 
-.. option:: +verilator+prof+threads+file+<filename>
+.. option:: +verilator+prof+exec+file+<filename>
 
-   When a model was Verilated using :vlopt:`--prof-threads`, sets the
+   When a model was Verilated using :vlopt:`--prof-exec`, sets the
    simulation runtime filename to dump to.  Defaults to
-   :file:`profile_threads.dat`.
+   :file:`profile_exec.dat`.
 
-.. option:: +verilator+prof+threads+start+<value>
+.. option:: +verilator+prof+exec+start+<value>
 
-   When a model was Verilated using :vlopt:`--prof-threads`, the simulation
+   When a model was Verilated using :vlopt:`--prof-exec`, the simulation
    runtime will wait until $time is at this value (expressed in units of
    the time precision), then start the profiling warmup, then
    capturing. Generally this should be set to some time that is well within
    the normal operation of the simulation, i.e. outside of reset. If 0, the
    dump is disabled. Defaults to 1.
 
-.. option:: +verilator+prof+threads+window+<value>
+.. option:: +verilator+prof+exec+window+<value>
 
-   When a model was Verilated using :vlopt:`--prof-threads`, after $time
-   reaches :vlopt:`+verilator+prof+threads+start+\<value\>`, Verilator will
+   When a model was Verilated using :vlopt:`--prof-exec`, after $time
+   reaches :vlopt:`+verilator+prof+exec+start+\<value\>`, Verilator will
    warm up the profiling for this number of eval() calls, then will capture
    the profiling of this number of eval() calls.  Defaults to 2, which
    makes sense for a single-clock-domain module where it's typical to want
    to capture one posedge eval() and one negedge eval().
 
+.. option:: +verilator+prof+threads+file+<filename>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+file+\<filename\>`
+
+.. option:: +verilator+prof+threads+start+<value>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+start+\<value\>`
+
+.. option:: +verilator+prof+threads+window+<value>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\<filename\>`
+
+.. option:: +verilator+prof+vlt+file+<filename>
+
+   When a model was Verilated using :vlopt:`--prof-pgo`, sets the
+   profile-guided optimization data runtime filename to dump to.  Defaults
+   to :file:`profile.vlt`.
+
 .. option:: +verilator+rand+reset+<value>
 
    When a model was Verilated using :vlopt:`--x-initial unique

docs/guide/exe_verilator.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator Arguments
@@ -99,10 +99,10 @@ Summary:
 .. option:: --bbox-sys
 
    Black box any unknown $system task or function calls.  System tasks will
-   simply become no-operations, and system functions will be replaced with
-   unsized zero.  Arguments to such functions will be parsed, but not
-   otherwise checked.  This prevents errors when linting in the presence of
-   company specific PLI calls.
+   become no-operations, and system functions will be replaced with unsized
+   zero.  Arguments to such functions will be parsed, but not otherwise
+   checked.  This prevents errors when linting in the presence of company
+   specific PLI calls.
 
    Using this argument will likely cause incorrect simulation.
 
@@ -158,41 +158,26 @@ Summary:
 
 .. option:: --clk <signal-name>
 
-   Sometimes it is quite difficult for Verilator to distinguish clock
-   signals from other data signals. Occasionally the clock signals can end
-   up in the checking list of signals which determines if further
-   evaluation is needed. This will heavily degrade the performance of a
-   Verilated model.
-
    With :vlopt:`--clk`, the specified signal-name is taken as a root clock
-   into the model, then Verilator will mark the signal as clocker and
-   propagate the clocker attribute automatically to other signals derived
-   from that. In this way, Verilator will try to avoid taking the clocker
-   signal into checking list.
+   into the model; Verilator will mark the signal as clocker and
+   propagate the clocker attribute automatically to other signals downstream in
+   that clock tree.
 
-   Note signal-name is specified by the RTL hierarchy path. For example,
-   v.foo.bar.  If the signal is the input to top-module, the directly the
-   signal name. If you find it difficult to find the exact name, try to use
-   a :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the
+   The provided signal-name is specified using a RTL hierarchy path. For
+   example, v.foo.bar.  If the signal is the input to top-module, then
+   directly provide the signal name. Alternatively, use a
+   :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the
    signal directly.
 
-   If clock signals are assigned to vectors and then later used
-   individually, Verilator will attempt to decompose the vector and connect
-   the single-bit clock signals directly.  This should be transparent to
-   the user.
+   If clock signals are assigned to vectors and then later used as
+   individual bits, Verilator will attempt to decompose the vector and
+   connect the single-bit clock signals.
 
-.. option:: --make <build-tool>
-
-   Generates a script for the specified build tool.
-
-   Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake.
-   Both can be specified together.  If no build tool is specified, gmake is
-   assumed.  The executable of gmake can be configured via environment
-   variable "MAKE".
-
-   When using :vlopt:`--build` Verilator takes over the responsibility of
-   building the model library/executable.  For this reason :option:`--make`
-   cannot be specified when using :vlopt:`--build`.
+   The clocker attribute is useful in cases where Verilator does not
+   properly distinguish clock signals from other data signals. Using
+   clocker will cause the signal indicated to be considered a clock, and
+   remove it from the combinatorial logic reevaluation checking code. This
+   may greatly improve performance.
 
 .. option:: --compiler <compiler-name>
 
@@ -403,6 +388,12 @@ Summary:
    files on the command line that implement the main loop for your
    simulation.
 
+.. option:: --expand-limit <value>
+
+   Rarely needed.  Fine-tune optimizations to set the maximum size of an
+   expression in 32-bit words to expand into separate word-based
+   statements.
+
 .. option:: -F <file>
 
    Read the specified file, and act as if all text inside it was specified
@@ -418,8 +409,11 @@ Summary:
    fairly standard across Verilog tools.
 
    The file may contain :code:`//` comments which are ignored to the end of
-   the line.  Any :code:`$VAR`, :code:`$(VAR)`, or :code:`${VAR}` will be
-   replaced with the specified environment variable.
+   the line.  It may also contain :code:`/* .. */` comments which are
+   ignored, be cautious that wildcards are not handled in -f files, and
+   that :code:`directory/*` is the beginning of a comment, not a wildcard.
+   Any :code:`$VAR`, :code:`$(VAR)`, or :code:`${VAR}` will be replaced
+   with the specified environment variable.
 
 .. option:: -FI <file>
 
@@ -437,6 +431,54 @@ Summary:
    flattening large designs may require significant CPU time, memory and
    storage.
 
+.. option:: -fno-acyc-simp
+
+.. option:: -fno-assemble
+
+.. option:: -fno-case
+
+.. option:: -fno-combine
+
+.. option:: -fno-const
+
+.. option:: -fno-const-bit-op-tree
+
+.. option:: -fno-dedup
+
+.. option:: -fno-expand
+
+.. option:: -fno-gate
+
+.. option:: -fno-inline
+
+.. option:: -fno-life
+
+.. option:: -fno-life-post
+
+.. option:: -fno-localize
+
+.. option:: -fno-merge-cond
+
+.. option:: -fno-merge-cond-motion
+
+.. option:: -fno-merge-const-pool
+
+.. option:: -fno-reloop
+
+.. option:: -fno-reorder
+
+.. option:: -fno-split
+
+.. option:: -fno-subst
+
+.. option:: -fno-subst-const
+
+.. option:: -fno-table
+
+   Rarely needed. Disables one of the internal optimization steps. These
+   are typically used only when recommended by a maintainer to help debug
+   or work around an issue.
+
 .. option:: -G<name>=<value>
 
    Overwrites the given parameter of the toplevel module. The value is
@@ -518,14 +560,6 @@ Summary:
 
    See :vlopt:`-y`.
 
-.. option:: --inhibit-sim
-
-   Rarely needed and deprecated.  Create a :code:`inhibitSim(bool)`
-   function to enable and disable evaluation.  This allows an upper level
-   testbench to disable modules that are not important in a given
-   simulation, without needing to recompile or change the SystemC modules
-   instantiated.
-
 .. option:: --inline-mult <value>
 
    Tune the inlining of modules.  The default value of 2000 specifies that up
@@ -535,6 +569,14 @@ Summary:
    times, but potentially faster simulation speed.  This setting is ignored
    for very small modules; they will always be inlined, if allowed.
 
+.. option:: --instr-count-dpi <value>
+
+   Assumed dynamic instruction count of the average DPI import. This is used
+   by the partitioning algorithm when creating a multithread model. The
+   default value is 200. Adjusting this to an appropriate value can yield
+   performance improvements in multithreaded models. Ignored when creating a
+   single threaded model.
+
 .. option:: -j [<value>]
 
    Specify the level of parallelism for :vlopt:`--build`. The <value> must
@@ -581,6 +623,23 @@ Summary:
    "+libext+" is fairly standard across Verilog tools.  Defaults to
    ".v+.sv".
 
+.. option:: --lib-create <name>
+
+   Produces C++, Verilog wrappers and a Makefile which can in turn produce
+   a DPI library which can be used by Verilator or other simulators along
+   with the corresponding Verilog wrapper.  The Makefile will build both a
+   static and dynamic version of the library named :file:`lib<name>.a` and
+   :file:`lib<name>.so` respectively.  This is done because some simulators
+   require a dynamic library, but the static library is arguably easier to
+   use if possible.  :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`.
+
+   When using :vlopt:`--lib-create` it is advised to also use
+   :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the
+   model has a time resolution that is always compatible with the time
+   precision of the upper instantiating module.
+
+   See also :vlopt:`--protect-lib`.
+
 .. option:: --lint-only
 
    Check the files for lint violations only, do not create any other
@@ -592,6 +651,19 @@ Summary:
    If the design is not to be completely Verilated see also the
    :vlopt:`--bbox-sys` and :vlopt:`--bbox-unsup` options.
 
+.. option:: --make <build-tool>
+
+   Generates a script for the specified build tool.
+
+   Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake.
+   Both can be specified together.  If no build tool is specified, gmake is
+   assumed.  The executable of gmake can be configured via environment
+   variable "MAKE".
+
+   When using :vlopt:`--build` Verilator takes over the responsibility of
+   building the model library/executable.  For this reason :option:`--make`
+   cannot be specified when using :vlopt:`--build`.
+
 .. option:: -MAKEFLAGS <string>
 
    When using :vlopt:`--build`, add the specified argument to the invoked
@@ -645,10 +717,6 @@ Summary:
 
    Backward compatible alias for :vlopt:`--pins-bv 33 <--pins-bv>`.
 
-.. option:: --no-relative-cfuncs
-
-   Deprecated.
-
 .. option:: --no-skip-identical =item --skip-identical
 
    Rarely needed.  Disables or enables skipping execution of Verilator if
@@ -676,9 +744,9 @@ Summary:
 
    Rarely needed.  Enables or disables a specific optimizations, with the
    optimization selected based on the letter passed.  A lowercase letter
-   disables an optimization, an upper case letter enables it.  This is
-   intended for debugging use only; see the source code for
-   version-dependent mappings of optimizations to -O letters.
+   disables an optimization, an upper case letter enables it.  This option
+   is deprecated and the various `-f<optimization>` arguments should be
+   used instead.
 
 .. option:: -o <executable>
 
@@ -741,7 +809,7 @@ Summary:
 .. option:: --pins-bv <width>
 
    Specifies SystemC inputs/outputs of greater than or equal to <width>
-   bits wide should use sc_bv's instead of uint32/vluint64_t's.  The
+   bits wide should use sc_bv's instead of uint32/uint64_t's.  The
    default is "--pins-bv 65", and the value must be less than or equal
    to 65.  Versions before Verilator 3.671 defaulted to "--pins-bv 33".
    The more sc_bv is used, the worse for performance.  Use the
@@ -799,6 +867,13 @@ Summary:
    prepended to the name of the :vlopt:`--top` option, or V prepended to
    the first Verilog filename passed on the command line.
 
+.. option:: --prof-c
+
+   When compiling the C++ code, enable the compiler's profiling flag
+   (e.g. :code:`g++ -pg`). See :ref:`Profiling`.
+
+   Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`.
+
 .. option:: --prof-cfuncs
 
    Modify the created C++ functions to support profiling.  The functions
@@ -809,10 +884,21 @@ Summary:
    came from.  This allows gprof or oprofile reports to be correlated with
    the original Verilog source statements. See :ref:`Profiling`.
 
+   Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`.
+
+.. option:: --prof-exec
+
+   Enable collection of execution trace, that can be converted into a gantt
+   chart with verilator_gantt See :ref:`Execution Profiling`.
+
+.. option:: --prof-pgo
+
+   Enable collection of profiling data for profile guided Verilation. Currently
+   this is only useful with :vlopt:`--threads`. See :ref:`Thread PGO`.
+
 .. option:: --prof-threads
 
-   Enable gantt chart data collection for threaded builds. See :ref:`Thread
-   Profiling`.
+   Deprecated. Same as --prof-exec and --prof-pgo together.
 
 .. option:: --protect-key <key>
 
@@ -848,29 +934,20 @@ Summary:
 
    Using DPI imports/exports is allowed and generally relatively safe in
    terms of information disclosed, which is limited to the DPI function
-   prototyptes.  Use of the VPI is not recommended as many design details
+   prototypes.  Use of the VPI is not recommended as many design details
    may be exposed, and an INSECURE warning will be issued.
 
 .. option:: --protect-lib <name>
 
-   Produces C++, Verilog wrappers and a Makefile which can in turn produce
-   a DPI library which can be used by Verilator or other simulators along
-   with the corresponding Verilog wrapper.  The Makefile will build both a
-   static and dynamic version of the library named :file:`lib<name>.a` and
-   :file:`lib<name>.so` respectively.  This is done because some simulators
-   require a dynamic library, but the static library is arguably easier to
-   use if possible.  :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`.
+   Produces a DPI library similar to :vlopt:`--lib-create`, but hides
+   internal design details.  :vlopt:`--protect-lib` implies
+   :vlopt:`--protect-ids`, and :vlopt:`--lib-create`.
 
    This allows for the secure delivery of sensitive IP without the need for
    encrypted RTL (i.e. IEEE P1735).  See :file:`examples/make_protect_lib`
    in the distribution for a demonstration of how to build and use the DPI
    library.
 
-   When using :vlopt:`--protect-lib` it is advised to also use
-   :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the
-   model has a time resolution that is always compatible with the time
-   precision of the upper instantiating module.
-
 .. option:: --private
 
    Opposite of :vlopt:`--public`.  Is the default; this option exists for
@@ -915,6 +992,15 @@ Summary:
    the path of the referencing file, instead of relative to the current
    directory.
 
+.. option:: --reloop-limit
+
+   Rarely needed. Verilator attempts to turn some common sequences of
+   statements into loops in the output. This argument specifies the minimum
+   number of iterations the resulting loop needs to have in order to perform
+   this transformation. Default limit is 40. A smaller number may slightly
+   improve C++ compilation time on designs where these sequences are common,
+   however effect on model performance requires benchmarking.
+
 .. option:: --report-unoptflat
 
    Extra diagnostics for UNOPTFLAT warnings. This includes for each loop,
@@ -996,7 +1082,8 @@ Summary:
    is not thread safe. With "--threads 1", the generated model is single
    threaded but may run in a multithreaded environment. With "--threads N",
    where N >= 2, the model is generated to run multithreaded on up to N
-   threads. See :ref:`Multithreading`.
+   threads. See :ref:`Multithreading`. This option also applies to
+   :vlopt:`--trace` (but not :vlopt:`--trace-fst`).
 
 .. option:: --threads-dpi all
 
@@ -1022,6 +1109,8 @@ Summary:
      Verilator assumes DPI pure imports are threadsafe, but non-pure DPI
      imports are not.
 
+   See also :vlopt:`--instr-count-dpi` option.
+
 .. option:: --threads-max-mtasks <value>
 
    Rarely needed.  When using :vlopt:`--threads`, specify the number of
@@ -1072,7 +1161,8 @@ Summary:
    Having tracing compiled in may result in some small performance losses,
    even when tracing is not turned on during model execution.
 
-   See also :vlopt:`--trace-threads` option.
+   When using :vlopt:`--threads`, VCD tracing is parallelized, using the
+   same number of threads as passed to :vlopt:`--threads`.
 
 .. option:: --trace-coverage
 
@@ -1126,18 +1216,18 @@ Summary:
 .. option:: --trace-threads *threads*
 
    Enable waveform tracing using separate threads. This is typically faster
-   in simulation runtime but uses more total compute. This option is
-   independent of, and works with, both :vlopt:`--trace` and
-   :vlopt:`--trace-fst`.  Different trace formats can take advantage of
-   more trace threads to varying degrees. Currently VCD tracing can utilize
-   at most "--trace-threads 1", and FST tracing can utilize at most
-   "--trace-threads 2". This overrides :vlopt:`--no-threads` .
+   in simulation runtime but uses more total compute. This option only
+   applies to :vlopt:`--trace-fst`. FST tracing can utilize at most
+   "--trace-threads 2". This overrides :vlopt:`--no-threads`.
+
+   This option is accepted, but has absolutely no effect with
+   :vlopt:`--trace`, which respects :vlopt:`--threads` instead.
 
 .. option:: --trace-underscore
 
-   Enable tracing of signals that start with an underscore. Normally, these
-   signals are not output during tracing.  See also
-   :vlopt:`--coverage-underscore` option.
+   Enable tracing of signals or modules that start with an
+   underscore. Normally, these signals are not output during tracing.  See
+   also :vlopt:`--coverage-underscore` option.
 
 .. option:: -U<var>
 
@@ -1326,9 +1416,10 @@ Summary:
    .. note::
 
       This option applies only to values which are explicitly written as X
-      in the Verilog source code. Initial values of clocks are set to 0
-      unless `--x-initial-edge` is specified. Initial values of all other
-      state holding variables are controlled with `--x-initial`.
+      in modules (not classes) in the Verilog source code. Initial values
+      of clocks are set to 0 unless `--x-initial-edge` is
+      specified. Initial values of all other state holding variables are
+      controlled with `--x-initial`.
 
 .. option:: --x-initial 0
 
@@ -1474,9 +1565,9 @@ The grammar of configuration commands is as follows:
 
 .. option:: no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
 
-   Indicate the signal is used as clock or not. This information is used by
-   Verilator to mark the signal as clocker and propagate the clocker
-   attribute automatically to derived signals. See :vlopt:`--clk`.
+   Indicates that the signal is used as clock or not. This information is
+   used by Verilator to mark the signal and any derived signals as
+   clocker.  See :vlopt:`--clk`.
 
    Same as :option:`/*verilator&32;clocker*/` metacomment.
 
@@ -1490,6 +1581,14 @@ The grammar of configuration commands is as follows:
 
    Same as :option:`/*verilator&32;coverage_block_off*/` metacomment.
 
+.. option:: forceable -module "<modulename>" -var "<signame>"
+
+   Generate public `<signame>__VforceEn` and `<signame>__VforceVal` signals
+   that can be used to force/release a signal from C++ code. The force control
+   signals are created as :option:`public_flat` signals.
+
+   Same as :option:`/*verilator&32;forceable*/` metacomment.
+
 .. option:: full_case -file "<filename>" -lines <lineno>
 
 .. option:: parallel_case -file "<filename>" -lines <lineno>
@@ -1580,12 +1679,18 @@ The grammar of configuration commands is as follows:
    :option:`/*verilator&32;public_flat*/`, etc, metacomments. See
    e.g. :ref:`VPI Example`.
 
+.. option:: profile_data -mtask "<mtask_hash>" -cost <cost_value>
+
+   Feeds profile-guided optimization data into the Verilator algorithms in
+   order to improve model runtime performance.  This option is not expected
+   to be used by users directly.  See :ref:`Thread PGO`.
+
 .. option:: sc_bv -module "<modulename>" [-task "<taskname>"] -var "<signame>"
 
 .. option:: sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>"
 
    Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool,
-   vluint32_t or vluint64_t.  Same as :option:`/*verilator&32;sc_bv*/`
+   uint32_t or uint64_t.  Same as :option:`/*verilator&32;sc_bv*/`
    metacomment.
 
 .. option:: sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"
@@ -1614,9 +1719,28 @@ The grammar of configuration commands is as follows:
 
 .. option:: tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]
 
-   Enable/disable waveform tracing for all future signals declared in the
-   specified filename (or wildcard with '\*' or '?', or all files if
-   omitted) and range of line numbers (or all lines if omitted).
+.. option:: tracing_on  [-scope "<scopename>" [-levels <levels> ]]
 
-   For tracing_off, instances below any module in the files/ranges
-   specified will also not be traced.
+.. option:: tracing_off [-scope "<scopename>" [-levels <levels> ]]
+
+   Enable/disable waveform tracing for all future signals declared in
+   all files.
+
+   With -file, enable/disable waveform tracing in the specified
+   filename (or wildcard with '\*' or '?'), and -line range of line
+   numbers (or all lines if omitted).
+
+   For tracing_off with -file, instances below any module in the
+   files/ranges specified will also not be traced.  To overcome this
+   feature, use tracing_on on the upper module declaration and on any
+   cells, or use the -scope flavor of the command.
+
+   With -scope enable/disable waveform tracing for the specified scope (or
+   wildcard with '\*' or '?'), and optional --levels number of levels
+   below.  These controls only take place after other file/line/module
+   based controls have indicated the signal should be traced.
+
+   With -levels (used with -scope), the number of levels below that
+   scope which the rule is to match, where 0 means all levels below, 1
+   the exact level as the provided scope, and 2 meaning an additional
+   level of children below the provided scope, etc.

docs/guide/exe_verilator_coverage.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_coverage
@@ -67,7 +67,7 @@ which have low coverage are written to the output directory.
 
 Specifies if the coverage point does not include the count number of
 coverage hits, then the coverage point will be considered above the
-threashold, and the coverage report will put a "%" to indicate the coverage
+threshold, and the coverage report will put a "%" to indicate the coverage
 is not sufficient.  Defaults to 10.
 
 .. option:: --help

docs/guide/exe_verilator_gantt.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 verilator_gantt
@@ -10,42 +10,60 @@ starts and ends, and showing when each thread is busy or idle.
 
 For an overview of use of verilator_gantt, see :ref:`Profiling`.
 
-Gantt Chart Contents
---------------------
+Gantt Chart VCD
+---------------
 
-The generated Gantt chart has time on the X-axis. Times shown are to the
-scale printed, i.e. a certain about of time for each character width.  The
-Y-axis shows threads, each thread's execution is shown on one line.  That
-line shows "[" at the position in time when it executes.
+Verilated_gantt creates a value change dump (VCD) format dump file which
+may be viewed in a waveform viewer (e.g. C<GTKWave>):
 
-Following the "[" is the CPU number the task executed on, followed by zero
-or more "-" to make the width of the characters match the scaled execution
-time, followed by a "]".  If the scale is too small, the CPU number and
-mtask number will not be printed.  If the scale is very small, a "&"
-indicates multiple mtasks started at that time position.
+.. figure:: figures/fig_gantt_min.png
+
+   Example verilator_gantt output, as viewed with GTKWave.
+
+The viewed waveform chart has time on the X-axis, with one unit for each
+time tick of the system's high-performance counter.
 
-Also creates a value change dump (VCD) format dump file which may be viewed
-in a waveform viewer (e.g. C<GTKWave>).  See below.
 
 Gantt Chart VCD Signals
 -----------------------
 
-In waveforms there are the following signals. Most signals the "decimal"
-format will remove the leading zeros and make the traces easier to read.
+In waveforms there are the following signals. In GTKWave, using a data
+format of "decimal" will remove the leading zeros and make the traces
+easier to read.
 
-parallelism
+evals
+  Increments each time when eval_step was measured to be active.  This
+  allow visualization of how much time eval_step was active.
+
+eval_loop
+  Increments each time when the evaluation loop within eval_step was
+  measured to be active.  For best performance there is only a single
+  evaluation loop within each eval_step call, that is the eval_loop
+  waveform looks identical to the evals waveform.
+
+measured_parallelism
   The number of mtasks active at this time, for best performance this will
-  match the thread count. You may want to use an "analog step" format to
+  match the thread count. In GTKWave, use a data format of "analog step" to
   view this signal.
 
+predicted_parallelism
+  The number of mtasks Verilator predicted would be active at this time,
+  for best performance this will match the thread count. In GTKWave, use a
+  data format of "analog step" to view this signal.
+
 cpu#_thread
-  For the given CPU number, the thread number executing.
+  For the given CPU number, the thread number measured to be executing.
 
 mtask#_cpu
-  For the given mtask id, the CPU it is executing on.
+  For the given mtask id, the CPU it was measured to execute on.
 
 thread#_mtask
-  For the given thread number, the mtask id executing.
+  For the given thread number, the mtask id it was executing.
+
+predicted_thread#_mtask
+  For the given thread number, the mtask id Verilator predicted would be
+  executing.
+
 
 verilator_gantt Arguments
 -------------------------
@@ -54,19 +72,12 @@ verilator_gantt Arguments
 
 .. option:: <filename>
 
-The filename to read data from, defaults to "profile_threads.dat".
+The filename to read data from, defaults to "profile_exec.dat".
 
 .. option:: --help
 
 Displays a help summary, the program version, and exits.
 
-.. option:: --scale <n>
-
-Sets the number of time units per character on the X-axis of the generated
-Gantt chart.  (On x86, time units are rdtsc ticks.)  Defaults to 0, which
-will automatically compute a reasonable scale where no two mtasks need to
-fit into same character width's worth of scaled time.
-
 .. option:: --no-vcd
 
 Disables creating a .vcd file.

docs/guide/exe_verilator_profcfunc.rst

@@ -1,20 +1,24 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-verilator_profcfuncs
-====================
+verilator_profcfunc
+===================
 
 Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of time, etc, in
 each Verilog block.
 
-For an overview of use of verilator_profcfuncs, see :ref:`Profiling`.
+Due to rounding errors in gprof reports, the input report's percentages may
+not total to 100%.  In the verilator_profcfunc report this will get
+reported as a rounding error.
 
-verilator_profcfuncs Arguments
-------------------------------
+For an overview of use of verilator_profcfunc, see :ref:`Profiling`.
 
-.. program:: verilator_profcfuncs
+verilator_profcfunc Arguments
+-----------------------------
+
+.. program:: verilator_profcfunc
 
 .. option:: <filename>
 

docs/guide/executables.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *********************************
@@ -15,5 +15,5 @@ options to each executable.
    exe_verilator.rst
    exe_verilator_coverage.rst
    exe_verilator_gantt.rst
-   exe_verilator_profcfuncs.rst
+   exe_verilator_profcfunc.rst
    exe_sim.rst

docs/guide/extensions.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************
@@ -33,7 +33,12 @@ or "`ifdef`"'s may break other tools.
    that returns up to a 32-bit number (without a trailing ;). This can be
    used to call C++ functions from your Verilog code.
 
-   String arguments will be put directly into the output C++ code.
+   String arguments will be put directly into the output C++ code, except
+   the word 'this' (i.e.: the object pointer) might be replaced with a
+   different pointer as Verilator might implement logic with non-member
+   functions. For this reason, any references to class members must be made
+   via an explicit 'this->' pointer dereference.
+
    Expression arguments will have the code to evaluate the expression
    inserted.  Thus to call a C++ function, :code:`$c("func(",a,")")` will
    result in :code:`func(a)` in the output C++ code.  For input arguments,
@@ -43,6 +48,14 @@ or "`ifdef`"'s may break other tools.
    Verilog functions where the variable is flattened out, and also enable
    other optimizations.
 
+   Verilator does not use any text inside the quotes for
+   ordering/scheduling.  If you need the $c to be called at a specific
+   time, e.g. when a variable changes, then the $c must be under an
+   appropriate sensitivity statement, e.g. :code:`always @(posedge clk)
+   $c("func()")` to call it on every edge, or e.g. :code:`always @*
+   c("func(",a,")")` to call it when :code:`a` changes (the latter working
+   because :code:`a` is outside the quotes).
+
    If you will be reading or writing any Verilog variables inside the C++
    functions, the Verilog signals must be declared with
    :option:`/*verilator&32;public*/` metacomments.
@@ -171,10 +184,9 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;no_clocker*/
 
-   Used after a signal declaration to indicate the signal is used as clock
-   or not. This information is used by Verilator to mark the signal as
-   clocker and propagate the clocker attribute automatically to derived
-   signals. See :vlopt:`--clk`.
+   Specifies that the signal is used as clock or not. This information is
+   used by Verilator to mark the signal and any derived signals as
+   clocker.  See :vlopt:`--clk`.
 
    Same as :option:`clocker` and :option:`no_clocker` in configuration
    files.
@@ -197,6 +209,20 @@ or "`ifdef`"'s may break other tools.
    (if appropriate :vlopt:`--coverage` flags are passed) after being
    disabled earlier with :option:`/*verilator&32;coverage_off*/`.
 
+.. option:: /*verilator&32;forceable*/
+
+   Specifies that the signal (net or variable) should be made forceable from
+   C++ code by generating public `<signame>__VforceEn` and
+   `<signame>__VforceVal` signals The force control signals are created as
+   :option:`public_flat` signals.
+
+   To force a marked signal from C++, set the corresponding `__VforceVal`
+   variable to the desired value, and the `__VforceEn` signal to the bit-mask
+   indicating which bits of the signal to force. To force all bits of the
+   target signal, set `__VforceEn` to all ones. To release the signal (or part
+   thereof), set appropriate bits of the `__VforceEn` signal to zero.
+
+   Same as :option:`forceable` in configuration  files.
 
 .. _verilator_hier_block:
 
@@ -419,7 +445,7 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;sc_bv*/
 
    Used after a port declaration.  It sets the port to be of
-   :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t.
+   :code:`sc_bv<{width}>` type, instead of bool, uint32_t or uint64_t.
    This may be useful if the port width is parameterized and the
    instantiating C++ code wants to always have a sc_bv so it can accept any
    width.  In general you should avoid using this attribute when not
@@ -477,6 +503,13 @@ or "`ifdef`"'s may break other tools.
    Verilator) text that should be passed through to the XML output as a tag,
    for use by downstream applications.
 
+.. option:: /*verilator&32;trace_init_task*/
+
+   Attached to a DPI import to indicate that function should be called when
+   initializing tracing. This attribute is indented only to be used
+   internally in code that Verilator generates when :vlopt:`--lib-create`
+   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`.
+
 .. option:: /*verilator&32;tracing_off*/
 
    Disable waveform tracing for all future signals that are declared in

docs/guide/faq.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ******************************
@@ -35,15 +35,17 @@ simulators.
 Does Verilator run under Windows?
 """""""""""""""""""""""""""""""""
 
-Yes, using Cygwin.  Verilated output also compiles under Microsoft Visual
-C++, but this is not tested every release.
+Yes, ideally run Ubuntu under Windows Subsystem for Linux (WSL2).
+Alternatively use Cygwin, though this tends to be slower and is not
+regularly tested.  Verilated output also compiles under Microsoft Visual
+C++, but this is also not regularly tested.
 
 
 Can you provide binaries?
 """""""""""""""""""""""""
 
 You can install Verilator via the system package manager (apt, yum, etc.)
-on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and
+on many Linux distributions, including Debian, Ubuntu, SuSE, Red Hat, and
 others.  These packages are provided by the Linux distributions and
 generally will lag the version of the mainline Verilator repository.  If no
 binary package is available for your distribution, how about you set one
@@ -70,23 +72,38 @@ a good thing for getting working silicon.
 Will Verilator output remain under my own license/copyright?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Yes, it's just like using GCC on your programs; this is why Verilator uses
-the "GNU **Lesser** Public License Version 3" instead of the more typical
-"GNU Public License".  See the licenses for details, but in brief, if you
-change Verilator itself or the header files Verilator includes, you must
-make the source code available under the GNU Lesser Public License.
-However, Verilator output (the Verilated code) only "include"s the licensed
-files, and so you are **not** required to open-source release any output
-from Verilator.
+Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own license.
+
+It's just like how using GCC on your programs does not change the copyright
+of your program; this is why Verilator uses the "GNU **Lesser** Public
+License Version 3" instead of the more typical "GNU Public License".  See
+the licenses for details.
+
+Some examples:
+
+* Any SystemVerilog or other input fed into Verilator remain your own.
+
+* Any of your VPI/DPI C++ routines that Verilator calls remain your own.
+
+* Any of your main() C++ code that calls into Verilator remain your own.
+
+* If you change Verilator itself, for example changing or adding a file
+  under the src/ directory in the repository, you must make the source code
+  available under the GNU Lesser Public License.
+
+* If you change a header Verilator provides, for example under include/ in
+  the repository, you must make the source code available under the GNU
+  Lesser Public License.
 
 You also have the option of using the Perl Artistic License, which again
-does not require you to release your Verilog or generated code, and also
-allows you to modify Verilator for internal use without distributing the
-modified version.  But please contribute back to the community!
+does not require you to release your Verilog, C++, or generated code. This
+license also allows you to modify Verilator for internal use without
+distributing the modified version.  But please contribute back to the
+community!
 
-One limit is that you cannot under either license release a closed-source
-Verilog simulation product incorporating Verilator. That is you can have a
-commercial product, but must make the source code available.
+Under both license you can offer a commercial product that is based on
+Verilator either directly or embedded within.  However under both licenses,
+any changes you make to Verilator for such a product must be open sourced.
 
 As is standard with Open Source, contributions back to Verilator will be
 placed under the Verilator copyright and LGPL/Artistic license.  Small test
@@ -118,9 +135,9 @@ A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C
 
 B. Or, for finer-grained control, or C++ files with multiple Verilated
    modules you may also create the trace purely from C++.  Create a
-   VerilatedVcdC object, and in your main loop call
-   ``trace_object->dump(time)`` every time step, and finally call
-   ``trace_object->close()``.
+   VerilatedVcdC object, and in your main loop right after ``eval()`` call
+   ``trace_object->dump(contextp->time())`` every time step, and finally
+   call ``trace_object->close()``.
 
    .. code-block:: C++
       :emphasize-lines: 1,5-8,12
@@ -128,15 +145,18 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
       #include "verilated_vcd_c.h"
       ...
       int main(int argc, char** argv, char** env) {
+          const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
           ...
           Verilated::traceEverOn(true);
           VerilatedVcdC* tfp = new VerilatedVcdC;
-          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
+          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy (or see below)
+          // tfp->dumpvars(1, "t");  // trace 1 level under "t"
           tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
           ...
-          while (Verilated::time() < sim_time && !Verilated::gotFinish()) {
-              Verilated::timeInc(1);
-              tfp->dump(main_time);
+          while (contextp->time() < sim_time && !contextp->gotFinish()) {
+              contextp->timeInc(1);
+              topp->eval();
+              tfp->dump(contextp->time());
           }
           tfp->close();
       }
@@ -349,8 +369,8 @@ also use the "import DPI" SystemVerilog feature to call C code (see the
 chapter above).  There is also limited VPI access to public signals.
 
 If you want something more complex, since Verilator emits standard C++
-code, you can simply write your own C++ routines that can access and modify
-signal values without needing any PLI interface code, and call it with
+code, you can write your own C++ routines that can access and modify signal
+values without needing any PLI interface code, and call it with
 $c("{any_c++_statement}").
 
 See the :ref:`Connecting` section.
@@ -385,7 +405,7 @@ How do I get faster build times?
   identical source builds, even across different users.  If ccache was
   installed when Verilator was built it is used, or see OBJCACHE
   environment variable to override this. Also see the
-  :vlopt:`--output-split` option.
+  :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`
 
 * To reduce the compile time of classes that use a Verilated module (e.g. a
   top CPP file) you may wish to add a
@@ -440,7 +460,7 @@ the signal, as you would any other member variable.
 Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
 64-bit unsigned long longs (uint64_t) that fits the width of the signal.
-Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for
+Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
 1 to 64 bits, and the compiler will properly up-convert smaller entities.
 Note even signed ports are declared as unsigned; you must sign extend
 yourself to the appropriate signal width.
@@ -477,7 +497,7 @@ by your code or you'll get strange results.
 Should a module be in Verilog or SystemC?
 """""""""""""""""""""""""""""""""""""""""
 
-Sometimes there is a block that just interconnects instances, and have a
+Sometimes there is a block that only interconnects instances, and have a
 choice as to if you write it in Verilog or SystemC.  Everything else being
 equal, best performance is when Verilator sees all of the design.  So, look
 at the hierarchy of your design, labeling instances as to if they are

docs/guide/files.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *****
@@ -54,32 +54,38 @@ For --cc/--sc, it creates:
      - Arguments for hierarchical Verilation (from --make gmake)
    * - *{prefix}*\ _hierCMakeArgs.f
      - Arguments for hierarchical Verilation (from --make cmake)
-   * - *{prefix}*\ .cpp
-     - Top level C++ file
-   * - *{prefix}{__n}*\ .cpp
-     - Additional top C++ files (from --output-split)
    * - *{prefix}*\ .h
-     - Top level header
-   * - *{prefix}*\ __Slow\ *{__n}*\ .cpp
+     - Model header
+   * - *{prefix}*\ .cpp
+     - Model C++ file
+   * - *{prefix}*\ ___024root.h
+     - Top level (SystemVerilog $root) internal header file
+   * - *{prefix}*\ ___024root.cpp
+     - Top level (SystemVerilog $root) internal C++ file
+   * - *{prefix}*___024root*{__n}*\ .cpp
+     - Additional top level internal C++ files (from --output-split)
+   * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
      - Infrequent cold routines
-   * - *{prefix}*\ __Dpi.cpp
-     - DPI import and export wrappers (from --dpi)
+   * - *{prefix}*\ ___024root__Trace{__n}*\ .cpp
+     - Wave file generation code (from --trace)
+   * - *{prefix}*\ ___024root__Trace__Slow{__n}*\ .cpp
+     - Wave file generation code (from --trace)
    * - *{prefix}*\ __Dpi.h
      - DPI import and export declarations (from --dpi)
+   * - *{prefix}*\ __Dpi.cpp
+     - Global DPI export wrappers (from --dpi)
+   * - *{prefix}*\ __Dpi_Export\ *{__n}*\ .cpp
+     - DPI export wrappers scoped to this particular model (from --dpi)
    * - *{prefix}*\ __Inlines.h
      - Inline support functions
-   * - *{prefix}*\ __Syms.cpp
-     - Global symbol table C++
    * - *{prefix}*\ __Syms.h
      - Global symbol table header
-   * - *{prefix}*\ __Trace{__n}*\ .cpp
-     - Wave file generation code (from --trace)
-   * - *{prefix}*\ __Trace__Slow{__n}*\ .cpp
-     - Wave file generation code (from --trace)
-   * - *{prefix}{each_verilog_module}*\ .cpp
-     - Lower level internal C++ files
+   * - *{prefix}*\ __Syms.cpp
+     - Global symbol table C++
    * - *{prefix}{each_verilog_module}*\ .h
      - Lower level internal header files
+   * - *{prefix}{each_verilog_module}*\ .cpp
+     - Lower level internal C++ files
    * - *{prefix}{each_verilog_module}{__n}*\ .cpp
      - Additional lower C++ files (from --output-split)
 
@@ -114,7 +120,7 @@ In certain debug and other modes, it also creates:
      - Debugging graph files (from --debug)
    * - *{prefix}{misc}*\ .tree
      - Debugging files (from --debug)
-   * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp
+   * - {mod_prefix}_{each_verilog_base_filename}*\ .vpp
      - Pre-processed verilog (from --debug)
 
 After running Make, the C++ compiler may produce the following:
@@ -139,3 +145,23 @@ After running Make, the C++ compiler may produce the following:
      - Intermediate dependencies
    * - *{prefix}{misc}*\ .o
      - Intermediate objects
+
+The Verilated executable may produce the following:
+
+.. list-table::
+
+   * - coverage.dat
+     - Code coverage output, and default input filename for :command:`verilator_coverage`
+   * - gmon.out
+     - GCC/clang code profiler output, often fed into :command:`verilator_profcfunc`
+   * - profile.vlt
+     - --prof-pgo data file for :ref:`Thread PGO`
+   * - profile_exec.dat
+     - --prof-exec data file for :command:`verilator_gantt`
+
+Verilator_gantt may produce the following:
+
+.. list-table::
+
+   * - profile_exec.vcd
+     - Gantt report waveform output

docs/guide/index.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ######################

docs/guide/install.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Installation:
@@ -23,6 +23,8 @@ package:
 
    apt-get install verilator   # On Ubuntu
 
+For other distributions refer to `Repology Verilator Distro Packages
+<https://repology.org/project/verilator>`__.
 
 .. _Git Install:
 
@@ -44,21 +46,20 @@ In brief, to install from git:
    #sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
 
    git clone https://github.com/verilator/verilator   # Only first time
-   ## Note the URL above is not a page you can see with a browser, it's for git only
 
    # Every time you need to build:
    unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
    unset VERILATOR_ROOT  # For bash
    cd verilator
-   git pull        # Make sure git repository is up-to-date
-   git tag         # See what versions exist
+   git pull         # Make sure git repository is up-to-date
+   git tag          # See what versions exist
    #git checkout master      # Use development branch (e.g. recent bug fixes)
    #git checkout stable      # Use most recent stable release
    #git checkout v{version}  # Switch to specified release version
 
-   autoconf        # Create ./configure script
-   ./configure     # Configure and create Makefile
-   make -j         # Build Verilator itself
+   autoconf         # Create ./configure script
+   ./configure      # Configure and create Makefile
+   make -j `nproc`  # Build Verilator itself (if error, try just 'make')
    sudo make install
 
 
@@ -76,17 +77,17 @@ OS Requirements
 ---------------
 
 Verilator is developed and has primary testing on Ubuntu, with additional
-testing on FreeBSD and Apple OS-X. Versions have also built on Redhat
-Linux, HPUX and Solaris. It should run with minor porting on any
-GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and
-Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator
-itself) compiles under all the options above, plus using MSVC++.
+testing on FreeBSD and Apple OS-X. Versions have also built on Red Hat
+Linux, and other flavors of GNU/Linux-ish platforms. Verilator also works
+on Windows Subsystem for Linux (WSL2), Windows under Cygwin, and Windows
+under MinGW (gcc -mno-cygwin). Verilated output (not Verilator itself)
+compiles under all the options above, plus using MSVC++.
 
 
 Install Prerequisites
 ---------------------
 
-To build or run Verilator you need these standard packages:
+To build or run Verilator, you need these standard packages:
 
 ::
 
@@ -97,13 +98,20 @@ To build or run Verilator you need these standard packages:
    sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)
    sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
 
-To build or run the following are optional but should be installed for good
-performance:
+To build or run Verilator, the following are optional but should be installed
+for good performance:
 
 ::
 
    sudo apt-get install ccache  # If present at build, needed for run
-   sudo apt-get install libgoogle-perftools-dev numactl perl-doc
+   sudo apt-get install libgoogle-perftools-dev numactl
+
+The following is optional but is recommended for nicely rendered command line
+help when running Verilator:
+
+::
+
+   sudo apt-get install perl-doc
 
 To build Verilator you will need to install these packages; these do not
 need to be present to run Verilator:
@@ -116,8 +124,9 @@ Those developing Verilator itself may also want these (see internals.rst):
 
 ::
 
-   sudo apt-get install gdb graphviz cmake clang clang-format gprof lcov
-   sudo pip3 install sphinx sphinx_rtd_theme breathe
+   sudo apt-get install gdb graphviz cmake clang clang-format-11 gprof lcov
+   sudo apt-get install yapf3
+   sudo pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe
    cpan install Pod::Perldoc
    cpan install Parallel::Forker
 
@@ -286,7 +295,7 @@ Compile Verilator:
 
 ::
 
-   make -j
+   make -j `nproc`  # Or if error on `nproc`, the number of CPUs in system
 
 
 Test

docs/guide/languages.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ***************
@@ -92,7 +92,7 @@ appropriate code to detect failing cases at simulation runtime and print an
 
 Verilator likewise also asserts any "unique" or "priority" SystemVerilog
 keywords on case statement, as well as "unique" on if statements.  However,
-"priority if" is currently simply ignored.
+"priority if" is currently ignored.
 
 
 .. _Language Limitations:
@@ -136,7 +136,7 @@ ___05F (5F is the hex code of an underscore.)
 Bind
 ----
 
-sVerilator only supports bind to a target module name, not to an
+Verilator only supports bind to a target module name, not to an
 instance path.
 
 
@@ -174,9 +174,9 @@ Structures and Unions
 ---------------------
 
 Presently Verilator only supports packed structs and packed unions.  Rand
-and randc tags on members are simply ignored.  All structures and unions
-are represented as a single vector, which means that generating one member
-of a structure from blocking, and another from non-blocking assignments is
+and randc tags on members are ignored.  All structures and unions are
+represented as a single vector, which means that generating one member of a
+structure from blocking, and another from non-blocking assignments is
 unsupported.
 
 
@@ -336,6 +336,24 @@ Verilator does not support SEREs yet.  All assertion and coverage
 statements must be simple expressions that complete in one cycle.
 
 
+Force statement
+---------------
+
+Verilator supports the procedural `force` (and corresponding `release`)
+statement. The behavior of the `force` statement however does not entirely
+comply with the IEEE 1800 SystemVerilog standard. According to the standard,
+when a procedural statement of the form `force a = b;` is executed, the
+simulation should behave as if from that point forwards, a continuous
+assignment `assign a = b;` have been added to override the drivers of `a`.
+More specifically: the value of `a` should be updated, whenever the value of
+`b` changes, all the way until a `release a;` statement is executed.
+Verilator instead evaluates the current value of `b` at the time the `force`
+statement is executed, and forces `a` to that value, without updating it
+until a new `force` or `release` statement is encountered that applies to
+`a`. This non-standard behavior is nevertheless consistent with some other
+simulators.
+
+
 Encrypted Verilog
 -----------------
 

docs/guide/overview.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 ********

docs/guide/simulating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. _Simulating:
@@ -26,7 +26,8 @@ risk of reset bugs in trade for performance; see the above documentation
 for these options.
 
 If using Verilated multithreaded, use ``numactl`` to ensure you are using
-non-conflicting hardware resources. See :ref:`Multithreading`.
+non-conflicting hardware resources. See :ref:`Multithreading`. Also
+consider using profile-guided optimization, see :ref:`Thread PGO`.
 
 Minor Verilog code changes can also give big wins.  You should not have any
 UNOPTFLAT warnings from Verilator.  Fixing these warnings can result in
@@ -93,9 +94,7 @@ cases, for example regressions, it is usually worth spending extra
 compilation time to reduce total CPU time.
 
 If you will be running many simulations on a single model, you can
-investigate profile guided optimization. With GCC, using GCC's
-"-fprofile-arcs", then GCC's "-fbranch-probabilities" will yield another
-15% or so.
+investigate profile guided optimization. See :ref:`Compiler PGO`.
 
 Modern compilers also support link-time optimization (LTO), which can help
 especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in
@@ -230,7 +229,7 @@ coverage point insertions into the model and collect the coverage data.
 
 To get the coverage data from the model, in the user wrapper code,
 typically at the end once a test passes, call
-:code:`Verilated::coveragep()->write` with an argument of the filename for
+:code:`Verilated::threadContextp()->coveragep()->write` with an argument of the filename for
 the coverage data file to write coverage data to (typically
 "logs/coverage.dat").
 
@@ -272,8 +271,6 @@ profiled C++ code functions.
 To use profiling:
 
 #. Use Verilator's :vlopt:`--prof-cfuncs`.
-#. Use Verilator's :vlopt:`-CFLAGS "-g -pg" <-CFLAGS>` to pass the
-   profiling flags through to GCC/Clang.
 #. Build and run the simulation model.
 #. The model will create gmon.out.
 #. Run :command:`gprof` to see where in the C++ code the time is spent.
@@ -282,23 +279,25 @@ To use profiling:
    is being spent.
 
 
-.. _Thread Profiling:
+.. _Execution Profiling:
 
-Thread Profiling
-================
+Execution Profiling
+===================
 
-When using multithreaded mode (:vlopt:`--threads`), it is useful to see
-statistics and visualize how well the multiple CPUs are being utilized.
+For performance optimization, it is useful to see statistics and visualize how
+execution time is distributed in a verilated model.
 
-With the :vlopt:`--prof-threads` option, Verilator will:
+With the :vlopt:`--prof-exec` option, Verilator will:
 
-* Add code to the Verilated model to record the start and end time of each
-  macro-task across a number of calls to eval. (What is a macro-task?  See
-  the Verilator internals document (:file:`docs/internals.rst` in the
-  distribution.)
+* Add code to the Verilated model to record execution flow.
 
 * Add code to save profiling data in non-human-friendly form to the file
-  specified with :vlopt:`+verilator+prof+threads+file+\<filename\>`.
+  specified with :vlopt:`+verilator+prof+exec+file+\<filename\>`.
+
+* In multi-threaded models, add code to record the start and end time of each
+  macro-task across a number of calls to eval. (What is a macro-task?  See the
+  Verilator internals document (:file:`docs/internals.rst` in the
+  distribution.)
 
 The :command:`verilator_gantt` program may then be run to transform the
 saved profiling file into a nicer visual format and produce some related
@@ -308,7 +307,7 @@ statistics.
 
    Example verilator_gantt output, as viewed with GTKWave.
 
-   The parallelism shows the number of CPUs being used at a given moment.
+   The measured_parallelism shows the number of CPUs being used at a given moment.
 
    The cpu_thread section shows which thread is executing on each of the physical CPUs.
 
@@ -316,6 +315,36 @@ statistics.
 
 For more information see :command:`verilator_gantt`.
 
+
+.. _Profiling ccache efficiency:
+
+Profiling ccache efficiency
+===========================
+
+The Verilator generated Makefile provides support for basic profiling of
+ccache behavior during the build. This can be used to track down files that
+might be unnecessarily rebuilt, though as of today even small code changes
+will usually require rebuilding a large number of files. Improving ccache
+efficiency during the edit/compile/test loop is an active area of
+development.
+
+To get a basic report of how well ccache is doing, add the `ccache-report`
+target when invoking the generated Makefile:
+
+.. code-block:: bash
+
+     make -C obj_dir -f Vout.mk Vout ccache-report
+
+This will print a report based on all executions of ccache during this
+invocation of Make. The report is also written to a file, in this example
+`obj_dir/Vout__cache_report.txt`.
+
+To use the `ccache-report` target, at least one other explicit build target
+must be specified, and OBJCACHE must be set to 'ccache'.
+
+This feature is currently experimental and might change in subsequent
+releases.
+
 .. _Save/Restore:
 
 Save/Restore
@@ -350,3 +379,121 @@ For example:
          os >> main_time;
          os >> *topp;
      }
+
+
+Profile-Guided Optimization
+===========================
+
+Profile-guided optimization is the technique where profiling data is
+collected by running your simulation executable, then this information is
+used to guide the next Verilation or compilation.
+
+There are two forms of profile-guided optimizations.  Unfortunately for
+best results they must each be performed from the highest level code to the
+lowest, which means performing them separately and in this order:
+
+* :ref:`Thread PGO`
+* :ref:`Compiler PGO`
+
+Other forms of PGO may be supported in the future, such as clock and reset
+toggle rate PGO, branch prediction PGO, statement execution time PGO, or
+others as they prove beneficial.
+
+
+.. _Thread PGO:
+
+Thread Profile-Guided Optimization
+----------------------------------
+
+Verilator supports profile-guided optimization (Verilation) of multi-threaded
+models (Thread PGO) to improve performance.
+
+When using multithreading, Verilator computes how long macro tasks take and
+tries to balance those across threads.  (What is a macro-task?  See the
+Verilator internals document (:file:`docs/internals.rst` in the
+distribution.)  If the estimations are incorrect, the threads will not be
+balanced, leading to decreased performance.  Thread PGO allows collecting
+profiling data to replace the estimates and better optimize these
+decisions.
+
+To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option. This
+will code to the verilated model to save profiling data for profile-guided
+optimization.
+
+Run the model executable. When the executable exits, it will create a
+profile.vlt file.
+
+Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option,
+and adding the profile.vlt generated earlier to the command line.
+
+Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
+profile data file (profile.vlt) can be placed on the verilator command line
+directly without any prefix.
+
+If results from multiple simulations are to be used in generating the
+optimization, multiple simulation's profile.vlt may be concatenated
+externally, or each of the files may be fed as separate command line
+options into Verilator.  Verilator will sum the profile results, so a
+longer running test will have proportionally more weight for optimization
+than a shorter running test.
+
+If you provide any profile feedback data to Verilator, and it cannot use
+it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
+scheduled using estimated costs.  This usually indicates that the profile
+data was generated from different Verilog source code than Verilator is
+currently running against. Therefore, repeat the data collection phase to
+create new profiling data, then rerun Verilator with the same input source
+files and that new profiling data.
+
+
+.. _Compiler PGO:
+
+Compiler Profile-Guided Optimization
+------------------------------------
+
+GCC and Clang support compiler profile-guided optimization (PGO). This
+optimizes any C/C++ program including Verilated code.  Using compiler PGO
+typically yields improvements of 5-15% on both single-threaded and
+multi-threaded models.
+
+To use compiler PGO with GCC or Clang, please see the appropriate compiler
+documentation.  The process in GCC 10 was as follows:
+
+1. Compile the Verilated model with the compiler's "-fprofile-generate"
+   flag:
+
+   .. code-block:: bash
+
+      verilator [whatever_flags] --make \
+          -CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate
+
+   or, if calling make yourself, add -fprofile-generate appropriately to your
+   Makefile.
+
+2. Run your simulation. This will create \*.gcda file(s) in the same
+   directory as the source files.
+
+3. Recompile the model with -fprofile-use. The compiler will read the
+   \*.gcda file(s).
+
+   For GCC:
+
+   .. code-block:: bash
+
+      verilator [whatever_flags] --build \
+          -CFLAGS "-fprofile-use -fprofile-correction"
+
+   For Clang:
+
+   .. code-block:: bash
+
+      llvm-profdata merge -output default.profdata *.profraw
+      verilator [whatever_flags] --build \
+          -CFLAGS "-fprofile-use -fprofile-correction"
+
+   or, if calling make yourself, add these CFLAGS switches appropriately to
+   your Makefile.
+
+Clang and GCC also support -fauto-profile which uses sample-based
+feedback-directed optimization.  See the appropriate compiler
+documentation.

docs/guide/verilating.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 **********
@@ -68,12 +68,11 @@ multi-core SoC.
 
 Verilator is run in hierarchical mode on the whole SoC.  Verilator will
 make two models, one for the CPU hierarchy block, and one for the SoC.  The
-Verialted code for the SoC will automatically call the CPU Verilated model.
+Verilated code for the SoC will automatically call the CPU Verilated model.
 
-The current hierarchical Verilation is based on protect-lib. Each hierarchy
-block is Verilated to a protect-lib. User modules of the hierarchy blocks
-will see a tiny wrapper generated by protect-lib instead of the actual
-design.
+The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
+hierarchy block is Verilated into a library. User modules of the hierarchy
+blocks will see a tiny wrapper generated by :vlopt:`--lib-create`.
 
 
 Usage
@@ -216,9 +215,19 @@ be done by a "main thread". In most cases the eval thread and main thread
 are the same thread (i.e. the user's top C++ testbench runs on a single
 thread), but this is not required.
 
-The :vlopt:`--trace-threads` options can be used to produce trace dumps
-using multiple threads. If :vlopt:`--trace-threads` is set without
-:vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
+When making frequent use of DPI imported functions in a multi-threaded
+model, it may be beneficial to performance to adjust the
+:vlopt:`--instr-count-dpi` option based on some experimentation. This
+influences the partitioning of the model by adjusting the assumed execution
+time of DPI imports.
+
+When using :vlopt:`--trace` to perform VCD tracing, the VCD trace
+construction is parallelized using the same number of threads as specified
+with :vlopt:`--threads`, and is executed on the same thread pool as the model.
+
+The :vlopt:`--trace-threads` options can be used with :vlopt:`--trace-fst`
+to offload FST tracing using multiple threads. If :vlopt:`--trace-threads` is
+given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
 :vlopt:`--threads 1 <--threads>`, i.e.: the support libraries will be
 thread safe.
 
@@ -226,12 +235,12 @@ With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced
 on the main thread. This again gives the highest single thread performance.
 
 With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1,
-N additional threads will be created and managed by the trace files (e.g.:
-VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main
-thread will be released to proceed with execution as soon as possible,
-though some blocking of the main thread is still necessary while capturing
-the trace. Different trace formats can utilize a various number of
-threads. See the :vlopt:`--trace-threads` option.
+up to N additional threads will be created and managed by the trace files
+(e.g.: VerilatedFstC), to offload construction of the trace dump. The main
+thread will be released to proceed with execution as soon as possible, though
+some blocking of the main thread is still necessary while capturing the
+trace. FST tracing can utilize up to 2 offload threads, so there is no use
+of setting :vlopt:`--trace-threads` higher than 2 at the moment.
 
 When running a multithreaded model, the default Linux task scheduler often
 works against the model, by assuming threads are short lived, and thus
@@ -260,7 +269,7 @@ This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
 (presumably on socket 0) optimizing performance.  Of course this must be
 adjusted if you want another simulator using e.g. socket 1, or if you
 Verilated with a different number of threads.  To see what CPUs are
-actually used, use :vlopt:`--prof-threads`.
+actually used, use :vlopt:`--prof-exec`.
 
 
 Multithreaded Verilog and Library Support
@@ -360,7 +369,8 @@ Verilate in CMake
      verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name]
               [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE]
               [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...]
-              [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...])
+              [OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
+              [TRACE_THREADS num] [VERILATOR_ARGS ...])
 
 Lowercase and ... should be replaced with arguments, the uppercase parts
 delimit the arguments and can be passed in any order, or left out entirely
@@ -429,6 +439,15 @@ SystemC include directories and link to the SystemC libraries.
    the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS
    environment variable.
 
+.. describe:: THREADS
+
+   Optional. Generated a multi-threaded model, same as "--threads".
+
+.. describe:: TRACE_THREADS
+
+   Optional. Generated multi-threaded FST trace dumping, same as
+   "--trace-threads".
+
 .. describe:: TOP_MODULE
 
    Optional. Sets the name of the top module. Defaults to the name of the

docs/guide/warnings.rst

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 *******************
@@ -12,7 +12,7 @@ Disabling Warnings
 Warnings may be disabled in multiple ways:
 
 #. Disable the warning in the source code.  When the warning is printed it
-   will include a warning code.  Simply surround the offending line with a
+   will include a warning code.  Surround the offending line with a
    :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/`
    metacomment pair:
 
@@ -128,6 +128,14 @@ List Of Warnings
    simulate correctly.
 
 
+.. option:: BADSTDPRAGMA
+
+   Error that a pragma is badly formed, when that pragma is defined by IEEE
+   1800-2017.  For example, an empty pragma line, or an incorrect specified
+   'pragma protect'.  Note that 3rd party pragmas not defined by IEEE
+   1800-2017 are ignored.
+
+
 .. option:: BLKANDNBLK
 
    .. TODO better example
@@ -154,7 +162,7 @@ List Of Warnings
          always @(posedge clk)  foo[0] <= ...
          always_comb foo[1] = ...
 
-   Simply use a different register for the flop:
+   Instead use a different register for the flop:
 
    .. code-block:: sv
 
@@ -276,7 +284,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that it is simply better style to use casez, and "?" in place of
+   Warns that it is better style to use casez, and "?" in place of
    "x"'s.  See
    `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf
    <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>`_
@@ -439,7 +447,7 @@ List Of Warnings
               p0();
          endmodule
 
-   Other tools with similar warnings: Veriable's forbid_defparam_rule.
+   Other tools with similar warnings: Verible's forbid_defparam_rule.
 
 
 .. option:: DEPRECATED
@@ -474,39 +482,44 @@ List Of Warnings
 
    Faulty example:
 
-   .. code-block:: sv
+   .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_faulty.rst
 
-         always_comb b = ~a;
-         always_comb a = b
+   Results in at runtime (not when Verilated):
 
-   This code will toggle forever, and thus to prevent an infinite loop, the
-   executable will give the didn't converge error.
+   .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst
 
-   To debug this, first review any UNOPTFLAT warnings that were ignored.
-   Though typically it is safe to ignore UNOPTFLAT (at a performance cost),
-   at the time of issuing a UNOPTFLAT Verilator did not know if the logic
-   would eventually converge and assumed it would.
+   This is because the signals keep toggling even with out time
+   passing. Thus to prevent an infinite loop, the Verilated executable
+   gives the DIDNOTCONVERGE error.
+
+   To debug this, first review any UNOPT or UNOPTFLAT warnings that were
+   ignored.  Though typically it is safe to ignore UNOPTFLAT (at a
+   performance cost), at the time of issuing a UNOPTFLAT Verilator did not
+   know if the logic would eventually converge and assumed it would.
 
    Next, run Verilator with :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG
    <--prof-cfuncs>`.  Rerun the test.  Now just before the convergence
    error you should see additional output similar to this:
 
-   .. code-block::
+   .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_msg.rst
 
-         CHANGE: filename.v:1: b
-         CHANGE: filename.v:2: a
-
-   This means that signal b and signal a keep changing, inspect the code
-   that modifies these signals.  Note if many signals are getting printed
-   then most likely all of them are oscillating.  It may also be that
-   e.g. "a" may be oscillating, then "a" feeds signal "c" which then is
-   also reported as oscillating.
+   The CHANGE line means that on the given filename and line number that
+   drove a signal, the signal 'a' kept changing. Inspect the code that
+   modifies these signals.  Note if many signals are getting printed then
+   most likely all of them are oscillating.  It may also be that e.g. "a"
+   may be oscillating, then "a" feeds signal "c" which then is also
+   reported as oscillating.
 
    One way DIDNOTCONVERGE may occur is flops are built out of gate
-   primitives.  error. Verilator does not support building flops or latches
-   out of gate primitives, and any such code must change to use behavioral
+   primitives. Verilator does not support building flops or latches out of
+   gate primitives, and any such code must change to use behavioral
    constructs (e.g. always_ff and always_latch).
 
+   Another way DIDNOTCONVERGE may occur is if # delays are used to generate
+   clocks.  Verilator ignores the delays and gives an :option:`ASSIGNDLY`
+   or :option:`STMTDLY` warning.  If these were suppressed, due to the
+   absence of the delay, the code may now oscillate.
+
    Finally, rare, more difficult cases can be debugged like a C++ program;
    either enter :command:`gdb` and use its tracing facilities, or edit the
    generated C++ code to add appropriate prints to see what is going on.
@@ -515,7 +528,7 @@ List Of Warnings
 .. option:: ENDCAPSULATED
 
    Warns that a class member is declared is local or protected, but is
-   being accessed from outside that class (if local) or a derrived class
+   being accessed from outside that class (if local) or a derived class
    (if protected).
 
    Ignoring this warning will only suppress the lint check, it will
@@ -565,7 +578,7 @@ List Of Warnings
    must end in newline, as otherwise for example :command:`cat` with the
    file as an argument may produce undesirable results.
 
-   Repair by adding a newline to the end of the file.
+   Repair by appending a newline to the end of the file.
 
    Disabled by default as this is a code style warning; it will simulate
    correctly.
@@ -785,8 +798,8 @@ List Of Warnings
    .. TODO better example
 
    Warns that a module has multiple definitions.  Generally this indicates
-   a coding error, or a mistake in a library file and it's good practice to
-   have one module per file (and only put each file once on the command
+   a coding error, or a mistake in a library file, and it's good practice
+   to have one module per file (and only put each file once on the command
    line) to avoid these issues.  For some gate level netlists duplicates
    are sometimes unavoidable, and MODDUP should be disabled.
 
@@ -796,15 +809,25 @@ List Of Warnings
 
 .. option:: MULTIDRIVEN
 
-   .. TODO better example
+   Warns that the specified signal comes from multiple always blocks each
+   with different clocking. This warning does not look at individual bits
+   (see example below).
 
-   Warns that the specified signal comes from multiple always blocks.  This
-   is often unsupported by synthesis tools, and is considered bad style.
-   It will also cause longer simulation runtimes due to reduced
-   optimizations.
+   This is considered bad style, as the consumer of a given signal may be
+   unaware of the inconsistent clocking, causing clock domain crossing
+   or timing bugs.
+
+   Faulty example:
+
+   .. include:: ../../docs/gen/ex_MULTIDRIVEN_faulty.rst
+
+   Results in:
+
+   .. include:: ../../docs/gen/ex_MULTIDRIVEN_msg.rst
 
    Ignoring this warning will only slow simulations, it will simulate
-   correctly.
+   correctly.  It may however cause longer simulation runtimes due to
+   reduced optimizations.
 
 
 .. option:: MULTITOP
@@ -901,7 +924,7 @@ List Of Warnings
    simulate correctly.
 
    Other tools with similar warnings: Icarus Verilog's portbind, "warning:
-   Instantiating module ... with dangling impot port (...)". Slang's
+   Instantiating module ... with dangling input port (...)". Slang's
    unconnected-port, "port '...' has no connection".
 
 
@@ -988,6 +1011,32 @@ List Of Warnings
    a var/reg must be used as the target of procedural assignments.
 
 
+.. option:: PROFOUTOFDATE
+
+   Warns that threads were scheduled using estimated costs, despite the
+   fact that data was provided from profile-guided optimization (see
+   :ref:`Thread PGO`) as fed into Verilator using the
+   :option:`profile_data` configuration file option.  This usually
+   indicates that the profile data was generated from different Verilog
+   source code than Verilator is currently running against.
+
+   It is recommended to create new profiling data, then rerun Verilator
+   with the same input source files and that new profiling data.
+
+   Ignoring this warning may only slow simulations, it will simulate
+   correctly.
+
+
+.. option:: PROTECTED
+
+   Warning that a 'pragma protected' section was encountered. The code
+   inside the protected region will be partly checked for correctness, but is
+   otherwise ignored.
+
+   Suppressing the warning may make Verilator differ from a simulator that
+   accepts the protected code.
+
+
 .. option:: RANDC
 
    Warns that the :code:`randc` keyword is currently unsupported, and that
@@ -1156,9 +1205,25 @@ List Of Warnings
 
    Faulty example:
 
-   .. code-block:: sv
+   .. include:: ../../docs/gen/ex_STMTDLY_faulty.rst
 
-         #100 $finish;  //<--- Warning
+   Results in:
+
+   .. include:: ../../docs/gen/ex_STMTDLY_msg.rst
+
+   This is a warning because Verilator does not support delayed statements.
+   It will ignore all such delays.  In many cases ignoring a delay might be
+   harmless, but if the delayed statement is, as in this example, used to
+   cause some important action at a later time, it might be an important
+   difference.
+
+   Some possible workarounds:
+
+   * Move the delayed statement into the C++ wrapper file, where the
+     stimulus and clock generation can be done in C++.
+
+   * Convert the statement into a FSM, or other statement that tests
+     against $time.
 
 
 .. option:: SYMRSVDWORD
@@ -1326,7 +1391,9 @@ List Of Warnings
 
    Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by
    synthesis which analyzes interconnection per-bit, but is circular to
-   simulation which analyzes per-bus:
+   simulation which analyzes per-bus.
+
+   Faulty example:
 
    .. code-block:: sv
 
@@ -1439,9 +1506,16 @@ List Of Warnings
    Error that a construct might be legal according to IEEE but is not
    currently supported by Verilator.
 
+   A typical workaround is to rewrite the construct into a simpler and more
+   common alternative language construct.
+
+   Alternatively, check if the construct is supported by other tools, and
+   if so please consider submitting a github pull request against the
+   Verilator sources to implement the missing unsupported feature.
+
    This error may be ignored with :vlopt:`--bbox-unsup`, however this will
-   make the design simulate incorrectly; see the details under
-   :vlopt:`--bbox-unsup`.
+   make the design simulate incorrectly and is only intended for lint
+   usage; see the details under :vlopt:`--bbox-unsup`.
 
 
 .. option:: UNUSED
@@ -1571,7 +1645,7 @@ List Of Warnings
    * A part select has a different size then needed to index into the
      packed or unpacked array (etc).
 
-   Verilator for attempts to track the minimum width of unsized constants
+   Verilator attempts to track the minimum width of unsized constants
    and will suppress the warning when the minimum width is appropriate to
    fit the required size.
 
@@ -1580,11 +1654,13 @@ List Of Warnings
 
    The recommendation is to fix these issues by:
 
-   * Resizing the variable or constant.  E.g. :code:`2'd2` instead of :code:`3'd2`.
+   * Resizing the variable or constant to match the needed size for the
+     expression.  E.g. :code:`2'd2` instead of :code:`3'd2`.
 
-   * Using :code:`'0` or :code:`'1`.
+   * Using :code:`'0` or :code:`'1` which automatically resize in an
+     expression.
 
-   * Using part select to narrow a variable. E.g. :code:`too_wide[1:0]`.
+   * Using part selects to narrow a variable. E.g. :code:`too_wide[1:0]`.
 
    * Using concatenate to widen a variable. E.g. :code:`{1'b1, too_narrow}`.
 

docs/internals.rst

@@ -114,11 +114,11 @@ By convention, each function/method uses the variable ``nodep`` as a
 pointer to the ``AstNode`` currently being processed.
 
 
-``AstNVisitor``
+``VNVisitor``
 ^^^^^^^^^^^^^^^
 
 The passes are implemented by AST visitor classes. These are implemented by
-subclasses of the abstract class, ``AstNVisitor``. Each pass creates an
+subclasses of the abstract class, ``VNVisitor``. Each pass creates an
 instance of the visitor class, which in turn implements a method to perform
 the pass.
 
@@ -268,13 +268,13 @@ Estimating Logic Costs
 
 To compute the cost of any given path through the graph, Verilator
 estimates an execution cost for each task. Each macro-task has an execution
-cost which is simply the sum of its tasks' costs. We assume that
-communication overhead and synchronization overhead are zero, so the cost
-of any given path through the graph is simply the sum of macro-task
-execution costs. Sarkar does almost the same thing, except that he has
-nonzero estimates for synchronization costs.
+cost which is the sum of its tasks' costs. We assume that communication
+overhead and synchronization overhead are zero, so the cost of any given
+path through the graph is the sum of macro-task execution costs. Sarkar
+does almost the same thing, except that he has nonzero estimates for
+synchronization costs.
 
-Verilator's cost estimates are assigned by ``InstrCountCostVisitor``.  This
+Verilator's cost estimates are assigned by ``InstrCountVisitor``.  This
 class is perhaps the most fragile piece of the multithread
 implementation. It's easy to have a bug where you count something cheap
 (eg. accessing one element of a huge array) as if it were expensive (eg.
@@ -301,7 +301,7 @@ prerequisites on other threads have finished.
 
 The synchronization cost is cheap if the prereqs are done. If they're not,
 fragmentation (idle CPU cores waiting) is possible. This is the major
-source of overhead in this approach. The ``--prof-threads`` switch and the
+source of overhead in this approach. The ``--prof-exec`` switch and the
 ``verilator_gantt`` script can visualize the time lost to such
 fragmentation.
 
@@ -405,6 +405,9 @@ routines in the sources to rely more heavily on randomness, and
 generally try harder not to keep input nodes together when we have the
 option to scramble things.
 
+Profile-guided optimization make this a bit better, by adjusting mtask
+scheduling, but this does not yet guide the packing into mtasks.
+
 
 Performance Regression
 """"""""""""""""""""""
@@ -502,7 +505,7 @@ Some of the code implementing passes is extremely repetitive, and must be
 implemented for each sub-class of ``AstNode``. However, while repetitive,
 there is more variability than can be handled in C++ macros.
 
-In Verilator this is implemented by using a Perl script, ``astgen`` to
+In Verilator this is implemented by using a script, ``astgen`` to
 pre-process the C++ code. For example in ``V3Const.cpp`` this is used to
 implement the ``visit()`` functions for each binary operation using the
 ``TREEOP`` macro.
@@ -520,10 +523,10 @@ optimization passes. This allows separation of the pass algorithm from the
 AST on which it operates. Wikipedia provides an introduction to the concept
 at https://en.wikipedia.org/wiki/Visitor_pattern.
 
-As noted above, all visitors are derived classes of ``AstNVisitor``. All
+As noted above, all visitors are derived classes of ``VNVisitor``. All
 derived classes of ``AstNode`` implement the ``accept`` method, which takes
-as argument a reference to an instance or a ``AstNVisitor`` derived class
-and applies the visit method of the ``AstNVisitor`` to the invoking AstNode
+as argument a reference to an instance or a ``VNVisitor`` derived class
+and applies the visit method of the ``VNVisitor`` to the invoking AstNode
 instance (i.e. ``this``).
 
 One possible difficulty is that a call to ``accept`` may perform an edit
@@ -601,8 +604,8 @@ There are three ways data is passed between visitor functions.
 Iterators
 ---------
 
-``AstNVisitor`` provides a set of iterators to facilitate walking over
-the tree. Each operates on the current ``AstNVisitor`` class (as this)
+``VNVisitor`` provides a set of iterators to facilitate walking over
+the tree. Each operates on the current ``VNVisitor`` class (as this)
 and takes an argument type ``AstNode*``.
 
 ``iterate``
@@ -750,8 +753,8 @@ test. For run-time tests, this is followed by a call to the ``execute``
 subroutine. Both of these functions can optionally be provided with a hash
 table as argument specifying additional options.
 
-The test driver assumes by default that the source Verilog file name
-matches the PERL driver name. So a test whose driver is
+The driver.pl script assumes by default that the source Verilog file name
+matches the test script name. So a test whose driver is
 ``t/t_mytest.pl`` will expect a Verilog source file ``t/t_mytest.v``.
 This can be changed using the ``top_filename`` subroutine, for example
 
@@ -814,7 +817,7 @@ which you can install using cpan.
 
 There are some traps to avoid when running regression tests
 
-- When checking the MANIFEST, the test will barf on unexpected code in the
+- When checking the MANIFEST, the test will fail on unexpected code in the
   Verilator tree. So make sure to keep any such code outside the tree.
 
 - Not all Linux systems install Perldoc by default. This is needed for the
@@ -1180,10 +1183,10 @@ Verilator ideally would support all of IEEE, and has the goal to get close
 to full support. However the following IEEE sections and features are not
 anticipated to be ever implemented for the reasons indicated.
 
-IEEE 1800-2017 3.3 recursive modules
+IEEE 1800-2017 3.3 modules within modules
     Little/no tool support, and arguably not a good practice.
 IEEE 1800-2017 6.12 "shortreal"
-    Little/no tool support, and easily simply promoted to real.
+    Little/no tool support, and easily promoted to real.
 IEEE 1800-2017 11.11 Min, typ, max
     No SDF support so will always use typical.
 IEEE 1800-2017 11.12 "let"
@@ -1205,7 +1208,7 @@ IEEE 1800-2017 33 Config
 Distribution
 ============
 
-Copyright 2008-2021 by Wilson Snyder. Verilator is free software; you can
+Copyright 2008-2022 by Wilson Snyder. Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
 

docs/spelling.txt

@@ -2,9 +2,11 @@ ABCp
 Accellera
 Affe
 Aleksander
+Alexandre
 Ami
 Amir
 Anastasiadis
+Anikin
 Antonin
 Antwerpen
 Arasanipalai
@@ -70,6 +72,7 @@ Eda
 Eddleston
 Egbert
 Egil
+Ehab
 Eiler
 Eivind
 El
@@ -82,6 +85,7 @@ Fabrizio
 Fekete
 Ferrandi
 Flachs
+Flavien
 Foletto
 Forker
 Francillon
@@ -104,6 +108,7 @@ Goessling
 Gonnen
 Goorah
 Gossner
+Graybeal
 Grobman
 Gunter
 Guo
@@ -121,6 +126,7 @@ Hornung
 Hossell
 Hsu
 Hyperthreading
+Ibrahim
 Iles
 Inlines
 Inout
@@ -134,6 +140,7 @@ Jannis
 Jens
 Jeras
 Jiuyang
+Joannou
 Joly
 Jullien
 Junji
@@ -147,6 +154,7 @@ Kamendje
 Kandadi
 Kaplan
 Karge
+Karlsson
 Katz
 Katzman
 Keren
@@ -161,6 +169,7 @@ Kolecki
 Koonce
 Korteland
 Koszek
+Kouping
 Kravitz
 Krolnik
 Kruse
@@ -194,6 +203,7 @@ Mednick
 Michiels
 Microsystems
 Milanovic
+Millis
 MinW
 Mindspeed
 Miodrag
@@ -224,12 +234,14 @@ Petr
 Piechotka
 Piersall
 Plunkett
+Popolon
 Popov
 Prabhat
 Prabhu
 Prateek
 Pre
 Preprocess
+Pretet
 Priyadharshini
 Pullup
 Pulver
@@ -262,12 +274,15 @@ Shi
 Shinkarovsky
 Shirakawa
 Shuba
+Shunyao
 Slatter
 SoC
 Sobhan
 Sokorac
 Solaris
 Solomatnikov
+Solt
+Southwell
 Srini
 Stamness
 Stephane
@@ -286,6 +301,7 @@ SystemVerilog
 Takatsukasa
 Tambe
 Tariq
+Tejada
 Tengstrand
 Terpstra
 Thiede
@@ -293,8 +309,10 @@ Thierry
 Thyer
 Tichelaar
 Tomov
+Tood
 Topa
 Tota
+Trefor
 Tresidder
 Tri
 Tristate
@@ -304,11 +322,13 @@ Ubixum
 Uints
 Undefines
 Unsized
+Urbach
 Uselib
 Usha
 Usuario
 VERILATOR
 Vasu
+Vdeeptemp
 Vdly
 Vemumtab
 Vemuri
@@ -351,7 +371,9 @@ Zhang
 abirkmanis
 accessor
 accessors
+adrienlemasle
 agrobman
+ahouska
 al
 ala
 andit
@@ -372,8 +394,12 @@ backtrace
 backtraces
 basename
 bbox
+benchmarking
 biguint
 biops
+bitOpTree
+bitOpTree
+bitop
 bitstoreal
 blackbox
 bokke
@@ -389,6 +415,7 @@ casez
 casted
 cb
 ccache
+ccall
 cdc
 ceil
 celldefine
@@ -411,6 +438,8 @@ concat
 concats
 config
 const
+constexpr
+constpool
 coredump
 countbits
 countones
@@ -426,6 +455,7 @@ da
 dat
 datadir
 datafiles
+david
 ddd
 deassign
 debugi
@@ -434,6 +464,7 @@ defname
 defparam
 demangling
 der
+dereference
 desassign
 destructor
 detections
@@ -462,6 +493,7 @@ dumpvars
 dut
 dx
 elab
+elike
 elsif
 endcase
 endcelldefine
@@ -480,15 +512,18 @@ enums
 env
 envvar
 eof
+errae
 erroring
 et
 eval
+evals
 exe
 executables
 expr
 extern
 fanin
 fasttrace
+fauto
 fbranch
 fclose
 fdisplay
@@ -503,6 +538,7 @@ filt
 flto
 flushCall
 fopen
+forceable
 foreach
 fprintf
 fprofile
@@ -521,6 +557,7 @@ funcs
 fwrite
 gantt
 gcc
+gcda
 gdb
 genblk
 genvar
@@ -552,6 +589,7 @@ incdir
 includer
 inferfaces
 inhibitSim
+initarray
 initializer
 initializers
 inits
@@ -570,6 +608,7 @@ killua
 lang
 lcov
 ld
+leavinel
 len
 libext
 libgoogle
@@ -584,6 +623,7 @@ ln
 loc
 localparam
 localparams
+localtime
 logicals
 longint
 lsb
@@ -618,6 +658,7 @@ multithreaded
 multithreading
 mutexes
 mux
+myftptoyman
 mysignal
 namespace
 nand
@@ -642,15 +683,19 @@ onehot
 ooo
 oprofile
 oversubscription
+parallelized
 param
 parameterized
 params
 parens
+pawel
 pc
 pdf
 perf
 perftools
+pgo
 picoChip
+pinIndex
 pinout
 plusargs
 pmos
@@ -676,7 +721,7 @@ prev
 printf
 printtimescale
 profcfunc
-profcfuncs
+profiler
 prototyptes
 ps
 pthread
@@ -704,12 +749,14 @@ regs
 reloop
 resetall
 respecified
+rodata
 rr
 rst
 runtime
 runtimes
 rw
 sVerilator
+sawatzke
 sc
 scalared
 sccanf
@@ -725,6 +772,7 @@ specparam
 splitme
 spp
 sqrt
+src
 srcdir
 srcfile
 sscanf
@@ -744,6 +792,7 @@ subcells
 subexpressions
 submodule
 submodules
+substring
 sv
 svBitVal
 svBitVecVal
@@ -778,6 +827,7 @@ trunc
 txt
 typ
 typedef
+typedef'ed
 typedefed
 typedefs
 typename
@@ -791,6 +841,7 @@ uniquified
 unistd
 unlink
 unlinked
+unnamedblk
 unopt
 unoptflat
 unoptimizable
@@ -840,11 +891,14 @@ writeme
 writemem
 writememb
 writememh
+xiak
 xin
 xml
 xnor
 xout
 xuejiazidi
 yanx
+ypq
 yurivict
 zdave
+Øyvind

docs/xml.rst

@@ -46,9 +46,6 @@ The XML document consists of 4 sections within the top level
    hierarchy. Each instance is represented with the ``<cell>`` element
    with the following attributes:
 
-   -  ``fl`` (deprecated): The file id and line number where the module
-      was instanced. Use ``loc`` instead.
-
    -  ``loc``: The file id, first line number, last line number, first
       column number and last column number of the identifier where the
       module was instanced, separated by commas.
@@ -73,7 +70,7 @@ The XML document consists of 4 sections within the top level
 Distribution
 ============
 
-Copyright 2020-2021 by Wilson Snyder. Verilator is free software; you can
+Copyright 2020-2022 by Wilson Snyder. Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
 

examples/cmake_hello_sc/CMakeLists.txt

@@ -20,7 +20,7 @@
 # cmake --build .
 
 cmake_minimum_required(VERSION 3.8)
-project(cmake_hello_sc)
+project(cmake_hello_sc CXX)
 
 find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT})
 if (NOT verilator_FOUND)
@@ -37,6 +37,11 @@ find_package(SystemCLanguage QUIET)
 # Create a new executable target that will contain all your sources
 add_executable(example ../make_hello_sc/sc_main.cpp)
 
+set_property(
+  TARGET example
+  PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD}
+  )
+
 # Add the Verilated circuit to the target
 verilate(example SYSTEMC
   INCLUDE_DIRS "../make_hello_sc"

examples/cmake_hello_sc/Makefile

@@ -99,7 +99,7 @@ run:
 
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/cmake_tracing_sc."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
 
 clean mostlyclean distclean maintainer-clean:
 	@rm -rf build logs

examples/cmake_tracing_c/CMakeLists.txt

@@ -33,5 +33,5 @@ add_executable(example ../make_tracing_c/sim_main.cpp)
 # Add the Verilated circuit to the target
 verilate(example COVERAGE TRACE
   INCLUDE_DIRS "../make_tracing_c"
-  VERILATOR_ARGS -f ../make_tracing_c/input.vc -Os -x-assign 0
+  VERILATOR_ARGS -f ../make_tracing_c/input.vc -x-assign fast
   SOURCES ../make_tracing_c/top.v)

examples/cmake_tracing_sc/CMakeLists.txt

@@ -20,7 +20,7 @@
 # cmake --build .
 
 cmake_minimum_required(VERSION 3.8)
-project(cmake_tracing_sc_example)
+project(cmake_tracing_sc_example CXX)
 
 find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT})
 if (NOT verilator_FOUND)
@@ -37,10 +37,15 @@ find_package(SystemCLanguage QUIET)
 # Create a new executable target that will contain all your sources
 add_executable(example ../make_tracing_sc/sc_main.cpp)
 
+set_property(
+  TARGET example
+  PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD}
+  )
+
 # Add the Verilated circuit to the target
 verilate(example SYSTEMC COVERAGE TRACE
   INCLUDE_DIRS "../make_tracing_sc"
-  VERILATOR_ARGS -f ../make_tracing_sc/input.vc -Os -x-assign 0
+  VERILATOR_ARGS -f ../make_tracing_sc/input.vc -x-assign fast
   SOURCES ../make_tracing_sc/top.v)
 
 verilator_link_systemc(example)

examples/make_hello_c/Makefile

@@ -40,7 +40,7 @@ default:
 	obj_dir/Vtop
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/make_tracing_c."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
 
 ######################################################################
 

examples/make_hello_c/top.v

@@ -4,7 +4,8 @@
 // any use, without warranty, 2017 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top;
    initial begin
       $display("Hello World!");

examples/make_hello_sc/Makefile

@@ -49,7 +49,7 @@ run:
 	obj_dir/Vtop
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/make_tracing_sc."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
 
 ######################################################################
 

examples/make_hello_sc/top.v

@@ -4,7 +4,8 @@
 // any use, without warranty, 2017 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top;
    initial begin
       $display("Hello World!");

examples/make_protect_lib/Makefile

@@ -33,7 +33,7 @@ VERILATOR_FLAGS =
 # Generate C++
 VERILATOR_FLAGS += -cc
 # Optimize
-VERILATOR_FLAGS += -Os -x-assign 0
+VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # This example does not use vl_time_stamp but rather

examples/make_protect_lib/top.v

@@ -4,7 +4,8 @@
 // any use, without warranty, 2019 by Todd Strader.
 // SPDX-License-Identifier: CC0-1.0
 
-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top (input clk);
 
    integer cyc = 0;

examples/make_tracing_c/Makefile

@@ -36,7 +36,7 @@ VERILATOR_FLAGS += -cc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 #VERILATOR_FLAGS += -MMD
 # Optimize
-VERILATOR_FLAGS += -Os -x-assign 0
+VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms

examples/make_tracing_c/sim_main.cpp

@@ -34,6 +34,8 @@ int main(int argc, char** argv, char** env) {
     // Using unique_ptr is similar to
     // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Do not instead make Vtop as a file-scope static variable, as the
+    // "C++ static initialization order fiasco" may cause a crash
 
     // Set debug level, 0 is off, 9 is highest presently used
     // May be overridden by commandArgs argument parsing
@@ -69,7 +71,7 @@ int main(int argc, char** argv, char** env) {
         // Historical note, before Verilator 4.200 Verilated::gotFinish()
         // was used above in place of contextp->gotFinish().
         // Most of the contextp-> calls can use Verilated:: calls instead;
-        // the Verilated:: versions simply assume there's a single context
+        // the Verilated:: versions just assume there's a single context
         // being used (per thread).  It's faster and clearer to use the
         // newer contextp-> versions.
 
@@ -103,8 +105,8 @@ int main(int argc, char** argv, char** env) {
         top->eval();
 
         // Read outputs
-        VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
-                  " -> oquad=%" VL_PRI64 "x owide=%x_%08x_%08x\n",
+        VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
+                  " owide=%x_%08x_%08x\n",
                   contextp->time(), top->clk, top->reset_l, top->in_quad, top->out_quad,
                   top->out_wide[2], top->out_wide[1], top->out_wide[0]);
     }

examples/make_tracing_sc/Makefile

@@ -37,7 +37,7 @@ VERILATOR_FLAGS += -sc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 #VERILATOR_FLAGS += -MMD
 # Optimize
-VERILATOR_FLAGS += -Os -x-assign 0
+VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms

examples/make_tracing_sc/sc_main.cpp

@@ -58,11 +58,11 @@ int sc_main(int argc, char* argv[]) {
 
     // Define interconnect
     sc_signal<bool> reset_l;
-    sc_signal<vluint32_t> in_small;
-    sc_signal<vluint64_t> in_quad;
+    sc_signal<uint32_t> in_small;
+    sc_signal<uint64_t> in_quad;
     sc_signal<sc_bv<70>> in_wide;
-    sc_signal<vluint32_t> out_small;
-    sc_signal<vluint64_t> out_quad;
+    sc_signal<uint32_t> out_small;
+    sc_signal<uint64_t> out_quad;
     sc_signal<sc_bv<70>> out_wide;
 
     // Construct the Verilated model, from inside Vtop.h

include/gtkwave/fst_win_unistd.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2009-2018 Tony Bybell.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef WIN_UNISTD_H
+#define WIN_UNISTD_H
+
+#include <stdlib.h>
+#ifdef _WIN64
+#include <io.h>
+#else
+#include <sys/io.h>
+#endif
+
+#include <process.h>
+
+#define ftruncate _chsize_s
+#define unlink _unlink
+#define fileno _fileno
+#define lseek _lseeki64
+
+#ifdef _WIN64
+#define ssize_t __int64
+#define SSIZE_MAX 9223372036854775807i64
+#else
+#define ssize_t long
+#define SSIZE_MAX 2147483647L
+#endif
+
+#include "stdint.h"
+
+#endif //WIN_UNISTD_H

include/gtkwave/fstapi.c

@@ -80,6 +80,12 @@
 #define PATH_MAX (4096)
 #endif
 
+#if defined(_MSC_VER)
+typedef int64_t fst_off_t;
+#else
+typedef off_t fst_off_t;
+#endif
+
 /* note that Judy versus Jenkins requires more experimentation: they are  */
 /* functionally equivalent though it appears Jenkins is slightly faster.  */
 /* in addition, Jenkins is not bound by the LGPL.                         */
@@ -134,6 +140,10 @@ void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint3
 #include <sys/sysctl.h>
 #endif
 
+#if defined(FST_MACOSX) || defined(__MINGW32__) || defined(__OpenBSD__) || defined(__FreeBSD__)
+#define FST_UNBUFFERED_IO
+#endif
+
 #ifdef __GNUC__
 /* Boolean expression more often true than false */
 #define FST_LIKELY(x) __builtin_expect(!!(x), 1)
@@ -155,8 +165,8 @@ void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint3
 #ifdef __MINGW32__
 #include <io.h>
 #ifndef HAVE_FSEEKO
-#define ftello ftell
-#define fseeko fseek
+#define ftello _ftelli64
+#define fseeko _fseeki64
 #endif
 #endif
 
@@ -284,7 +294,7 @@ static size_t fstFwrite(const void *buf, size_t siz, size_t cnt, FILE *fp)
 return(fwrite(buf, siz, cnt, fp));
 }
 
-static int fstFtruncate(int fd, off_t length)
+static int fstFtruncate(int fd, fst_off_t length)
 {
 return(ftruncate(fd, length));
 }
@@ -329,12 +339,12 @@ return(NULL);
 #define fstMmap(__addr,__len,__prot,__flags,__fd,__off) fstMmap2((__len), (__fd), (__off))
 #define fstMunmap(__addr,__len)                         free(__addr)
 
-static void *fstMmap2(size_t __len, int __fd, off_t __off)
+static void *fstMmap2(size_t __len, int __fd, fst_off_t __off)
 {
 (void)__off;
 
 unsigned char *pnt = (unsigned char *)malloc(__len);
-off_t cur_offs = lseek(__fd, 0, SEEK_CUR);
+fst_off_t cur_offs = lseek(__fd, 0, SEEK_CUR);
 size_t i;
 
 lseek(__fd, 0, SEEK_SET);
@@ -734,7 +744,7 @@ FILE *tchn_handle;
 
 unsigned char *vchg_mem;
 
-off_t hier_file_len;
+fst_off_t hier_file_len;
 
 uint32_t *valpos_mem;
 unsigned char *curval_mem;
@@ -754,7 +764,7 @@ unsigned fourpack : 1;
 unsigned fastpack : 1;
 
 int64_t timezero;
-off_t section_header_truncpos;
+fst_off_t section_header_truncpos;
 uint32_t tchn_cnt, tchn_idx;
 uint64_t curtime;
 uint64_t firsttime;
@@ -762,7 +772,7 @@ uint32_t vchg_siz;
 uint32_t vchg_alloc_siz;
 
 uint32_t secnum;
-off_t section_start;
+fst_off_t section_start;
 
 uint32_t numscopes;
 double nan; /* nan value for uninitialized doubles */
@@ -820,7 +830,7 @@ fstEnumHandle max_enumhandle;
 };
 
 
-static int fstWriterFseeko(struct fstWriterContext *xc, FILE *stream, off_t offset, int whence)
+static int fstWriterFseeko(struct fstWriterContext *xc, FILE *stream, fst_off_t offset, int whence)
 {
 int rc = fseeko(stream, offset, whence);
 
@@ -987,7 +997,7 @@ if(pnt == MAP_FAILED)
 
 static void fstWriterCreateMmaps(struct fstWriterContext *xc)
 {
-off_t curpos = ftello(xc->handle);
+fst_off_t curpos = ftello(xc->handle);
 
 fflush(xc->hier_handle);
 
@@ -1041,7 +1051,7 @@ if(xc->curval_mem)
                 {
                 unsigned char *pnt = xc->curval_mem;
                 int __fd = fileno(xc->curval_handle);
-                off_t cur_offs = lseek(__fd, 0, SEEK_CUR);
+                fst_off_t cur_offs = lseek(__fd, 0, SEEK_CUR);
                 size_t i;
                 size_t __len = xc->maxvalpos;
 
@@ -1282,14 +1292,14 @@ int cnt = 0;
 unsigned int i;
 unsigned char *vchg_mem;
 FILE *f;
-off_t fpos, indxpos, endpos;
+fst_off_t fpos, indxpos, endpos;
 uint32_t prevpos;
 int zerocnt;
 unsigned char *scratchpad;
 unsigned char *scratchpnt;
 unsigned char *tmem;
-off_t tlen;
-off_t unc_memreq = 0; /* for reader */
+fst_off_t tlen;
+fst_off_t unc_memreq = 0; /* for reader */
 unsigned char *packmem;
 unsigned int packmemlen;
 uint32_t *vm4ip;
@@ -1733,7 +1743,7 @@ if(tmem)
         unsigned char *dmem = (unsigned char *)malloc(compressBound(destlen));
         int rc = compress2(dmem, &destlen, tmem, tlen, 9);
 
-        if((rc == Z_OK) && (((off_t)destlen) < tlen))
+        if((rc == Z_OK) && (((fst_off_t)destlen) < tlen))
                 {
                 fstFwrite(dmem, destlen, 1, xc->handle);
                 }
@@ -1781,7 +1791,7 @@ fstWriterFseeko(xc, xc->handle, endpos, SEEK_SET);
 xc2->section_header_truncpos = endpos;                          /* cache in case of need to truncate */
 if(xc->dump_size_limit)
         {
-        if(endpos >= ((off_t)xc->dump_size_limit))
+        if(endpos >= ((fst_off_t)xc->dump_size_limit))
                 {
                 xc2->skip_writing_section_hdr = 1;
                 xc2->size_limit_locked = 1;
@@ -1931,7 +1941,7 @@ if(xc)
 if(xc && !xc->already_in_close && !xc->already_in_flush)
         {
         unsigned char *tmem = NULL;
-        off_t fixup_offs, tlen, hlen;
+        fst_off_t fixup_offs, tlen, hlen;
 
         xc->already_in_close = 1; /* never need to zero this out as it is freed at bottom */
 
@@ -1991,7 +2001,7 @@ if(xc && !xc->already_in_close && !xc->already_in_flush)
                 unsigned char *dmem = (unsigned char *)malloc(compressBound(destlen));
                 int rc = compress2(dmem, &destlen, tmem, tlen, 9);
 
-                if((rc != Z_OK) || (((off_t)destlen) > tlen))
+                if((rc != Z_OK) || (((fst_off_t)destlen) > tlen))
                         {
                         destlen = tlen;
                         }
@@ -2002,7 +2012,7 @@ if(xc && !xc->already_in_close && !xc->already_in_flush)
                 fstWriterUint64(xc->handle, tlen);              /* uncompressed */
                                                                 /* compressed len is section length - 24 */
                 fstWriterUint64(xc->handle, xc->maxhandle);     /* maxhandle */
-                fstFwrite((((off_t)destlen) != tlen) ? dmem : tmem, destlen, 1, xc->handle);
+                fstFwrite((((fst_off_t)destlen) != tlen) ? dmem : tmem, destlen, 1, xc->handle);
                 fflush(xc->handle);
 
                 fstWriterFseeko(xc, xc->handle, fixup_offs, SEEK_SET);
@@ -2018,7 +2028,7 @@ if(xc && !xc->already_in_close && !xc->already_in_flush)
         if(xc->num_blackouts)
                 {
                 uint64_t cur_bl = 0;
-                off_t bpos, eos;
+                fst_off_t bpos, eos;
                 uint32_t i;
 
                 fixup_offs = ftello(xc->handle);
@@ -2051,7 +2061,7 @@ if(xc && !xc->already_in_close && !xc->already_in_flush)
 
         if(xc->compress_hier)
                 {
-                off_t hl, eos;
+                fst_off_t hl, eos;
                 gzFile zhandle;
                 int zfd;
                 int fourpack_duo = 0;
@@ -2174,7 +2184,7 @@ if(xc && !xc->already_in_close && !xc->already_in_flush)
                 if(xc->repack_on_close)
                         {
                         FILE *fp;
-                        off_t offpnt, uclen;
+                        fst_off_t offpnt, uclen;
                         int flen = strlen(xc->filename);
                         char *hf = (char *)calloc(1, flen + 5);
 
@@ -2281,7 +2291,7 @@ struct fstWriterContext *xc = (struct fstWriterContext *)ctx;
 if(xc)
         {
         char s[FST_HDR_DATE_SIZE];
-        off_t fpos = ftello(xc->handle);
+        fst_off_t fpos = ftello(xc->handle);
         int len = strlen(dat);
 
         fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_DATE, SEEK_SET);
@@ -2300,7 +2310,7 @@ struct fstWriterContext *xc = (struct fstWriterContext *)ctx;
 if(xc && vers)
         {
         char s[FST_HDR_SIM_VERSION_SIZE];
-        off_t fpos = ftello(xc->handle);
+        fst_off_t fpos = ftello(xc->handle);
         int len = strlen(vers);
 
         fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_SIM_VERSION, SEEK_SET);
@@ -2320,7 +2330,7 @@ if(xc)
         {
         if(/*(filetype >= FST_FT_MIN) &&*/ (filetype <= FST_FT_MAX))
                 {
-                off_t fpos = ftello(xc->handle);
+                fst_off_t fpos = ftello(xc->handle);
 
                 xc->filetype = filetype;
 
@@ -2461,7 +2471,7 @@ void fstWriterSetTimescale(void *ctx, int ts)
 struct fstWriterContext *xc = (struct fstWriterContext *)ctx;
 if(xc)
         {
-        off_t fpos = ftello(xc->handle);
+        fst_off_t fpos = ftello(xc->handle);
         fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_TIMESCALE, SEEK_SET);
         fputc(ts & 255, xc->handle);
         fflush(xc->handle);
@@ -2519,7 +2529,7 @@ void fstWriterSetTimezero(void *ctx, int64_t tim)
 struct fstWriterContext *xc = (struct fstWriterContext *)ctx;
 if(xc)
         {
-        off_t fpos = ftello(xc->handle);
+        fst_off_t fpos = ftello(xc->handle);
         fstWriterFseeko(xc, xc->handle, FST_HDR_OFFS_TIMEZERO, SEEK_SET);
         fstWriterUint64(xc->handle, (xc->timezero = tim));
         fflush(xc->handle);
@@ -3361,7 +3371,7 @@ char date[FST_HDR_DATE_SIZE + 1];
 int64_t timezero;
 
 char *filename, *filename_unpacked;
-off_t hier_pos;
+fst_off_t hier_pos;
 
 uint32_t num_blackouts;
 uint64_t *blackout_times;
@@ -3376,10 +3386,10 @@ uint64_t *rvat_time_table;
 uint64_t rvat_beg_tim, rvat_end_tim;
 unsigned char *rvat_frame_data;
 uint64_t rvat_frame_maxhandle;
-off_t *rvat_chain_table;
+fst_off_t *rvat_chain_table;
 uint32_t *rvat_chain_table_lengths;
 uint64_t rvat_vc_maxhandle;
-off_t rvat_vc_start;
+fst_off_t rvat_vc_start;
 uint32_t *rvat_sig_offs;
 int rvat_packtype;
 
@@ -3418,7 +3428,7 @@ char *fh_nam;
 };
 
 
-int fstReaderFseeko(struct fstReaderContext *xc, FILE *stream, off_t offset, int whence)
+int fstReaderFseeko(struct fstReaderContext *xc, FILE *stream, fst_off_t offset, int whence)
 {
 int rc = fseeko(stream, offset, whence);
 
@@ -3911,11 +3921,11 @@ int pass_status = 1;
 
 if(!xc->fh)
         {
-        off_t offs_cache = ftello(xc->f);
+        fst_off_t offs_cache = ftello(xc->f);
         char *fnam = (char *)malloc(strlen(xc->filename) + 6 + 16 + 32 + 1);
         unsigned char *mem = (unsigned char *)malloc(FST_GZIO_LEN);
-        off_t hl, uclen;
-        off_t clen = 0;
+        fst_off_t hl, uclen;
+        fst_off_t clen = 0;
         gzFile zhandle = NULL;
         int zfd;
         int htyp = FST_BL_SKIP;
@@ -4535,8 +4545,8 @@ return(1);
  */
 int fstReaderInit(struct fstReaderContext *xc)
 {
-off_t blkpos = 0;
-off_t endfile;
+fst_off_t blkpos = 0;
+fst_off_t endfile;
 uint64_t seclen;
 int sectype;
 uint64_t vc_section_count_actual = 0;
@@ -4548,7 +4558,7 @@ sectype = fgetc(xc->f);
 if(sectype == FST_BL_ZWRAPPER)
         {
         FILE *fcomp;
-        off_t offpnt, uclen;
+        fst_off_t offpnt, uclen;
         char gz_membuf[FST_GZIO_LEN];
         gzFile zhandle;
         int zfd;
@@ -4571,12 +4581,11 @@ if(sectype == FST_BL_ZWRAPPER)
                 if(!fcomp) { tmpfile_close(&fcomp, &xc->f_nam); return(0); }
                 }
 
-#if defined(FST_MACOSX)
+#if defined(FST_UNBUFFERED_IO)
         setvbuf(fcomp, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
 #endif
 
 #ifdef __MINGW32__
-        setvbuf(fcomp, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
         xc->filename_unpacked = hf;
 #else
         if(hf)
@@ -4874,7 +4883,7 @@ if((!nam)||(!(xc->f=fopen(nam, "rb"))))
         char *hf = (char *)calloc(1, flen + 6);
         int rc;
 
-#if defined(__MINGW32__) || defined(FST_MACOSX)
+#if defined(FST_UNBUFFERED_IO)
         setvbuf(xc->f, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
 #endif
 
@@ -4981,15 +4990,13 @@ uint64_t *time_table = NULL;
 uint64_t tsec_nitems;
 unsigned int secnum = 0;
 int blocks_skipped = 0;
-off_t blkpos = 0;
+fst_off_t blkpos = 0;
 uint64_t seclen, beg_tim;
-#ifdef FST_DEBUG
 uint64_t end_tim;
-#endif
 uint64_t frame_uclen, frame_clen, frame_maxhandle, vc_maxhandle;
-off_t vc_start;
-off_t indx_pntr, indx_pos;
-off_t *chain_table = NULL;
+fst_off_t vc_start;
+fst_off_t indx_pntr, indx_pos;
+fst_off_t *chain_table = NULL;
 uint32_t *chain_table_lengths = NULL;
 unsigned char *chain_cmem;
 unsigned char *pnt;
@@ -5052,14 +5059,11 @@ for(;;)
         if(!seclen) break;
 
         beg_tim = fstReaderUint64(xc->f);
-#ifdef FST_DEBUG
-        end_tim =
-#endif
-        fstReaderUint64(xc->f);
+        end_tim = fstReaderUint64(xc->f);
 
         if(xc->limit_range_valid)
                 {
-                if(beg_tim < xc->limit_range_start)
+                if(end_tim < xc->limit_range_start)
                         {
                         blocks_skipped++;
                         blkpos += seclen;
@@ -5105,7 +5109,7 @@ for(;;)
         destlen = tsec_uclen;
         sourcelen = tsec_clen;
 
-        fstReaderFseeko(xc, xc->f, -24 - ((off_t)tsec_clen), SEEK_CUR);
+        fstReaderFseeko(xc, xc->f, -24 - ((fst_off_t)tsec_clen), SEEK_CUR);
 
         if(tsec_uclen != tsec_clen)
                 {
@@ -5346,11 +5350,11 @@ for(;;)
                                 }
 
                         free(mu);
-                        fstReaderFseeko(xc, xc->f, -((off_t)frame_clen), SEEK_CUR);
+                        fstReaderFseeko(xc, xc->f, -((fst_off_t)frame_clen), SEEK_CUR);
                         }
                 }
 
-        fstReaderFseeko(xc, xc->f, (off_t)frame_clen, SEEK_CUR); /* skip past compressed data */
+        fstReaderFseeko(xc, xc->f, (fst_off_t)frame_clen, SEEK_CUR); /* skip past compressed data */
 
         vc_maxhandle = fstReaderVarint64(xc->f);
         vc_start = ftello(xc->f);       /* points to '!' character */
@@ -5380,7 +5384,7 @@ for(;;)
                 free(chain_table_lengths);
 
                 vc_maxhandle_largest = vc_maxhandle;
-                chain_table = (off_t *)calloc((vc_maxhandle+1), sizeof(off_t));
+                chain_table = (fst_off_t *)calloc((vc_maxhandle+1), sizeof(fst_off_t));
                 chain_table_lengths = (uint32_t *)calloc((vc_maxhandle+1), sizeof(uint32_t));
                 }
 
@@ -6001,7 +6005,7 @@ return(buf);
 char *fstReaderGetValueFromHandleAtTime(void *ctx, uint64_t tim, fstHandle facidx, char *buf)
 {
 struct fstReaderContext *xc = (struct fstReaderContext *)ctx;
-off_t blkpos = 0, prev_blkpos;
+fst_off_t blkpos = 0, prev_blkpos;
 uint64_t beg_tim, end_tim, beg_tim2, end_tim2;
 int sectype;
 unsigned int secnum = 0;
@@ -6012,7 +6016,7 @@ uint64_t frame_uclen, frame_clen;
 #ifdef FST_DEBUG
 uint64_t mem_required_for_traversal;
 #endif
-off_t indx_pntr, indx_pos;
+fst_off_t indx_pntr, indx_pos;
 long chain_clen;
 unsigned char *chain_cmem;
 unsigned char *pnt;
@@ -6074,7 +6078,7 @@ for(;;)
                 {
                 if((tim == end_tim) && (tim != xc->end_time))
                         {
-                        off_t cached_pos = ftello(xc->f);
+                        fst_off_t cached_pos = ftello(xc->f);
                         fstReaderFseeko(xc, xc->f, blkpos, SEEK_SET);
 
                         sectype = fgetc(xc->f);
@@ -6136,7 +6140,7 @@ ucdata = (unsigned char *)malloc(tsec_uclen);
 destlen = tsec_uclen;
 sourcelen = tsec_clen;
 
-fstReaderFseeko(xc, xc->f, -24 - ((off_t)tsec_clen), SEEK_CUR);
+fstReaderFseeko(xc, xc->f, -24 - ((fst_off_t)tsec_clen), SEEK_CUR);
 if(tsec_uclen != tsec_clen)
         {
         cdata = (unsigned char *)malloc(tsec_clen);
@@ -6221,7 +6225,7 @@ chain_cmem = (unsigned char *)malloc(chain_clen);
 fstReaderFseeko(xc, xc->f, indx_pos, SEEK_SET);
 fstFread(chain_cmem, chain_clen, 1, xc->f);
 
-xc->rvat_chain_table = (off_t *)calloc((xc->rvat_vc_maxhandle+1), sizeof(off_t));
+xc->rvat_chain_table = (fst_off_t *)calloc((xc->rvat_vc_maxhandle+1), sizeof(fst_off_t));
 xc->rvat_chain_table_lengths = (uint32_t *)calloc((xc->rvat_vc_maxhandle+1), sizeof(uint32_t));
 
 pnt = chain_cmem;

include/gtkwave/fstapi.h

@@ -35,7 +35,11 @@ extern "C" {
 #include <ctype.h>
 #include <zlib.h>
 #include <inttypes.h>
-#include <unistd.h>
+#if defined(_MSC_VER)
+    #include "fst_win_unistd.h"
+#else
+    #include <unistd.h>
+#endif
 #include <time.h>
 
 #define FST_RDLOAD "FSTLOAD | "

include/verilated.mk.in

@@ -2,27 +2,27 @@
 ######################################################################
 # DESCRIPTION: Makefile commands for all verilated target files
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2022 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ######################################################################
 
-PERL = @PERL@
+AR = @AR@
 CXX = @CXX@
 LINK = @CXX@
-AR = ar
-RANLIB = ranlib
 OBJCACHE ?= @OBJCACHE@
+PERL = @PERL@
+PYTHON3 = @PYTHON3@
 
 CFG_WITH_CCWARN = @CFG_WITH_CCWARN@
 CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@
 
+# Compiler flags to enable profiling
+CFG_CXXFLAGS_PROFILE = @CFG_CXXFLAGS_PROFILE@
 # Select newest language
 CFG_CXXFLAGS_STD_NEWEST = @CFG_CXXFLAGS_STD_NEWEST@
-# Select oldest language (for Verilator internal testing only)
-CFG_CXXFLAGS_STD_OLDEST = @CFG_CXXFLAGS_STD_OLDEST@
 # Compiler flags to use to turn off unused and generated code warnings, such as -Wno-div-by-zero
 CFG_CXXFLAGS_NO_UNUSED = @CFG_CXXFLAGS_NO_UNUSED@
 # Compiler flags that turn on extra warnings
@@ -35,6 +35,7 @@ CFG_LDLIBS_THREADS = @CFG_LDLIBS_THREADS@
 
 VERILATOR_COVERAGE = $(PERL) $(VERILATOR_ROOT)/bin/verilator_coverage
 VERILATOR_INCLUDER = $(PERL) $(VERILATOR_ROOT)/bin/verilator_includer
+VERILATOR_CCACHE_REPORT = $(PYTHON3) $(VERILATOR_ROOT)/bin/verilator_ccache_report
 
 ######################################################################
 # Make checks
@@ -55,6 +56,7 @@ VK_CPPFLAGS_ALWAYS += \
 		-DVM_SC=$(VM_SC) \
 		-DVM_TRACE=$(VM_TRACE) \
 		-DVM_TRACE_FST=$(VM_TRACE_FST) \
+		-DVM_TRACE_VCD=$(VM_TRACE_VCD) \
 		$(CFG_CXXFLAGS_NO_UNUSED) \
 
 ifeq ($(CFG_WITH_CCWARN),yes)	# Local... Else don't burden users
@@ -102,6 +104,14 @@ OPT_FAST = -Os
 # to change this as the library is small, but can have significant speed impact.
 OPT_GLOBAL = -Os
 
+#######################################################################
+##### Profile builds
+
+ifeq ($(VM_PROFC),1)
+  CPPFLAGS += $(CFG_CXXFLAGS_PROFILE)
+  LDFLAGS  += $(CFG_CXXFLAGS_PROFILE)
+endif
+
 #######################################################################
 ##### SystemC builds
 
@@ -184,6 +194,10 @@ VK_USER_OBJS   = $(addsuffix .o, $(VM_USER_CLASSES))
 # but keeping the distinction for compatibility for now.
 VK_GLOBAL_OBJS = $(addsuffix .o, $(VM_GLOBAL_FAST) $(VM_GLOBAL_SLOW))
 
+# Need to re-build if the generated makefile changes, as compiler options might
+# have changed.
+$(VK_GLOBAL_OBJS): $(VM_PREFIX).mk
+
 ifneq ($(VM_PARALLEL_BUILDS),1)
   # Fast build for small designs: All .cpp files in one fell swoop. This
   # saves total compute, but can be slower if only a little changes. It is
@@ -202,16 +216,21 @@ else
 endif
 
 # When archiving just objects (.o), use single $(AR) run
-#   1. Make .tmp file with list of objects so don't exceed commend line
+#   1. Make .verilator_deplist.tmp file with list of objects so don't exceed
+#      the command line limits when calling $(AR).
+#      The approach to write the dependency file is compatible with GNU Make 3,
+#      and can be simplified using the file function once GNU Make 4.x becomes
+#      the minimum supported version.
 # When merging objects (.o) and archives (.a) additionally:
 #   1. Extract object files from .a
 #   2. Create a new archive from extracted .o and given .o
-%.a:
+%.a: | %.verilator_deplist.tmp
 	$(info Archive $(AR) -rcs $@ $^)
-	$(file >$@.tmp)
-	$(foreach L, $(filter-out %.a,$^), $(file >>[email protected], $L))
+	$(foreach L, $(filter-out %.a,$^), $(shell echo $L >>[email protected]_deplist.tmp))
 	@if test $(words $(filter %.a,$^)) -eq 0; then \
-		$(AR) -rcs $@ @[email protected]; \
+		$(RM) -f $@; \
+		cat [email protected]_deplist.tmp | xargs $(AR) -rc $@; \
+		$(AR) -s $@; \
 	else \
 		$(RM) -rf [email protected]; \
 		for archive in $(filter %.a,$^); do \
@@ -220,9 +239,15 @@ endif
 			$(AR) -x ../../$${archive}; \
 			cd ../..; \
 		done; \
-		$(AR) -rcs $@ @[email protected] [email protected]/*/*.o; \
+		$(RM) -f $@; \
+		cat [email protected]_deplist.tmp | xargs $(AR) -rc $@; \
+		$(AR) -rcs $@ [email protected]/*/*.o; \
 	fi \
-	; $(RM) -rf [email protected] [email protected]
+	; $(RM) -rf $@.verilator_deplist.tmp [email protected]
+
+# Truncate the dependency list file used in the %.a target above.
+%.verilator_deplist.tmp:
+	echo "" > $@
 
 $(VM_PREFIX)__ALL.a: $(VK_OBJS) $(VM_HIER_LIBS)
 
@@ -247,6 +272,42 @@ endif
 #.cpp.o:
 #	$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $<
 
+######################################################################
+### ccache report
+
+ifneq ($(findstring ccache-report,$(MAKECMDGOALS)),)
+  ifneq ($(OBJCACHE),ccache)
+    $(error ccache-report requires OBJCACHE to equal 'ccache')
+  endif
+  VK_OTHER_GOALS := $(strip $(subst ccache-report,,$(MAKECMDGOALS)))
+  ifeq ($(VK_OTHER_GOALS),)
+    $(error ccache-report must be used with at least one other explicit target)
+  endif
+
+  # Report ccache behaviour for this invocation of make
+  VK_CCACHE_LOGDIR := ccache-logs
+  VK_CCACHE_REPORT := $(VM_PREFIX)__ccache_report.txt
+  # Remove previous logfiles and report
+  $(shell rm -rf $(VK_CCACHE_LOGDIR) $(VK_CCACHE_REPORT))
+
+$(VK_CCACHE_LOGDIR):
+	mkdir -p $@
+
+$(VK_OBJS): | $(VK_CCACHE_LOGDIR)
+
+$(VK_OBJS): export CCACHE_LOGFILE=$(VK_CCACHE_LOGDIR)/[email protected]
+
+$(VK_CCACHE_REPORT): $(VK_OBJS)
+	$(VERILATOR_CCACHE_REPORT) -o $@ $(VK_CCACHE_LOGDIR)
+
+.PHONY: ccache-report
+ccache-report: $(VK_CCACHE_REPORT)
+	@cat $<
+
+# ccache-report runs last
+ccache-report: $(VK_OTHER_GOALS)
+endif
+
 ######################################################################
 ### Debugging
 

include/verilated.v

@@ -2,7 +2,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_config.h.in

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -20,6 +20,11 @@
 // Autoconf substitutes this with the strings from AC_INIT.
 #define VERILATOR_PRODUCT "@PACKAGE_NAME@"
 
-/// Verilator version name, e.g. "1.000 2000-01-01"
+/// Verilator version name, e.g. "1.002 2000-01-01"
 // Autoconf substitutes this with the strings from AC_INIT.
 #define VERILATOR_VERSION "@PACKAGE_VERSION@"
+
+/// Verilator version number as integer
+/// As major * 100000 + minor * 1000, e.g. 1002000 == 1.002
+// Autoconf substitutes this with the strings from AC_INIT.
+#define VERILATOR_VERSION_INTEGER @VERILATOR_VERSION_INTEGER@

include/verilated_cov.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -29,6 +29,7 @@
 #include <deque>
 #include <fstream>
 #include <map>
+#include <utility>
 
 //=============================================================================
 // VerilatedCovConst
@@ -58,7 +59,7 @@ public:  // But only local to this file
         }
     }
     virtual ~VerilatedCovImpItem() = default;
-    virtual vluint64_t count() const = 0;
+    virtual uint64_t count() const = 0;
     virtual void zero() const = 0;
 };
 
@@ -75,7 +76,7 @@ private:
 public:
     // METHODS
     // cppcheck-suppress truncLongCastReturn
-    virtual vluint64_t count() const override { return *m_countp; }
+    virtual uint64_t count() const override { return *m_countp; }
     virtual void zero() const override { *m_countp = 0; }
     // CONSTRUCTORS
     // cppcheck-suppress noExplicitConstructor
@@ -102,7 +103,7 @@ private:
     using ItemList = std::deque<VerilatedCovImpItem*>;
 
     // MEMBERS
-    VerilatedMutex m_mutex;  // Protects all members
+    mutable VerilatedMutex m_mutex;  // Protects all members
     ValueIndexMap m_valueIndexes VL_GUARDED_BY(m_mutex);  // Unique arbitrary value for values
     IndexValueMap m_indexValues VL_GUARDED_BY(m_mutex);  // Unique arbitrary value for keys
     ItemList m_items VL_GUARDED_BY(m_mutex);  // List of all items
@@ -122,17 +123,13 @@ public:
 protected:
     friend class VerilatedCovContext;
     virtual ~VerilatedCovImp() override { clearGuts(); }
-    static VerilatedCovImp& imp() VL_MT_SAFE {
-        static VerilatedCovImp s_singleton;
-        return s_singleton;
-    }
 
 private:
     // PRIVATE METHODS
     int valueIndex(const std::string& value) VL_REQUIRES(m_mutex) {
         const auto iter = m_valueIndexes.find(value);
         if (iter != m_valueIndexes.end()) return iter->second;
-        m_nextIndex++;
+        ++m_nextIndex;
         assert(m_nextIndex > 0);  // Didn't rollover
         m_valueIndexes.emplace(value, m_nextIndex);
         m_indexValues.emplace(m_nextIndex, value);
@@ -143,8 +140,9 @@ private:
         std::string rtn;
         for (const char* pos = text.c_str(); *pos; ++pos) {
             if (!std::isprint(*pos) || *pos == '%' || *pos == '"') {
-                char hex[10];
-                VL_SNPRINTF(hex, 10, "%%%02X", pos[0]);
+                constexpr size_t LEN_MAX_HEX = 20;
+                char hex[LEN_MAX_HEX];
+                VL_SNPRINTF(hex, LEN_MAX_HEX, "%%%02X", pos[0]);
                 rtn += hex;
             } else {
                 rtn += *pos;
@@ -165,11 +163,11 @@ private:
                                          const std::string& value) VL_PURE {
         std::string name;
         if (key.length() == 1 && std::isalpha(key[0])) {
-            name += std::string("\001") + key;
+            name += std::string{"\001"} + key;
         } else {
-            name += std::string("\001") + dequote(key);
+            name += std::string{"\001"} + dequote(key);
         }
-        name += std::string("\002") + dequote(value);
+        name += std::string{"\002"} + dequote(value);
         return name;
     }
     static std::string combineHier(const std::string& old, const std::string& add) VL_PURE {
@@ -180,33 +178,34 @@ private:
         if (old.empty()) return add;
         if (add.empty()) return old;
 
-        const char* a = old.c_str();
-        const char* b = add.c_str();
+        const char* const a = old.c_str();
+        const char* const b = add.c_str();
 
         // Scan forward to first mismatch
         const char* apre = a;
         const char* bpre = b;
         while (*apre == *bpre) {
-            apre++;
-            bpre++;
+            ++apre;
+            ++bpre;
         }
 
         // We used to backup and split on only .'s but it seems better to be verbose
         // and not assume . is the separator
-        std::string prefix = std::string(a, apre - a);
+        const size_t prefix_len = apre - a;
+        const std::string prefix = std::string{a, prefix_len};
 
         // Scan backward to last mismatch
         const char* apost = a + std::strlen(a) - 1;
         const char* bpost = b + std::strlen(b) - 1;
         while (*apost == *bpost && apost > apre && bpost > bpre) {
-            apost--;
-            bpost--;
+            --apost;
+            --bpost;
         }
 
         // Forward to . so we have a whole word
-        std::string suffix = *bpost ? std::string(bpost + 1) : "";
+        const std::string suffix = *bpost ? std::string{bpost + 1} : "";
 
-        std::string out = prefix + "*" + suffix;
+        const std::string out = prefix + "*" + suffix;
 
         // cout << "\nch pre="<<prefix<<"  s="<<suffix<<"\nch a="<<old<<"\nch b="<<add
         // <<"\ncho="<<out<<endl;
@@ -217,7 +216,7 @@ private:
         for (int i = 0; i < VerilatedCovConst::MAX_KEYS; ++i) {
             if (itemp->m_keys[i] != VerilatedCovConst::KEY_UNDEF) {
                 // We don't compare keys, only values
-                std::string val = m_indexValues[itemp->m_vals[i]];
+                const std::string val = m_indexValues[itemp->m_vals[i]];
                 if (std::string::npos != val.find(match)) {  // Found
                     return true;
                 }
@@ -229,7 +228,7 @@ private:
         // Little selftest
 #define SELF_CHECK(got, exp) \
     do { \
-        if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest\n"); \
+        if ((got) != (exp)) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: selftest"); \
     } while (0)
         SELF_CHECK(combineHier("a.b.c", "a.b.c"), "a.b.c");
         SELF_CHECK(combineHier("a.b.c", "a.b"), "a.b*");
@@ -251,19 +250,19 @@ private:
 
 public:
     // PUBLIC METHODS
-    void forcePerInstance(bool flag) VL_MT_SAFE_EXCLUDES(m_mutex) {
+    void forcePerInstance(const bool flag) VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         m_forcePerInstance = flag;
     }
     void clear() VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         clearGuts();
     }
-    void clearNonMatch(const char* matchp) VL_MT_SAFE_EXCLUDES(m_mutex) {
+    void clearNonMatch(const char* const matchp) VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         if (matchp && matchp[0]) {
             ItemList newlist;
             for (const auto& itemp : m_items) {
@@ -278,29 +277,29 @@ public:
     }
     void zero() VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         for (const auto& itemp : m_items) itemp->zero();
     }
 
     // We assume there's always call to i/f/p in that order
     void inserti(VerilatedCovImpItem* itemp) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         assert(!m_insertp);
         m_insertp = itemp;
     }
-    void insertf(const char* filenamep, int lineno) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+    void insertf(const char* const filenamep, const int lineno) VL_MT_SAFE_EXCLUDES(m_mutex) {
+        const VerilatedLockGuard lock{m_mutex};
         m_insertFilenamep = filenamep;
         m_insertLineno = lineno;
     }
     void insertp(const char* ckeyps[VerilatedCovConst::MAX_KEYS],
                  const char* valps[VerilatedCovConst::MAX_KEYS]) VL_MT_SAFE_EXCLUDES(m_mutex) {
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
         assert(m_insertp);
         // First two key/vals are filename
         ckeyps[0] = "filename";
         valps[0] = m_insertFilenamep;
-        std::string linestr = vlCovCvtToStr(m_insertLineno);
+        const std::string linestr = vlCovCvtToStr(m_insertLineno);
         ckeyps[1] = "lineno";
         valps[1] = linestr.c_str();
         // Default page if not specified
@@ -308,7 +307,8 @@ public:
         while (const char* foundp = std::strchr(fnstartp, '/')) fnstartp = foundp + 1;
         const char* fnendp = fnstartp;
         for (; *fnendp && *fnendp != '.'; fnendp++) {}
-        std::string page_default = "sp_user/" + std::string(fnstartp, fnendp - fnstartp);
+        const size_t page_len = fnendp - fnstartp;
+        const std::string page_default = "sp_user/" + std::string{fnstartp, page_len};
         ckeyps[2] = "page";
         valps[2] = page_default.c_str();
 
@@ -337,9 +337,9 @@ public:
                 // cout<<"   "<<__FUNCTION__<<"  "<<key<<" = "<<val<<endl;
                 m_insertp->m_keys[addKeynum] = valueIndex(key);
                 m_insertp->m_vals[addKeynum] = valueIndex(val);
-                addKeynum++;
+                ++addKeynum;
                 if (VL_UNCOVERABLE(!legalKey(key))) {
-                    std::string msg
+                    const std::string msg
                         = ("%Error: Coverage keys of one character, or letter+digit are illegal: "
                            + key);  // LCOV_EXCL_LINE
                     VL_FATAL_MT("", 0, "", msg.c_str());
@@ -353,22 +353,22 @@ public:
 
     void write(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
         Verilated::quiesce();
-        const VerilatedLockGuard lock(m_mutex);
+        const VerilatedLockGuard lock{m_mutex};
 #ifndef VM_COVERAGE
-        VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled\n");
+        VL_FATAL_MT("", 0, "", "%Error: Called VerilatedCov::write when VM_COVERAGE disabled");
 #endif
         selftest();
 
-        std::ofstream os(filename);
+        std::ofstream os{filename};
         if (os.fail()) {
-            std::string msg = std::string("%Error: Can't write '") + filename + "'";
+            const std::string msg = std::string{"%Error: Can't write '"} + filename + "'";
             VL_FATAL_MT("", 0, "", msg.c_str());
             return;
         }
         os << "# SystemC::Coverage-3\n";
 
         // Build list of events; totalize if collapsing hierarchy
-        std::map<const std::string, std::pair<std::string, vluint64_t>> eventCounts;
+        std::map<const std::string, std::pair<std::string, uint64_t>> eventCounts;
         for (const auto& itemp : m_items) {
             std::string name;
             std::string hier;
@@ -377,8 +377,9 @@ public:
 
             for (int i = 0; i < VerilatedCovConst::MAX_KEYS; ++i) {
                 if (itemp->m_keys[i] != VerilatedCovConst::KEY_UNDEF) {
-                    std::string key = VerilatedCovKey::shortKey(m_indexValues[itemp->m_keys[i]]);
-                    std::string val = m_indexValues[itemp->m_vals[i]];
+                    const std::string key
+                        = VerilatedCovKey::shortKey(m_indexValues[itemp->m_keys[i]]);
+                    const std::string val = m_indexValues[itemp->m_vals[i]];
                     if (key == VL_CIK_PER_INSTANCE) {
                         if (val != "0") per_instance = true;
                     }
@@ -434,11 +435,11 @@ void VerilatedCovContext::clearNonMatch(const char* matchp) VL_MT_SAFE {
 }
 void VerilatedCovContext::zero() VL_MT_SAFE { impp()->zero(); }
 void VerilatedCovContext::write(const char* filenamep) VL_MT_SAFE { impp()->write(filenamep); }
-void VerilatedCovContext::_inserti(vluint32_t* itemp) VL_MT_SAFE {
-    impp()->inserti(new VerilatedCoverItemSpec<vluint32_t>(itemp));
+void VerilatedCovContext::_inserti(uint32_t* itemp) VL_MT_SAFE {
+    impp()->inserti(new VerilatedCoverItemSpec<uint32_t>{itemp});
 }
-void VerilatedCovContext::_inserti(vluint64_t* itemp) VL_MT_SAFE {
-    impp()->inserti(new VerilatedCoverItemSpec<vluint64_t>(itemp));
+void VerilatedCovContext::_inserti(uint64_t* itemp) VL_MT_SAFE {
+    impp()->inserti(new VerilatedCoverItemSpec<uint64_t>{itemp});
 }
 void VerilatedCovContext::_insertf(const char* filename, int lineno) VL_MT_SAFE {
     impp()->insertf(filename, lineno);
@@ -511,7 +512,7 @@ VerilatedCovContext* VerilatedCov::threadCovp() VL_MT_SAFE {
 VerilatedCovContext* VerilatedContext::coveragep() VL_MT_SAFE {
     static VerilatedMutex s_mutex;
     if (VL_UNLIKELY(!m_coveragep)) {
-        const VerilatedLockGuard lock(s_mutex);
+        const VerilatedLockGuard lock{s_mutex};
         if (VL_LIKELY(!m_coveragep)) {  // Not redundant, prevents race
             m_coveragep.reset(new VerilatedCovImp);
         }

include/verilated_cov.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -72,7 +72,7 @@ class VerilatedCovImp;
 ///
 /// Example:
 ///
-///     vluint32_t m_cases[10];  // Storage for coverage data
+///     uint32_t m_cases[10];  // Storage for coverage data
 ///     constructor() {
 ///         // Initialize
 ///         for (int i = 0; i < 10; ++i) m_cases[i] = 0;
@@ -126,8 +126,8 @@ public:  // But Internal use only
     // Call _insert1, followed by _insert2 and _insert3
     // Do not call directly; use VL_COVER_INSERT or higher level macros instead
     // _insert1: Remember item pointer with count.  (Not const, as may add zeroing function)
-    void _inserti(vluint32_t* itemp) VL_MT_SAFE;
-    void _inserti(vluint64_t* itemp) VL_MT_SAFE;
+    void _inserti(uint32_t* itemp) VL_MT_SAFE;
+    void _inserti(uint64_t* itemp) VL_MT_SAFE;
     // _insert2: Set default filename and line number
     void _insertf(const char* filename, int lineno) VL_MT_SAFE;
     // _insert3: Set parameters
@@ -157,8 +157,8 @@ protected:
     friend class VerilatedCovImp;
     // CONSTRUCTORS
     // Internal: Only made as part of VerilatedCovImp
-    VerilatedCovContext() {}
-    virtual ~VerilatedCovContext() {}
+    VerilatedCovContext() = default;
+    virtual ~VerilatedCovContext() = default;
 
     // METHODS
     // Internal: access to implementation class

include/verilated_cov_key.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.

include/verilated_dpi.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2009-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -68,7 +68,7 @@ svLogic svGetBitselLogic(const svLogicVecVal* sp, int bit) {
             | (((sp[VL_BITWORD_I(bit)].bval >> VL_BITBIT_I(bit)) & 1) << 1));
 }
 
-void svPutBitselBit(svBitVecVal* dp, int bit, svBit s) { VL_ASSIGNBIT_WI(32, bit, dp, s); }
+void svPutBitselBit(svBitVecVal* dp, int bit, svBit s) { VL_ASSIGNBIT_WI(bit, dp, s); }
 void svPutBitselLogic(svLogicVecVal* dp, int bit, svLogic s) {
     // Verilator doesn't support X/Z so only aval
     dp[VL_BITWORD_I(bit)].aval = ((dp[VL_BITWORD_I(bit)].aval & ~(VL_UL(1) << VL_BITBIT_I(bit)))
@@ -79,19 +79,19 @@ void svPutBitselLogic(svLogicVecVal* dp, int bit, svLogic s) {
 
 void svGetPartselBit(svBitVecVal* dp, const svBitVecVal* sp, int lsb, int width) {
     // See also VL_SEL_WWI
-    int msb = lsb + width - 1;
-    int word_shift = VL_BITWORD_I(lsb);
+    const int msb = lsb + width - 1;
+    const int word_shift = VL_BITWORD_I(lsb);
     if (VL_BITBIT_I(lsb) == 0) {
         // Just a word extract
         for (int i = 0; i < VL_WORDS_I(width); ++i) dp[i] = sp[i + word_shift];
     } else {
-        int loffset = lsb & VL_SIZEBITS_I;
-        int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
+        const int loffset = lsb & VL_SIZEBITS_I;
+        const int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
         // Middle words
-        int words = VL_WORDS_I(msb - lsb + 1);
+        const int words = VL_WORDS_I(msb - lsb + 1);
         for (int i = 0; i < words; ++i) {
             dp[i] = sp[i + word_shift] >> loffset;
-            int upperword = i + word_shift + 1;
+            const int upperword = i + word_shift + 1;
             if (upperword <= static_cast<int>(VL_BITWORD_I(msb))) {
                 dp[i] |= sp[upperword] << nbitsfromlow;
             }
@@ -101,20 +101,20 @@ void svGetPartselBit(svBitVecVal* dp, const svBitVecVal* sp, int lsb, int width)
     dp[VL_WORDS_I(width) - 1] &= VL_MASK_I(width);
 }
 void svGetPartselLogic(svLogicVecVal* dp, const svLogicVecVal* sp, int lsb, int width) {
-    int msb = lsb + width - 1;
-    int word_shift = VL_BITWORD_I(lsb);
+    const int msb = lsb + width - 1;
+    const int word_shift = VL_BITWORD_I(lsb);
     if (VL_BITBIT_I(lsb) == 0) {
         // Just a word extract
         for (int i = 0; i < VL_WORDS_I(width); ++i) dp[i] = sp[i + word_shift];
     } else {
-        int loffset = lsb & VL_SIZEBITS_I;
-        int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
+        const int loffset = lsb & VL_SIZEBITS_I;
+        const int nbitsfromlow = 32 - loffset;  // bits that end up in lword (know loffset!=0)
         // Middle words
-        int words = VL_WORDS_I(msb - lsb + 1);
+        const int words = VL_WORDS_I(msb - lsb + 1);
         for (int i = 0; i < words; ++i) {
             dp[i].aval = sp[i + word_shift].aval >> loffset;
             dp[i].bval = sp[i + word_shift].bval >> loffset;
-            int upperword = i + word_shift + 1;
+            const int upperword = i + word_shift + 1;
             if (upperword <= static_cast<int>(VL_BITWORD_I(msb))) {
                 dp[i].aval |= sp[upperword].aval << nbitsfromlow;
                 dp[i].bval |= sp[upperword].bval << nbitsfromlow;
@@ -127,22 +127,22 @@ void svGetPartselLogic(svLogicVecVal* dp, const svLogicVecVal* sp, int lsb, int
 }
 void svPutPartselBit(svBitVecVal* dp, const svBitVecVal s, int lbit, int width) {
     // See also _vl_insert_WI
-    int hbit = lbit + width - 1;
-    int hoffset = VL_BITBIT_I(hbit);
-    int loffset = VL_BITBIT_I(lbit);
+    const int hbit = lbit + width - 1;
+    const int hoffset = VL_BITBIT_I(hbit);
+    const int loffset = VL_BITBIT_I(lbit);
     if (hoffset == VL_SIZEBITS_I && loffset == 0) {
         // Fast and common case, word based insertion
         dp[VL_BITWORD_I(lbit)] = s;
     } else {
-        int hword = VL_BITWORD_I(hbit);
-        int lword = VL_BITWORD_I(lbit);
+        const int hword = VL_BITWORD_I(hbit);
+        const int lword = VL_BITWORD_I(lbit);
         if (hword == lword) {  // know < 32 bits because above checks it
-            IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
+            const IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
             dp[lword] = (dp[lword] & ~insmask) | ((s << loffset) & insmask);
         } else {
-            IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
-            IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
-            int nbitsonright = 32 - loffset;  // bits that end up in lword
+            const IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
+            const IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
+            const int nbitsonright = 32 - loffset;  // bits that end up in lword
             dp[lword] = (dp[lword] & ~linsmask) | ((s << loffset) & linsmask);
             dp[hword] = (dp[hword] & ~hinsmask) | ((s >> nbitsonright) & hinsmask);
         }
@@ -150,24 +150,24 @@ void svPutPartselBit(svBitVecVal* dp, const svBitVecVal s, int lbit, int width)
 }
 // cppcheck-suppress passedByValue
 void svPutPartselLogic(svLogicVecVal* dp, const svLogicVecVal s, int lbit, int width) {
-    int hbit = lbit + width - 1;
-    int hoffset = VL_BITBIT_I(hbit);
-    int loffset = VL_BITBIT_I(lbit);
+    const int hbit = lbit + width - 1;
+    const int hoffset = VL_BITBIT_I(hbit);
+    const int loffset = VL_BITBIT_I(lbit);
     if (hoffset == VL_SIZEBITS_I && loffset == 0) {
         // Fast and common case, word based insertion
         dp[VL_BITWORD_I(lbit)].aval = s.aval;
         dp[VL_BITWORD_I(lbit)].bval = s.bval;
     } else {
-        int hword = VL_BITWORD_I(hbit);
-        int lword = VL_BITWORD_I(lbit);
+        const int hword = VL_BITWORD_I(hbit);
+        const int lword = VL_BITWORD_I(lbit);
         if (hword == lword) {  // know < 32 bits because above checks it
-            IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
+            const IData insmask = (VL_MASK_I(hoffset - loffset + 1)) << loffset;
             dp[lword].aval = (dp[lword].aval & ~insmask) | ((s.aval << loffset) & insmask);
             dp[lword].bval = (dp[lword].bval & ~insmask) | ((s.bval << loffset) & insmask);
         } else {
-            IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
-            IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
-            int nbitsonright = 32 - loffset;  // bits that end up in lword
+            const IData hinsmask = (VL_MASK_I(hoffset - 0 + 1)) << 0;
+            const IData linsmask = (VL_MASK_I(31 - loffset + 1)) << loffset;
+            const int nbitsonright = 32 - loffset;  // bits that end up in lword
             dp[lword].aval = (dp[lword].aval & ~linsmask) | ((s.aval << loffset) & linsmask);
             dp[lword].bval = (dp[lword].bval & ~linsmask) | ((s.bval << loffset) & linsmask);
             dp[hword].aval = (dp[hword].aval & ~hinsmask) | ((s.aval >> nbitsonright) & hinsmask);
@@ -184,7 +184,7 @@ static inline const VerilatedDpiOpenVar* _vl_openhandle_varp(const svOpenArrayHa
         VL_FATAL_MT(__FILE__, __LINE__, "",
                     "%%Error: DPI svOpenArrayHandle function called with nullptr handle");
     }
-    const VerilatedDpiOpenVar* varp = reinterpret_cast<const VerilatedDpiOpenVar*>(h);
+    const VerilatedDpiOpenVar* const varp = reinterpret_cast<const VerilatedDpiOpenVar*>(h);
     if (VL_UNLIKELY(!varp->magicOk())) {
         VL_FATAL_MT(__FILE__, __LINE__, "",
                     "%%Error: DPI svOpenArrayHandle function called with non-Verilator handle");
@@ -205,13 +205,13 @@ int svDimensions(const svOpenArrayHandle h) { return _vl_openhandle_varp(h)->udi
 
 // Return pointer to open array data, or nullptr if not in IEEE standard C layout
 void* svGetArrayPtr(const svOpenArrayHandle h) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h);
     if (VL_UNLIKELY(!varp->isDpiStdLayout())) return nullptr;
     return varp->datap();
 }
 // Return size of open array, or 0 if not in IEEE standard C layout
 int svSizeOfArray(const svOpenArrayHandle h) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h);
     if (VL_UNLIKELY(!varp->isDpiStdLayout())) return 0;
     // Truncate 64 bits to int; DPI is limited to 4GB
     return static_cast<int>(varp->totalSize());
@@ -264,22 +264,22 @@ static void* _vl_svGetArrElemPtr(const svOpenArrayHandle h, int nargs, int indx1
                                  int indx3) VL_MT_SAFE {
     const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
     if (VL_UNLIKELY(!varp->isDpiStdLayout())) return nullptr;
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     return datap;
 }
 
 // Copy to user bit array from simulator open array
 static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int nargs,
                                       int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: d[0] = *(reinterpret_cast<CData*>(datap)); return;
     case VLVT_UINT16: d[0] = *(reinterpret_cast<SData*>(datap)); return;
     case VLVT_UINT32: d[0] = *(reinterpret_cast<IData*>(datap)); return;
     case VLVT_UINT64: {
-        WData lwp[2];
+        VlWide<2> lwp;
         VL_SET_WQ(lwp, *(reinterpret_cast<QData*>(datap)));
         d[0] = lwp[0];
         d[1] = lwp[1];
@@ -299,8 +299,8 @@ static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s,
 // Copy to user logic array from simulator open array
 static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int nargs,
                                         int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8:
@@ -316,7 +316,7 @@ static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandl
         d[0].bval = 0;
         return;
     case VLVT_UINT64: {
-        WData lwp[2];
+        VlWide<2> lwp;
         VL_SET_WQ(lwp, *(reinterpret_cast<QData*>(datap)));
         d[0].aval = lwp[0];
         d[0].bval = 0;
@@ -342,8 +342,8 @@ static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandl
 // Copy to simulator open array from from user bit array
 static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int nargs,
                                       int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: *(reinterpret_cast<CData*>(datap)) = s[0]; return;
@@ -364,8 +364,8 @@ static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecV
 // Copy to simulator open array from from user logic array
 static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s,
                                         int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: *(reinterpret_cast<CData*>(datap)) = s[0].aval; return;
@@ -386,10 +386,10 @@ static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogic
 
 // Return bit from simulator open array
 static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1, int indx2,
-                                 int indx3, int indx4) VL_MT_SAFE {
+                                 int indx3, int) VL_MT_SAFE {
     // One extra index supported, as need bit number
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return 0;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: return (*(reinterpret_cast<CData*>(datap))) & 1;
@@ -401,11 +401,11 @@ static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1
 }
 // Update simulator open array from bit
 static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int nargs, int indx1,
-                                int indx2, int indx3, int indx4) VL_MT_SAFE {
+                                int indx2, int indx3, int) VL_MT_SAFE {
     // One extra index supported, as need bit number
     value &= 1;  // Make sure clean
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
-    void* datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
+    void* const datap = _vl_sv_adjusted_datap(varp, nargs, indx1, indx2, indx3);
     if (VL_UNLIKELY(!datap)) return;
     switch (varp->vltype()) {  // LCOV_EXCL_BR_LINE
     case VLVT_UINT8: *(reinterpret_cast<CData*>(datap)) = value; return;
@@ -417,10 +417,10 @@ static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int narg
 }
 
 //======================================================================
-// DPI accessors that simply call above functions
+// DPI accessors that call above functions
 
 void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h);
     void* datap;
     va_list ap;
     va_start(ap, indx1);
@@ -428,13 +428,13 @@ void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) {
     switch (varp->udims()) {
     case 1: datap = _vl_svGetArrElemPtr(h, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         datap = _vl_svGetArrElemPtr(h, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         datap = _vl_svGetArrElemPtr(h, 3, indx1, indx2, indx3);
         break;
     }
@@ -454,19 +454,19 @@ void* svGetArrElemPtr3(const svOpenArrayHandle h, int indx1, int indx2, int indx
 }
 
 void svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutBitArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutBitArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -486,19 +486,19 @@ void svPutBitArrElem3VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int
     _vl_svPutBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
 }
 void svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutLogicArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutLogicArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -522,19 +522,19 @@ void svPutLogicArrElem3VecVal(const svOpenArrayHandle d, const svLogicVecVal* s,
 // From simulator storage into user space
 
 void svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svGetBitArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svGetBitArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svGetBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -553,19 +553,19 @@ void svGetBitArrElem3VecVal(svBitVecVal* d, const svOpenArrayHandle s, int indx1
     _vl_svGetBitArrElemVecVal(d, s, 3, indx1, indx2, indx3);
 }
 void svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svGetLogicArrElemVecVal(d, s, 1, indx1, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svGetLogicArrElemVecVal(d, s, 2, indx1, indx2, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svGetLogicArrElemVecVal(d, s, 3, indx1, indx2, indx3);
         break;
     }
@@ -585,20 +585,20 @@ void svGetLogicArrElem3VecVal(svLogicVecVal* d, const svOpenArrayHandle s, int i
 }
 
 svBit svGetBitArrElem(const svOpenArrayHandle s, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     svBit out;
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: out = _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -618,20 +618,20 @@ svBit svGetBitArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int indx
 }
 svLogic svGetLogicArrElem(const svOpenArrayHandle s, int indx1, ...) {
     // Verilator doesn't support X/Z so can just call Bit version
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(s);
     svBit out;
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: out = _vl_svGetBitArrElem(s, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         out = _vl_svGetBitArrElem(s, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -654,19 +654,19 @@ svLogic svGetLogicArrElem3(const svOpenArrayHandle s, int indx1, int indx2, int
 }
 
 void svPutBitArrElem(const svOpenArrayHandle d, svBit value, int indx1, ...) {
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -685,19 +685,19 @@ void svPutBitArrElem3(const svOpenArrayHandle d, svBit value, int indx1, int ind
 }
 void svPutLogicArrElem(const svOpenArrayHandle d, svLogic value, int indx1, ...) {
     // Verilator doesn't support X/Z so can just call Bit version
-    const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d);
+    const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(d);
     va_list ap;
     va_start(ap, indx1);
     switch (varp->udims()) {
     case 1: _vl_svPutBitArrElem(d, value, 1, indx1, 0, 0, 0); break;
     case 2: {
-        int indx2 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 2, indx1, indx2, 0, 0);
         break;
     }
     case 3: {
-        int indx2 = va_arg(ap, int);
-        int indx3 = va_arg(ap, int);
+        const int indx2 = va_arg(ap, int);
+        const int indx3 = va_arg(ap, int);
         _vl_svPutBitArrElem(d, value, 3, indx1, indx2, indx3, 0);
         break;
     }
@@ -732,15 +732,15 @@ svScope svGetScope() {
 }
 
 svScope svSetScope(const svScope scope) {
-    const VerilatedScope* prevScopep = Verilated::dpiScope();
-    const VerilatedScope* vscopep = reinterpret_cast<const VerilatedScope*>(scope);
+    const VerilatedScope* const prevScopep = Verilated::dpiScope();
+    const VerilatedScope* const vscopep = reinterpret_cast<const VerilatedScope*>(scope);
     Verilated::dpiScope(vscopep);
     // NOLINTNEXTLINE(google-readability-casting)
     return (svScope)(prevScopep);
 }
 
 const char* svGetNameFromScope(const svScope scope) {
-    const VerilatedScope* vscopep = reinterpret_cast<const VerilatedScope*>(scope);
+    const VerilatedScope* const vscopep = reinterpret_cast<const VerilatedScope*>(scope);
     return vscopep->name();
 }
 

include/verilated_dpi.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -37,7 +37,7 @@
 
 // Convert svBitVecVal to Verilator internal data
 static inline void VL_SET_W_SVBV(int obits, WDataOutP owp, const svBitVecVal* lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i];
     owp[words - 1] = lwp[words - 1] & VL_MASK_I(obits);
 }
@@ -47,20 +47,20 @@ static inline QData VL_SET_Q_SVBV(const svBitVecVal* lwp) VL_MT_SAFE {
 static inline IData VL_SET_I_SVBV(const svBitVecVal* lwp) VL_MT_SAFE { return lwp[0]; }
 
 // Convert Verilator internal data to svBitVecVal
-static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, WDataInP lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+static inline void VL_SET_SVBV_W(int obits, svBitVecVal* owp, const WDataInP lwp) VL_MT_SAFE {
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i];
     owp[words - 1] = lwp[words - 1] & VL_MASK_I(obits);
 }
-static inline void VL_SET_SVBV_I(int, svBitVecVal* owp, IData ld) VL_MT_SAFE { owp[0] = ld; }
-static inline void VL_SET_SVBV_Q(int, svBitVecVal* owp, QData ld) VL_MT_SAFE {
+static inline void VL_SET_SVBV_I(int, svBitVecVal* owp, const IData ld) VL_MT_SAFE { owp[0] = ld; }
+static inline void VL_SET_SVBV_Q(int, svBitVecVal* owp, const QData ld) VL_MT_SAFE {
     VL_SET_WQ(owp, ld);
 }
 
 // Convert svLogicVecVal to Verilator internal data
 // Note these functions ignore X/Z in svLogicVecVal
 static inline void VL_SET_W_SVLV(int obits, WDataOutP owp, const svLogicVecVal* lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words - 1; ++i) owp[i] = lwp[i].aval;
     owp[words - 1] = lwp[words - 1].aval & VL_MASK_I(obits);
 }
@@ -71,18 +71,18 @@ static inline IData VL_SET_I_SVLV(const svLogicVecVal* lwp) VL_MT_SAFE { return
 
 // Convert Verilator internal data to svLogicVecVal
 // Note these functions never create X/Z in svLogicVecVal
-static inline void VL_SET_SVLV_W(int obits, svLogicVecVal* owp, WDataInP lwp) VL_MT_SAFE {
-    int words = VL_WORDS_I(obits);
+static inline void VL_SET_SVLV_W(int obits, svLogicVecVal* owp, const WDataInP lwp) VL_MT_SAFE {
+    const int words = VL_WORDS_I(obits);
     for (int i = 0; i < words; ++i) owp[i].bval = 0;
     for (int i = 0; i < words - 1; ++i) owp[i].aval = lwp[i];
     owp[words - 1].aval = lwp[words - 1] & VL_MASK_I(obits);
 }
-static inline void VL_SET_SVLV_I(int, svLogicVecVal* owp, IData ld) VL_MT_SAFE {
+static inline void VL_SET_SVLV_I(int, svLogicVecVal* owp, const IData ld) VL_MT_SAFE {
     owp[0].aval = ld;
     owp[0].bval = 0;
 }
-static inline void VL_SET_SVLV_Q(int, svLogicVecVal* owp, QData ld) VL_MT_SAFE {
-    WData lwp[2];
+static inline void VL_SET_SVLV_Q(int, svLogicVecVal* owp, const QData ld) VL_MT_SAFE {
+    VlWide<2> lwp;
     VL_SET_WQ(lwp, ld);
     owp[0].aval = lwp[0];
     owp[0].bval = 0;

include/verilated_fst_c.cpp

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -53,37 +53,41 @@
 
 //=============================================================================
 // Check that vltscope_t matches fstScopeType
-static_assert((int)FST_ST_VCD_MODULE == (int)VLT_TRACE_SCOPE_MODULE,
+
+static_assert(static_cast<int>(FST_ST_VCD_MODULE) == static_cast<int>(VLT_TRACE_SCOPE_MODULE),
               "VLT_TRACE_SCOPE_MODULE mismatches");
-static_assert((int)FST_ST_VCD_TASK == (int)VLT_TRACE_SCOPE_TASK,
+static_assert(static_cast<int>(FST_ST_VCD_TASK) == static_cast<int>(VLT_TRACE_SCOPE_TASK),
               "VLT_TRACE_SCOPE_TASK mismatches");
-static_assert((int)FST_ST_VCD_FUNCTION == (int)VLT_TRACE_SCOPE_FUNCTION,
+static_assert(static_cast<int>(FST_ST_VCD_FUNCTION) == static_cast<int>(VLT_TRACE_SCOPE_FUNCTION),
               "VLT_TRACE_SCOPE_FUNCTION mismatches");
-static_assert((int)FST_ST_VCD_BEGIN == (int)VLT_TRACE_SCOPE_BEGIN,
+static_assert(static_cast<int>(FST_ST_VCD_BEGIN) == static_cast<int>(VLT_TRACE_SCOPE_BEGIN),
               "VLT_TRACE_SCOPE_BEGIN mismatches");
-static_assert((int)FST_ST_VCD_FORK == (int)VLT_TRACE_SCOPE_FORK,
+static_assert(static_cast<int>(FST_ST_VCD_FORK) == static_cast<int>(VLT_TRACE_SCOPE_FORK),
               "VLT_TRACE_SCOPE_FORK mismatches");
-static_assert((int)FST_ST_VCD_GENERATE == (int)VLT_TRACE_SCOPE_GENERATE,
+static_assert(static_cast<int>(FST_ST_VCD_GENERATE) == static_cast<int>(VLT_TRACE_SCOPE_GENERATE),
               "VLT_TRACE_SCOPE_GENERATE mismatches");
-static_assert((int)FST_ST_VCD_STRUCT == (int)VLT_TRACE_SCOPE_STRUCT,
+static_assert(static_cast<int>(FST_ST_VCD_STRUCT) == static_cast<int>(VLT_TRACE_SCOPE_STRUCT),
               "VLT_TRACE_SCOPE_STRUCT mismatches");
-static_assert((int)FST_ST_VCD_UNION == (int)VLT_TRACE_SCOPE_UNION,
+static_assert(static_cast<int>(FST_ST_VCD_UNION) == static_cast<int>(VLT_TRACE_SCOPE_UNION),
               "VLT_TRACE_SCOPE_UNION mismatches");
-static_assert((int)FST_ST_VCD_CLASS == (int)VLT_TRACE_SCOPE_CLASS,
+static_assert(static_cast<int>(FST_ST_VCD_CLASS) == static_cast<int>(VLT_TRACE_SCOPE_CLASS),
               "VLT_TRACE_SCOPE_CLASS mismatches");
-static_assert((int)FST_ST_VCD_INTERFACE == (int)VLT_TRACE_SCOPE_INTERFACE,
+static_assert(static_cast<int>(FST_ST_VCD_INTERFACE)
+                  == static_cast<int>(VLT_TRACE_SCOPE_INTERFACE),
               "VLT_TRACE_SCOPE_INTERFACE mismatches");
-static_assert((int)FST_ST_VCD_PACKAGE == (int)VLT_TRACE_SCOPE_PACKAGE,
+static_assert(static_cast<int>(FST_ST_VCD_PACKAGE) == static_cast<int>(VLT_TRACE_SCOPE_PACKAGE),
               "VLT_TRACE_SCOPE_PACKAGE mismatches");
-static_assert((int)FST_ST_VCD_PROGRAM == (int)VLT_TRACE_SCOPE_PROGRAM,
+static_assert(static_cast<int>(FST_ST_VCD_PROGRAM) == static_cast<int>(VLT_TRACE_SCOPE_PROGRAM),
               "VLT_TRACE_SCOPE_PROGRAM mismatches");
 
 //=============================================================================
 // Specialization of the generics for this trace format
 
-#define VL_DERIVED_T VerilatedFst
-#include "verilated_trace_imp.cpp"
-#undef VL_DERIVED_T
+#define VL_SUB_T VerilatedFst
+#define VL_BUF_T VerilatedFstBuffer
+#include "verilated_trace_imp.h"
+#undef VL_SUB_T
+#undef VL_BUF_T
 
 //=============================================================================
 // VerilatedFst
@@ -98,7 +102,7 @@ VerilatedFst::~VerilatedFst() {
 }
 
 void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
-    const VerilatedLockGuard lock(m_mutex);
+    const VerilatedLockGuard lock{m_mutex};
     m_fst = fstWriterCreate(filename, 1);
     fstWriterSetPackType(m_fst, FST_WR_PT_LZ4);
     fstWriterSetTimescaleFromString(m_fst, timeResStr().c_str());  // lintok-begin-on-ref
@@ -109,7 +113,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 
     m_curScope.clear();
 
-    VerilatedTrace<VerilatedFst>::traceInit();
+    Super::traceInit();
 
     // Clear the scope stack
     auto it = m_curScope.begin();
@@ -120,7 +124,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 
     // convert m_code2symbol into an array for fast lookup
     if (!m_symbolp) {
-        m_symbolp = new fstHandle[nextCode()];
+        m_symbolp = new fstHandle[nextCode()]{0};
         for (const auto& i : m_code2symbol) m_symbolp[i.first] = i.second;
     }
     m_code2symbol.clear();
@@ -130,44 +134,46 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
 }
 
 void VerilatedFst::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
-    const VerilatedLockGuard lock(m_mutex);
-    VerilatedTrace<VerilatedFst>::closeBase();
+    const VerilatedLockGuard lock{m_mutex};
+    Super::closeBase();
     fstWriterClose(m_fst);
     m_fst = nullptr;
 }
 
 void VerilatedFst::flush() VL_MT_SAFE_EXCLUDES(m_mutex) {
-    const VerilatedLockGuard lock(m_mutex);
-    VerilatedTrace<VerilatedFst>::flushBase();
+    const VerilatedLockGuard lock{m_mutex};
+    Super::flushBase();
     fstWriterFlushContext(m_fst);
 }
 
-void VerilatedFst::emitTimeChange(vluint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); }
+void VerilatedFst::emitTimeChange(uint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); }
 
 //=============================================================================
 // Decl
 
-void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elements,
+void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elements,
                                  unsigned int minValbits, const char** itemNamesp,
                                  const char** itemValuesp) {
-    fstEnumHandle enumNum
+    const fstEnumHandle enumNum
         = fstWriterCreateEnumTable(m_fst, name, elements, minValbits, itemNamesp, itemValuesp);
     m_local2fstdtype[dtypenum] = enumNum;
 }
 
-void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
-                           fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
+void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                           fstVarType vartype, bool array, int arraynum, bool bussed, int msb,
+                           int lsb) {
     const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1;
 
-    VerilatedTrace<VerilatedFst>::declCode(code, bits, false);
+    const bool enabled = Super::declCode(code, name, bits, false);
+    if (!enabled) return;
 
-    std::istringstream nameiss(name);
+    std::string nameasstr = namePrefix() + name;
+    std::istringstream nameiss{nameasstr};
     std::istream_iterator<std::string> beg(nameiss);
     std::istream_iterator<std::string> end;
     std::list<std::string> tokens(beg, end);  // Split name
-    std::string symbol_name(tokens.back());
+    std::string symbol_name{tokens.back()};
     tokens.pop_back();  // Remove symbol name from hierarchy
-    tokens.insert(tokens.begin(), moduleName());  // Add current module to the hierarchy
     std::string tmpModName;
 
     // Find point where current and new scope diverge
@@ -191,22 +197,23 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV
             tmpModName = *new_it;
             tmpModName.pop_back();
             // If the scope ends with a non-ascii character, it will be 0x80 + fstScopeType
-            fstWriterSetScope(m_fst, (fstScopeType)(new_it->back() & 0x7f), tmpModName.c_str(),
-                              nullptr);
-        } else
+            fstWriterSetScope(m_fst, static_cast<fstScopeType>(new_it->back() & 0x7f),
+                              tmpModName.c_str(), nullptr);
+        } else {
             fstWriterSetScope(m_fst, FST_ST_VCD_SCOPE, new_it->c_str(), nullptr);
-
+        }
         m_curScope.push_back(*new_it);
         new_it = tokens.erase(new_it);
     }
 
     std::stringstream name_ss;
     name_ss << symbol_name;
-    if (array) name_ss << "(" << arraynum << ")";
+    if (array) name_ss << "[" << arraynum << "]";
+    if (bussed) name_ss << " [" << msb << ":" << lsb << "]";
     std::string name_str = name_ss.str();
 
     if (dtypenum > 0) {
-        fstEnumHandle enumNum = m_local2fstdtype[dtypenum];
+        const fstEnumHandle enumNum = m_local2fstdtype[dtypenum];
         fstWriterEmitEnumTableRef(m_fst, enumNum);
     }
 
@@ -219,66 +226,95 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV
     }
 }
 
-void VerilatedFst::declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                            fstVarType vartype, bool array, int arraynum) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, 0, 0);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0);
 }
-void VerilatedFst::declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                            fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb);
 }
-void VerilatedFst::declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declQuad(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                             fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb);
 }
-void VerilatedFst::declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declArray(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                              fstVarType vartype, bool array, int arraynum, int msb, int lsb) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, msb, lsb);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb);
 }
-void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+void VerilatedFst::declDouble(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                               fstVarType vartype, bool array, int arraynum) {
-    declare(code, name, dtypenum, vardir, vartype, array, arraynum, 63, 0);
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 63, 0);
 }
 
+//=============================================================================
+// Get/commit trace buffer
+
+VerilatedFstBuffer* VerilatedFst::getTraceBuffer() { return new VerilatedFstBuffer{*this}; }
+
+void VerilatedFst::commitTraceBuffer(VerilatedFstBuffer* bufp) {
+#ifdef VL_TRACE_OFFLOAD
+    if (bufp->m_offloadBufferWritep) {
+        m_offloadBufferWritep = bufp->m_offloadBufferWritep;
+        return;  // Buffer will be deleted by the offload thread
+    }
+#endif
+    delete bufp;
+}
+
+//=============================================================================
+// VerilatedFstBuffer implementation
+
+VerilatedFstBuffer::VerilatedFstBuffer(VerilatedFst& owner)
+    : VerilatedTraceBuffer<VerilatedFst, VerilatedFstBuffer>{owner} {}
+
+//=============================================================================
+// Trace rendering primitives
+
 // Note: emit* are only ever called from one place (full* in
-// verilated_trace_imp.cpp, which is included in this file at the top),
+// verilated_trace_imp.h, which is included in this file at the top),
 // so always inline them.
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitBit(vluint32_t code, CData newval) {
+void VerilatedFstBuffer::emitBit(uint32_t code, CData newval) {
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     fstWriterEmitValueChange(m_fst, m_symbolp[code], newval ? "1" : "0");
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) {
+void VerilatedFstBuffer::emitCData(uint32_t code, CData newval, int bits) {
     char buf[VL_BYTESIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtCDataToStr(buf, newval << (VL_BYTESIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) {
+void VerilatedFstBuffer::emitSData(uint32_t code, SData newval, int bits) {
     char buf[VL_SHORTSIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtSDataToStr(buf, newval << (VL_SHORTSIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) {
+void VerilatedFstBuffer::emitIData(uint32_t code, IData newval, int bits) {
     char buf[VL_IDATASIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtIDataToStr(buf, newval << (VL_IDATASIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitQData(vluint32_t code, QData newval, int bits) {
+void VerilatedFstBuffer::emitQData(uint32_t code, QData newval, int bits) {
     char buf[VL_QUADSIZE];
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
     cvtQDataToStr(buf, newval << (VL_QUADSIZE - bits));
     fstWriterEmitValueChange(m_fst, m_symbolp[code], buf);
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) {
+void VerilatedFstBuffer::emitWData(uint32_t code, const WData* newvalp, int bits) {
     int words = VL_WORDS_I(bits);
     char* wp = m_strbuf;
     // Convert the most significant word
@@ -294,6 +330,6 @@ void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) {
 }
 
 VL_ATTR_ALWINLINE
-void VerilatedFst::emitDouble(vluint32_t code, double newval) {
+void VerilatedFstBuffer::emitDouble(uint32_t code, double newval) {
     fstWriterEmitValueChange(m_fst, m_symbolp[code], &newval);
 }

include/verilated_fst_c.h

@@ -3,7 +3,7 @@
 //
 // Code available from: https://verilator.org
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -31,21 +31,25 @@
 #include <string>
 #include <vector>
 
+class VerilatedFstBuffer;
+
 //=============================================================================
 // VerilatedFst
 // Base class to create a Verilator FST dump
 // This is an internally used class - see VerilatedFstC for what to call from applications
 
-class VerilatedFst final : public VerilatedTrace<VerilatedFst> {
+class VerilatedFst final : public VerilatedTrace<VerilatedFst, VerilatedFstBuffer> {
+public:
+    using Super = VerilatedTrace<VerilatedFst, VerilatedFstBuffer>;
+
 private:
-    // Give the superclass access to private bits (to avoid virtual functions)
-    friend class VerilatedTrace<VerilatedFst>;
+    friend Buffer;  // Give the buffer access to the private bits
 
     //=========================================================================
     // FST specific internals
 
     void* m_fst;
-    std::map<vluint32_t, fstHandle> m_code2symbol;
+    std::map<uint32_t, fstHandle> m_code2symbol;
     std::map<int, fstEnumHandle> m_local2fstdtype;
     std::list<std::string> m_curScope;
     fstHandle* m_symbolp = nullptr;  // same as m_code2symbol, but as an array
@@ -53,38 +57,33 @@ private:
 
     // CONSTRUCTORS
     VL_UNCOPYABLE(VerilatedFst);
-    void declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
-                 fstVarType vartype, bool array, int arraynum, int msb, int lsb);
+    void declare(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                 fstVarType vartype, bool array, int arraynum, bool bussed, int msb, int lsb);
 
 protected:
     //=========================================================================
     // Implementation of VerilatedTrace interface
 
-    // Implementations of protected virtual methods for VerilatedTrace
-    virtual void emitTimeChange(vluint64_t timeui) override;
+    // Called when the trace moves forward to a new time point
+    virtual void emitTimeChange(uint64_t timeui) override;
 
     // Hooks called from VerilatedTrace
     virtual bool preFullDump() override { return isOpen(); }
     virtual bool preChangeDump() override { return isOpen(); }
 
-    // Implementations of duck-typed methods for VerilatedTrace. These are
-    // called from only one place (namely full*) so always inline them.
-    inline void emitBit(vluint32_t code, CData newval);
-    inline void emitCData(vluint32_t code, CData newval, int bits);
-    inline void emitSData(vluint32_t code, SData newval, int bits);
-    inline void emitIData(vluint32_t code, IData newval, int bits);
-    inline void emitQData(vluint32_t code, QData newval, int bits);
-    inline void emitWData(vluint32_t code, const WData* newvalp, int bits);
-    inline void emitDouble(vluint32_t code, double newval);
+    // Trace buffer management
+    virtual VerilatedFstBuffer* getTraceBuffer() override;
+    virtual void commitTraceBuffer(VerilatedFstBuffer*) override;
 
 public:
     //=========================================================================
     // External interface to client code
-    // (All must be threadsafe)
 
+    // CONSTRUCTOR
     explicit VerilatedFst(void* fst = nullptr);
     ~VerilatedFst();
 
+    // METHODS - All must be thread safe
     // Open the file; call isOpen() to see if errors
     void open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex);
     // Close the file
@@ -97,32 +96,65 @@ public:
     //=========================================================================
     // Internal interface to Verilator generated code
 
-    // Inside dumping routines, declare a data type
-    void declDTypeEnum(int dtypenum, const char* name, vluint32_t elements,
-                       unsigned int minValbits, const char** itemNamesp, const char** itemValuesp);
-
-    // Inside dumping routines, declare a signal
-    void declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                  fstVarType vartype, bool array, int arraynum);
-    void declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                  fstVarType vartype, bool array, int arraynum, int msb, int lsb);
-    void declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declQuad(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                   fstVarType vartype, bool array, int arraynum, int msb, int lsb);
-    void declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declArray(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                    fstVarType vartype, bool array, int arraynum, int msb, int lsb);
-    void declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+    void declDouble(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                     fstVarType vartype, bool array, int arraynum);
+
+    void declDTypeEnum(int dtypenum, const char* name, uint32_t elements, unsigned int minValbits,
+                       const char** itemNamesp, const char** itemValuesp);
 };
 
 #ifndef DOXYGEN
 // Declare specialization here as it's used in VerilatedFstC just below
-template <> void VerilatedTrace<VerilatedFst>::dump(vluint64_t timeui);
-template <> void VerilatedTrace<VerilatedFst>::set_time_unit(const char* unitp);
-template <> void VerilatedTrace<VerilatedFst>::set_time_unit(const std::string& unit);
-template <> void VerilatedTrace<VerilatedFst>::set_time_resolution(const char* unitp);
-template <> void VerilatedTrace<VerilatedFst>::set_time_resolution(const std::string& unit);
+template <> void VerilatedFst::Super::dump(uint64_t time);
+template <> void VerilatedFst::Super::set_time_unit(const char* unitp);
+template <> void VerilatedFst::Super::set_time_unit(const std::string& unit);
+template <> void VerilatedFst::Super::set_time_resolution(const char* unitp);
+template <> void VerilatedFst::Super::set_time_resolution(const std::string& unit);
+template <> void VerilatedFst::Super::dumpvars(int level, const std::string& hier);
 #endif
 
+//=============================================================================
+// VerilatedFstBuffer
+
+class VerilatedFstBuffer final : public VerilatedTraceBuffer<VerilatedFst, VerilatedFstBuffer> {
+    // Give the trace file access to the private bits
+    friend VerilatedFst;
+    friend VerilatedFst::Super;
+
+    // The FST file handle
+    void* const m_fst = m_owner.m_fst;
+    // code to fstHande map, as an array
+    const fstHandle* const m_symbolp = m_owner.m_symbolp;
+    // String buffer long enough to hold maxBits() chars
+    char* const m_strbuf = m_owner.m_strbuf;
+
+public:
+    // CONSTRUCTOR
+    explicit VerilatedFstBuffer(VerilatedFst& owner);
+    ~VerilatedFstBuffer() = default;
+
+    //=========================================================================
+    // Implementation of VerilatedTraceBuffer interface
+
+    // Implementations of duck-typed methods for VerilatedTraceBuffer. These are
+    // called from only one place (the full* methods), so always inline them.
+    VL_ATTR_ALWINLINE inline void emitBit(uint32_t code, CData newval);
+    VL_ATTR_ALWINLINE inline void emitCData(uint32_t code, CData newval, int bits);
+    VL_ATTR_ALWINLINE inline void emitSData(uint32_t code, SData newval, int bits);
+    VL_ATTR_ALWINLINE inline void emitIData(uint32_t code, IData newval, int bits);
+    VL_ATTR_ALWINLINE inline void emitQData(uint32_t code, QData newval, int bits);
+    VL_ATTR_ALWINLINE inline void emitWData(uint32_t code, const WData* newvalp, int bits);
+    VL_ATTR_ALWINLINE inline void emitDouble(uint32_t code, double newval);
+};
+
 //=============================================================================
 // VerilatedFstC
 /// Create a FST dump file in C standalone (no SystemC) simulations.
@@ -139,7 +171,7 @@ public:
     explicit VerilatedFstC(void* filep = nullptr)
         : m_sptrace{filep} {}
     /// Destruct, flush, and close the dump
-    ~VerilatedFstC() { close(); }
+    virtual ~VerilatedFstC() { close(); }
 
     // METHODS - User called
 
@@ -152,12 +184,14 @@ public:
     /// Flush dump
     void flush() VL_MT_SAFE { m_sptrace.flush(); }
     /// Write one cycle of dump data
-    void dump(vluint64_t timeui) { m_sptrace.dump(timeui); }
+    /// Call with the current context's time just after eval'ed,
+    /// e.g. ->dump(contextp->time())
+    void dump(uint64_t timeui) { m_sptrace.dump(timeui); }
     /// Write one cycle of dump data - backward compatible and to reduce
-    /// conversion warnings.  It's better to use a vluint64_t time instead.
-    void dump(double timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
-    void dump(vluint32_t timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
-    void dump(int timestamp) { dump(static_cast<vluint64_t>(timestamp)); }
+    /// conversion warnings.  It's better to use a uint64_t time instead.
+    void dump(double timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+    void dump(uint32_t timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+    void dump(int timestamp) { dump(static_cast<uint64_t>(timestamp)); }
 
     // METHODS - Internal/backward compatible
     // \protectedsection
@@ -176,9 +210,14 @@ public:
     void set_time_resolution(const std::string& unit) VL_MT_SAFE {
         m_sptrace.set_time_resolution(unit);
     }
+    // Set variables to dump, using $dumpvars format
+    // If level = 0, dump everything and hier is then ignored
+    void dumpvars(int level, const std::string& hier) VL_MT_SAFE {
+        m_sptrace.dumpvars(level, hier);
+    }
 
     // Internal class access
-    inline VerilatedFst* spTrace() { return &m_sptrace; };
+    inline VerilatedFst* spTrace() { return &m_sptrace; }
 };
 
 #endif  // guard

include/verilated_fst_sc.cpp

@@ -3,7 +3,7 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+// Copyright 2001-2022 by Wilson Snyder. This program is free software; you
 // can redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
@@ -27,6 +27,17 @@
 //======================================================================
 //======================================================================
 
+void VerilatedFstSc::open(const char* filename) {
+    if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+        vl_fatal(__FILE__, __LINE__, "VerilatedFstSc",
+                 ("%Error: VerilatedFstSc::open(\"" + std::string(filename)
+                  + "\") is called before sc_core::sc_start(). "
+                    "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.")
+                     .c_str());
+    }
+    VerilatedFstC::open(filename);
+}
+
 //--------------------------------------------------
 // SystemC 2.1.v1
 // cppcheck-suppress unusedFunction