Version bump

* v3Os: include <windows.h> instead of <winnt.h>

The windows.h header file should be included prior to any other headers,
in order to ensure all definitions are available.  By only including
some headers, such as winnt.h, many "undefined symbol" messages are
generated.

Include "windows.h" to fix the build on msys2 under mingw64.

Signed-off-by: Sean Cross <[email protected]>

* configure: check for bcrypt and psapi on windows

These two libraries must be linked in order to have access to
BCryptGenRandom and GetProcessMemoryInfo respectively.

Signed-off-by: Sean Cross <[email protected]>

.clang-format

@@ -90,10 +90,6 @@ PenaltyBreakString: 1000
 PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
 PointerAlignment: Left
-RawStringFormats: 
-  - Delimiter:       pb
-    Language:        TextProto
-    BasedOnStyle:    google
 ReflowComments:  true
 SortIncludes:    false
 SortUsingDeclarations: true
@@ -108,7 +104,7 @@ SpacesInContainerLiterals: true
 SpacesInCStyleCastParentheses: false
 SpacesInParentheses: false
 SpacesInSquareBrackets: false
-Standard:        Cpp11
+Standard:        Cpp03
 TabWidth:        8
 UseTab:          Never
 ...

.codacy.yml

@@ -1,4 +1,5 @@
 ---
 exclude_paths:
+  - '.github/**'
   - 'ci/build_verilator.sh'
   - 'include/vltstd/**'

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,14 @@
+---
+name: Bug report
+about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/.github/blob/master/CONTRIBUTING.adoc)
+title: ''
+labels: new
+assignees: ''
+
+---
+
+Thanks for taking the time to report this.
+
+Can you attach an example that shows the issue?  (Must be openly licensed, ideally in test_regress format.)
+
+May we assist you in trying to fix this yourself?

.github/ISSUE_TEMPLATE/feature.md

@@ -0,0 +1,16 @@
+---
+name: Feature Request
+about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/.github/blob/master/CONTRIBUTING.adoc)
+title: ''
+labels: new
+assignees: ''
+
+---
+
+Thanks for taking the time to report this.
+
+What would you like added/supported?
+
+Can you attach an example that runs on other simulators?  (Must be openly licensed, ideally in test_regress format.)
+
+May we assist you in trying to fix this yourself?

.github/ISSUE_TEMPLATE/questions.md

@@ -0,0 +1,10 @@
+---
+name: Q and A, or Other
+about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/.github/blob/master/CONTRIBUTING.adoc)
+title: ''
+labels: new
+assignees: ''
+
+---
+
+How may we help - what is your question?

.github/PULL_REQUEST_TEMPLATE.md

@@ -0,0 +1 @@
+We appreciate your contributing to Verilator.  If this is your first commit, please add your name to docs/CONTRIBUTORS, and read our contributing guidelines in docs/CONTRIBUTING.adoc.

.github/labels.toml

@@ -0,0 +1,199 @@
+["area: assertions"]
+color = "ffffe8"
+name = "area: assertions"
+description = "Issue involves assertions"
+
+["area: configure/compiling"]
+color = "ffffe8"
+name = "area: configure/compiling"
+description = "Issue involves configuring or compilating Verilator itself"
+
+["area: coverage"]
+color = "ffffe8"
+name = "area: coverage"
+description = "Issue involves coverage generation"
+
+["area: data-types"]
+color = "ffffe8"
+name = "area: data-types"
+description = "Issue involves data-types"
+
+["area: documentation"]
+color = "ffffe8"
+name = "area: documentation"
+description = "Issue involves documentation"
+
+["area: elaboration"]
+color = "ffffe8"
+name = "area: elaboration"
+description = "Issue involves elaboration phase"
+
+["area: invoking/options"]
+color = "ffffe8"
+name = "area: invoking/options"
+description = "Issue involves options passed to Verilator"
+
+["area: lint"]
+color = "ffffe8"
+name = "area: lint"
+description = "Issue involves SystemVerilog lint checking"
+
+["area: parser"]
+color = "ffffe8"
+name = "area: parser"
+description = "Issue involves SystemVerilog parsing"
+
+["area: performance"]
+color = "ffffe8"
+name = "area: performance"
+description = "Issue involves performance issues"
+
+["area: portability"]
+color = "ffffe8"
+name = "area: portability"
+description = "Issue involves operating system/compiler portability"
+
+["area: runtime result"]
+color = "ffffe8"
+name = "area: runtime result"
+description = "Issue involves an incorrect runtine result from Verilated model"
+
+["area: scheduling"]
+color = "ffffe8"
+name = "area: scheduling"
+description = "Issue involves scheduling/ordering of events"
+
+["area: tests"]
+color = "ffffe8"
+name = "area: tests"
+description = "Issue involves the testing system"
+
+["area: usability"]
+color = "ffffe8"
+name = "area: usability"
+description = "Issue involves general usability"
+
+["effort: days"]
+color = "d0c0b0"
+name = "effort: days"
+description = "Expect this issue to require roughly days of invested effort to resolve"
+
+["effort: hours"]
+color = "f5e6d6"
+name = "effort: hours"
+description = "Expect this issue to require roughly hours of invested effort to resolve"
+
+["effort: minutes"]
+color = "f5e6d6"
+name = "effort: minutes"
+description = "Expect this issue to require less than an hour of invested effort to resolve"
+
+["effort: weeks"]
+color = "d0c0b0"
+name = "effort: weeks"
+description = "Expect this issue to require weeks or more of invested effort to resolve"
+
+["good first issue"]
+color = "7057ff"
+name = "good first issue"
+description = "Good for newcomers"
+
+["help wanted"]
+color = "008672"
+name = "help wanted"
+description = "Extra attention is needed"
+
+["new"]
+color = "ff4400"
+name = "new"
+description = "New issue, not yet seen by maintainers"
+
+["resolution: abandoned"]
+color = "cfd3d7"
+name = "resolution: abandoned"
+description = "Closed; not enough information or otherwise never finished"
+
+["resolution: answered"]
+color = "cfd3d7"
+name = "resolution: answered"
+description = "Closed; only applies to questions which were answered"
+
+["resolution: duplicate"]
+color = "cfd3d7"
+name = "resolution: duplicate"
+description = "Closed; issue or pull request already exists"
+
+["resolution: external"]
+color = "cfd3d7"
+name = "resolution: external"
+description = "Closed; passed to another tool's bug tracker"
+
+["resolution: fixed"]
+color = "cfd3d7"
+name = "resolution: fixed"
+description = "Closed; fixed"
+
+["resolution: invalid"]
+color = "cfd3d7"
+name = "resolution: invalid"
+description = "Closed; issue or pull request is no longer relevant"
+
+["resolution: no fix needed"]
+color = "cfd3d7"
+name = "resolution: no fix needed"
+description = "Closed; no fix required (not a bug)"
+
+["resolution: wontfix"]
+color = "cfd3d7"
+name = "resolution: wontfix"
+description = "Closed; work won't continue on an issue or pull request"
+
+["status: asked reporter"]
+color = "ffffff"
+name = "status: asked reporter"
+description = "Bug is waiting for reporter to answer a question"
+
+["status: assigned"]
+color = "a0f0ff"
+name = "status: assigned"
+description = "Issue is assigned to someone to work on"
+
+["status: blocked"]
+color = "00007f"
+name = "status: blocked"
+description = "Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned'"
+
+["status: discussion"]
+color = "d876e3"
+name = "status: discussion"
+description = "Issue is waiting for discussions to resolve"
+
+["status: ready"]
+color = "b6c92a"
+name = "status: ready"
+description = "Issue is ready for someone to fix; then goes to 'status: assigned'"
+
+["type: bug"]
+color = "d73a4a"
+name = "type: bug"
+description = "Defect"
+
+["type: feature-IEEE"]
+color = "cfccff"
+name = "type: feature-IEEE"
+description = "Request to add new feature, described in IEEE 1800"
+
+["type: feature-non-IEEE"]
+color = "cfccff"
+name = "type: feature-non-IEEE"
+description = "Request to add new feature, outside IEEE 1800"
+
+["type: maintenance"]
+color = "cfccff"
+name = "type: maintenance"
+description = "Internal maintenance task"
+
+["type: q and a"]
+color = "84ba34"
+name = "type: q and a"
+description = "Question and answer about some feature or user question"

.gitignore

@@ -17,6 +17,7 @@
 README
 TAGS
 autom4te.cache
+compile_commands.json
 config.cache
 config.status
 configure

.travis.yml

@@ -1,8 +1,10 @@
 # DESCRIPTION: Travis-CI config
 #
-# Copyright 2003-2019 by Todd Strader. Verilator is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU Lesser
-# General Public License Version 3 or the Perl Artistic License Version 2.0.
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 version: ~> 1.0
 
@@ -16,6 +18,7 @@ env:
     - VERILATOR_ROOT=$PWD
     - VERILATOR_NUM_JOBS=$(echo `nproc` + 1 | bc)
     - VERILATOR_CONFIG_FLAGS="--enable-maintainer-mode --enable-longtests"
+    - VERILATOR_AUTHOR_SITE=1
     - OBJCACHE=ccache
 
 cache:
@@ -24,9 +27,12 @@ cache:
 
 before_install:
 # Perl modules needed for testing
-  - yes yes | sudo cpan -fi Unix::Processors Parallel::Forker Bit::Vector
+# Not listing Bit::Vector as slow to install, and only skips one test
+  - yes yes | sudo cpan -fi Unix::Processors Parallel::Forker
   - sudo apt-get install gdb gtkwave
+  - sudo apt-get install libgoogle-perftools-dev
 before_script:
+  - bash -x ci/build_vcddiff.sh
   - bash -x ci/build_verilator.sh
 after_script:
   - ccache -s
@@ -55,9 +61,14 @@ jobs:
       script: ci/test.sh vlt
     - if: type != cron
       stage: test
-      name: Vltmt test
+      name: Vltmt set 0 test
       compiler: gcc
-      script: ci/test.sh vltmt
+      script: ci/test.sh vltmt0
+    - if: type != cron
+      stage: test
+      name: Vltmt set 1 test
+      compiler: gcc
+      script: ci/test.sh vltmt1
 # Cron builds try different OS/compiler combinations
     - if: type = cron
       stage: "Build Verilator"

MANIFEST.SKIP

@@ -2,6 +2,7 @@
 \.clang-tidy
 \.git/
 \.git$
+\.github/
 \.svn/
 \.(bak|old)/
 \.(bak|old)$
@@ -18,15 +19,16 @@
 \.codacy\.yml
 \.travis\.yml
 /build/
-/obj_dir/
 /obj_dbg/
+/obj_dir/
+/obj_dist/
+/obj_iv/
 /obj_nc/
 /obj_opt/
 /obj_vcs/
 /obj_vlt/
 /obj_vltmt/
-/obj_dist/
-/INCA_libs/
+INCA_libs/
 /cov_work/
 /logs/
 ^Makefile$
@@ -35,6 +37,7 @@ bin/verilator_bin.*
 bin/verilator_coverage_bin.*
 docs/.*\.html$
 docs/Makefile$
+docs/clang-format.txt$
 docs/doxygen-doc/.*
 examples/xml_py/copied/
 examples/xml_py/graph.*

Makefile.in

@@ -7,15 +7,11 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
-#
-# Verilator is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 #****************************************************************************/
 #
@@ -103,7 +99,7 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 
 SHELL = /bin/sh
 
-SUBDIRS = src test_regress \
+SUBDIRS = docs src test_regress \
 	examples/cmake_hello_c \
 	examples/cmake_hello_sc \
 	examples/cmake_tracing_c \
@@ -114,6 +110,7 @@ SUBDIRS = src test_regress \
 	examples/make_tracing_c \
 	examples/make_tracing_sc \
 	examples/make_protect_lib \
+	examples/xml_py \
 
 INFOS = verilator.txt verilator.html verilator.pdf
 
@@ -147,6 +144,7 @@ DISTFILES_INC = $(INFOS) .gitignore \
 	docs/install.adoc \
 	docs/internals.adoc \
 	docs/verilator_logo.png \
+	docs/xml.adoc \
 	install-sh configure *.pod \
 	include/*.[chv]* \
 	include/*.in \
@@ -206,12 +204,6 @@ EXAMPLES_FIRST = \
 
 EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*)))
 
-ifeq ($(OBJCACHE_JOBS),)
-ifneq ($(OBJCACHE_HOSTS),)
-export OBJCACHE_JOBS := -j $(shell objcache --jobs "$(OBJCACHE_HOSTS)")
-endif
-endif
-
 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
 VL_INST_MAN_FILES = verilator.1 verilator_coverage.1 verilator_gantt.1 verilator_profcfunc.1
 
@@ -513,6 +505,7 @@ clean mostlyclean distclean maintainer-clean::
 	rm -f *.tex
 	rm -rf examples/*/obj_dir* examples/*/logs
 	rm -rf test_*/obj_dir
+	rm -rf nodist/fuzzer/dictionary
 	rm -rf nodist/obj_dir
 
 distclean maintainer-clean::

README.adoc

@@ -4,7 +4,7 @@
 ifdef::env-github[]
 image:https://img.shields.io/badge/License-LGPL%20v3-blue.svg[license LGPLv3,link=https://www.gnu.org/licenses/lgpl-3.0]
 image:https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg[license Artistic-2.0,link=https://opensource.org/licenses/Artistic-2.0]
-image:https://api.codacy.com/project/badge/Grade/ff998fdaa6f64b9a95eb5f342ee6bf4d[Code Quality,link=https://www.codacy.com/manual/wsnyder/verilator]
+image:https://api.codacy.com/project/badge/Grade/48478c986f13400682ffe4a5e0939b3a[Code Quality,link=https://www.codacy.com/gh/verilator/verilator]
 image:https://travis-ci.com/verilator/verilator.svg?branch=master[Build Status (Travis CI),link=https://travis-ci.com/verilator/verilator]
 endif::[]
 
@@ -16,6 +16,7 @@ ifndef::env-github[]
 :link_verilator_contributing: https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.adoc
 :link_verilator_install: https://verilator.org/install
 endif::[]
+:link_verilator_commercial_support: https://verilator.org/verilator_commercial_support
 
 == Welcome to Verilator
 
@@ -24,7 +25,7 @@ endif::[]
 ^.^| *Welcome to Verilator, the fastest free Verilog HDL simulator.*
 +++ <br/> +++ &bullet; Accepts synthesizable Verilog or SystemVerilog
 +++ <br/> +++ &bullet; Performs lint code-quality checks
-+++ <br/> +++ &bullet; Compiles into multithreaded {cpp}, SystemC, or (soon) {cpp}-under-Python
++++ <br/> +++ &bullet; Compiles into multithreaded {cpp}, or SystemC
 +++ <br/> +++ &bullet; Creates XML to front-end your own tools
 <.^|image:https://www.veripool.org/img/verilator_256_200_min.png[Logo,256,200]
 
@@ -38,12 +39,18 @@ endif::[]
 +++ <br/> +++ &bullet; Out-of-the-box support from Arm, and RISC-V vendor IP
 <.^|image:https://www.veripool.org/img/verilator_usage_400x200-min.png[,400,200]
 
->.^|image:https://www.veripool.org/img/chips_alliance_logo_225x75-min.png[CHIPS Alliance,link=https://chipsalliance.org]
-image:https://www.veripool.org/img/osi_logo_125x125-min.png[,125,125]
+>.^|image:https://www.veripool.org/img/verilator_community_400x125-min.png[,400,125]
 ^.^| *Community Driven & Openly Licensed*
 +++ <br/> +++ &bullet; Guided by the https://chipsalliance.org/[CHIPS Alliance] and https://www.linuxfoundation.org/[Linux Foundation]
 +++ <br/> +++ &bullet; Open, and free as in both speech and beer
 +++ <br/> +++ &bullet; More simulation for your verification budget
+
+^.^| *Commercial Support Available*
++++ <br/> +++ &bullet; Commercial support contracts
++++ <br/> +++ &bullet; Design support contracts
++++ <br/> +++ &bullet; Enhancement contracts
+<.^|image:https://www.veripool.org/img/verilator_support_400x125-min.png[,400,125]
+
 |===
 
 == What Verilator Does
@@ -74,7 +81,7 @@ touch of {cpp} code, Verilator is the tool for you.
 Verilator does not simply convert Verilog HDL to {cpp} or SystemC.  Rather
 than only translate, Verilator compiles your code into a much faster
 optimized and optionally thread-partitioned model, which is in turn wrapped
-inside a {cpp}/SystemC/Python module.  The results are a compiled Verilog
+inside a {cpp}/SystemC/{cpp}-under-Python module.  The results are a compiled Verilog
 model that executes even on a single-thread over 10x faster than standalone
 SystemC, and on a single thread is about 100 times faster than interpreted
 Verilog simulators such as http://iverilog.icarus.com[Icarus
@@ -109,7 +116,7 @@ or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)]
 
 * https://verilator.org/issues[Verilator Issues]
 
-== Community Supported
+== Support
 
 Verilator is a community project, guided by the
 https://chipsalliance.org/[CHIPS Alliance] under the
@@ -120,6 +127,10 @@ We appreciate and welcome your contributions in whatever form; please see
 https://verilator.org/verilator_doc.html#CONTRIBUTORS[Contributors and
 Sponsors].
 
+Verilator also supports and encourages commercial support models and
+organizations; please see {link_verilator_commercial_support}[Verilator
+Commercial Support].
+
 == Related Projects
 
 * http://gtkwave.sourceforge.net/[GTKwave] - Waveform viewer for Verilator
@@ -131,10 +142,10 @@ perhaps Icarus may.
 
 == Open License
 
-Verilator is Copyright 2003-2019 by Wilson Snyder.  (Report bugs to
+Verilator is Copyright 2003-2020 by Wilson Snyder.  (Report bugs to
 https://verilator.org/issues[Verilator Issues].)
 
 Verilator is free software; you can redistribute it and/or modify it under
 the terms of either the GNU Lesser General Public License Version 3 or the
-Perl Artistic License Version 2.0.  (See the documentation for more
-details.)
+Perl Artistic License Version 2.0.  See the documentation for more
+details.

bin/verilator

@@ -1,17 +1,11 @@
-: # -*-Mode: perl;-*- use perl, wherever it is
-eval 'exec perl -wS $0 ${1+"$@"}'
-  if 0;
+#!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 
@@ -325,6 +319,7 @@ detailed descriptions in L</"VERILATION ARGUMENTS"> for more information.
     --language <lang>           Default language standard to parse
      +libext+<ext>+[ext]...     Extensions for finding modules
     --lint-only                 Lint, but do not make output
+    --max-num-width <value>     Maximum number width (default: 64K)
     --MMD                       Create .d dependency files
     --MP                        Create phony dependency targets
     --Mdir <directory>          Name of output object directory
@@ -422,6 +417,7 @@ more information.
      +verilator+prof+threads+window+I<value>   Set profile duration
      +verilator+rand+reset+I<value>    Set random reset technique
      +verilator+seed+I<value>          Set random seed
+     +verilator+noassert               Disable assert checking
      +verilator+V                      Verbose version and config
      +verilator+version                Show version and exit
 
@@ -970,6 +966,11 @@ stylistic and not enabled by default.
 If the design is not to be completely Verilated see also the --bbox-sys and
 --bbox-unsup options.
 
+=item --max-num-width I<value>
+
+Set the maximum number literal width (e.g. in 1024'd22 this it the 1024).
+Defaults to 64K.
+
 =item --MMD
 =item --no-MMD
 
@@ -1078,8 +1079,8 @@ and the remaining files can be compiled on parallel machines.  Using
 design --output-split 20000 resulted in splitting into approximately
 one-minute-compile chunks.
 
-Typically when using this, make with VM_PARALLEL_BUILD=1, and use
-I<ccache>.
+Typically when using this, make with VM_PARALLEL_BUILDS=1 (set for you if
+using the default makefiles), and use I<ccache>.
 
 =item --output-split-cfuncs I<statements>
 
@@ -1268,7 +1269,8 @@ detailed description.
 
 =item --quiet-exit
 
-When exiting due to an error, do not display the "Command Failed" message.
+When exiting due to an error, do not display the "Exiting due to Errors"
+nor "Command Failed" messages.
 
 =item --relative-includes
 
@@ -1339,6 +1341,13 @@ Creates more detailed statistics, including a list of all the variables by
 size (plain --stats just gives a count).  See --stats, which is implied by
 this.
 
+=item --structs-packed
+
+Converts all unpacked structures to packed structures and issues a UNPACKED
+warning.  Currently this is the default and --no-structs-packed will not
+work.  Specifying this option allows for forward compatibility when a
+future version of Verilator no longer always packs unpacked structures.
+
 =item -sv
 
 Specifies SystemVerilog language features should be enabled; equivalent to
@@ -1769,6 +1778,11 @@ For $random and "-x-initial unique", set the simulation runtime random seed
 value.  If zero or not specified picks a value from the system random
 number generator.
 
+=item +verilator+noassert
+
+Disable assert checking per runtime argument. This is the same as calling
+"Verilated::assertOn(false)" in the model.
+
 =item +verilator+V
 
 Shows the verbose version, including configuration information.
@@ -1896,13 +1910,13 @@ Now we run Verilator on our little example.
 
 We then can compile it
 
-    cd obj_dir
-    make -j -f Vour.mk Vour__ALL.a
-    make -j -f Vour.mk ../sc_main.o verilated.o
+    make -j -C obj_dir -f Vour.mk Vour__ALL.a
+    make -j -C obj_dir -f Vour.mk ../sc_main.o verilated.o
 
 And link with SystemC.  Note your path to the libraries may vary,
 depending on the operating system.
 
+    cd obj_dir
     export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists
     export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
     # Might be needed if SystemC 2.3.0
@@ -1926,6 +1940,39 @@ when your source changes it will automatically run all of these steps.  See
 the examples directory in the distribution.
 
 
+=head1 EVALUATION LOOP
+
+When using SystemC, when Verilator is evaluated is managed by the SystemC
+kernel, and for the most part can be ignored.  When using C++, the user
+must call eval(), or eval_step() and eval_end_step().
+
+1. When there is a single design instantiated at the C++ level that need to
+evaluate, just call designp->eval().
+
+2. When there are multiple designs instantiated each at the C++ level that
+need to evaluate, call first_designp->eval_step() then ->eval_step() on all
+other designs.  Then call ->eval_end_step() on the first design then all
+other designs.  If there is only a single design, you would call
+eval_step() then eval_end_step(); in fact eval() described above is just a
+wrapper which calls these two functions.
+
+When eval() is called Verilator looks for changes in clock signals and
+evaluates related sequential always blocks, such as computing always_ff @
+(posedge...) outputs.  Then Verilator evaluates combinatorial logic.
+
+Note combinatorial logic is not computed before sequential always blocks
+are computed (for speed reasons). Therefore it is best to set any non-clock
+inputs up with a separate eval() call before changing clocks().
+
+Alternatively, if all always_ff statements use only the posedge of clocks,
+or all inputs go directly to always_ff statements, as is typical, then you
+can change non-clock inputs on the negative edge of the input clock, which
+will be faster as there will be fewer eval() calls.
+
+For more information on evaluation, see docs/internals.adoc in the
+distribution.
+
+
 =head1 BENCHMARKING & OPTIMIZATION
 
 For best performance, run Verilator with the "-O3 --x-assign fast
@@ -1954,27 +2001,27 @@ OPT, OPT_FAST, or OPT_SLOW lib/verilated.mk.  Or, use the -CFLAGS and/or
 the compiler or linker.  Or, just for one run, pass them on the command
 line to make:
 
-    make OPT_FAST="-O2 -fno-stack-protector" -f Vour.mk Vour__ALL.a
+    make OPT_FAST="-Os -fno-stack-protector" -f Vour.mk Vour__ALL.a
 
 OPT_FAST specifies optimizations for those programs that are part of the
 fast path, mostly code that is executed every cycle.  OPT_SLOW specifies
 optimizations for slow-path files (plus tracing), which execute only
 rarely, yet take a long time to compile with optimization on.  OPT
 specifies overall optimization and affects all compiles, including those
-OPT_FAST and OPT_SLOW control.  For best results, use OPT="-O2", and link
+OPT_FAST and OPT_SLOW control.  For best results, use OPT="-Os", and link
 with "-static".  Nearly the same results can be had with much better
 compile times with OPT_FAST="-O1 -fstrict-aliasing".  Higher optimization
-such as "-O3" may help, but gcc compile times may be excessive under O3 on
-even medium sized designs.  Alternatively, some larger designs report
-better performance using "-Os".
+such as "-O2" or "-O3" may help, but gcc compile times may be excessive
+under O3 on even medium sized designs.
 
 Unfortunately, using the optimizer with SystemC files can result in
 compiles taking several minutes.  (The SystemC libraries have many little
 inlined functions that drive the compiler nuts.)
 
-For best results, use GCC 3.3 or newer.  GCC 3.2 and earlier have
-optimization bugs around pointer aliasing detection, which can result in 2x
-performance losses.
+For best results, use the latest clang compiler (about 10% faster than
+GCC).  Note the now fairly old GCC 3.2 and earlier have optimization bugs
+around pointer aliasing detection, which can result in 2x performance
+losses.
 
 If you will be running many simulations on a single compile, investigate
 feedback driven compilation.  With GCC, using -fprofile-arcs, then
@@ -1985,6 +2032,9 @@ especially if you link in DPI code.  To enable LTO on GCC, pass "-flto" in
 both compilation and link.  Note LTO may cause excessive compile times on
 large designs.
 
+Using profile driven compiler optimization, with feedback from a real
+design, can yield up to30% improvements.
+
 If you are using your own makefiles, you may want to compile the Verilated
 code with -DVL_INLINE_OPT=inline. This will inline functions, however this
 requires that all cpp files be compiled in a single compiler run.
@@ -1995,7 +2045,7 @@ either oprofile or gprof to see where in the C++ code the time is spent.
 Run the gprof output through verilator_profcfunc and it will tell you what
 Verilog line numbers on which most of the time is being spent.
 
-When done, please let the author know the results.  I like to keep tabs on
+When done, please let the author know the results.  We like to keep tabs on
 how Verilator compares, and may be able to suggest additional improvements.
 
 
@@ -2070,7 +2120,7 @@ After running Make, the C++ compiler may produce the following:
 
 A generic Linux/OS variable specifying what directories have shared object
 (.so) files.  This path should include SystemC and any other shared objects
-needed at simultion runtime.
+needed at simulation runtime.
 
 =item OBJCACHE
 
@@ -2114,16 +2164,16 @@ specified, it will come from a default optionally specified at configure
 time (before Verilator was compiled), or computed from
 SYSTEMC/lib-SYSTEMC_ARCH.
 
-=item VCS_HOME
-
-If set, specifies the directory containing the Synopsys VCS distribution.
-When set, a 'make test' in the Verilator distribution will also run VCS
-baseline regression tests.
-
 =item VERILATOR_BIN
 
-If set, specifies an alternative name of the Verilator binary.  May be used
-for debugging and selecting between multiple operating system builds.
+If set, specifies an alternative name of the C<verilator> binary.  May be
+used for debugging and selecting between multiple operating system builds.
+
+=item VERILATOR_COVERAGE_BIN
+
+If set, specifies an alternative name of the C<verilator_coverage binary>.
+May be used for debugging and selecting between multiple operating system
+builds.
 
 =item VERILATOR_GDB
 
@@ -2199,7 +2249,7 @@ example:
 Note signals are read and written as member variables of the lower module.
 You call the eval() method to evaluate the model.  When the simulation is
 complete call the final() method to wrap up any SystemVerilog final blocks,
-and complete any assertions.
+and complete any assertions. See L</"EVALUATION LOOP">.
 
 
 =head1 CONNECTING TO SYSTEMC
@@ -2674,7 +2724,7 @@ The remainder of this section describe behavior with --threads 1 or
 VL_THREADED is defined when compiling a threaded Verilated module, causing
 the Verilated support classes become threadsafe.
 
-The thread used for constructing a model must the the same thread that
+The thread used for constructing a model must be the same thread that
 calls eval() into the model, this is called the "eval thread". The thread
 used to perform certain global operations such as saving and tracing must
 be done by a "main thread". In most cases the eval thread and main thread
@@ -2737,8 +2787,8 @@ controlled by configuration files, typically named with the .vlt
 extension. An example:
 
   `verilator_config
-  lint_off -msg WIDTH
-  lint_off -msg CASEX  -file "silly_vendor_code.v"
+  lint_off -rule WIDTH
+  lint_off -rule CASEX  -file "silly_vendor_code.v"
 
 This disables WIDTH warnings globally, and CASEX for a specific file.
 
@@ -2756,8 +2806,7 @@ The grammar of configuration commands is as follows:
 
 =item `verilator_config
 
-Take remaining text up the the next `verilog mode switch and treat it as
-Verilator configuration commands.
+Take remaining text and treat it as Verilator configuration commands.
 
 =item coverage_on  [-file "<filename>" [-lines <line> [ - <line> ]]]
 
@@ -2768,9 +2817,11 @@ Enable/disable coverage for the specified filename (or wildcard with '*' or
 omitted).  Often used to ignore an entire module for coverage analysis
 purposes.
 
-=item lint_on  [-msg <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
+=item lint_on  [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
 
-=item lint_off [-msg <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
+=item lint_off [-rule <message>] [-file "<filename>" [-lines <line> [ - <line>]]]
+
+=item lint_off [-rule <message>] [-file "<filename>"] [-match "<string>"]
 
 Enable/disables the specified lint warning, in the specified filename (or
 wildcard with '*' or '?', or all files if omitted) and range of line
@@ -2779,10 +2830,17 @@ numbers (or all lines if omitted).
 With lint_off using '*' will override any lint_on directives in the source,
 i.e. the warning will still not be printed.
 
-If the -msg is omitted, all lint warnings (see list in -Wno-lint) are
+If the -rule is omitted, all lint warnings (see list in -Wno-lint) are
 enabled/disabled.  This will override all later lint warning enables for
 the specified region.
 
+If -match is set the linter warnings are matched against this (wildcard)
+string and are waived in case they match iff rule and file (with wildcard)
+also match.
+
+In previous versions -rule was named -msg. The latter is deprecated, but
+still works with a deprecation info, it may be removed in future versions.
+
 =item tracing_on  [-file "<filename>" [-lines <line> [ - <line> ]]]
 
 =item tracing_off [-file "<filename>" [-lines <line> [ - <line> ]]]
@@ -2794,6 +2852,135 @@ and range of line numbers (or all lines if omitted).
 For tracing_off, cells below any module in the files/ranges specified will
 also not be traced.
 
+=item clock_enable -module "<modulename>" -var "<signame>"
+
+Indicate the signal is used to gate a clock, and the user takes responsibility
+for insuring there are no races related to it.
+
+Same as /*verilator clock_enable*/, see L</"LANGUAGE EXTENSIONS"> for
+more information and an example.
+
+=item clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+=item clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+=item no_clocker -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+=item no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+Indicate the signal is used as clock or not. This information is used by
+Verilator to mark the signal as clocker and propagate the clocker attribute
+automatically to derived signals. See C<--clk> for more information.
+
+Same as /*verilator clocker*/, see L</"LANGUAGE EXTENSIONS"> for more
+information.
+
+=item coverage_block_off -module "<modulename>" -block "<blockname>"
+
+=item coverage_block_off -file "<filename>" -line <lineno>
+
+Specifies the entire begin/end block should be ignored for coverage
+analysis purposes.  Can either be specified as a named block or as a
+filename and line number.
+
+Same as /*verilator coverage_block_off*/, see L</"LANGUAGE
+EXTENSIONS"> for more information.
+
+=item full_case -file "<filename>" -lines <lineno>
+
+=item parallel_case -file "<filename>" -lines <lineno>
+
+Same as "//synopsys full_case" and "//synopsys parallel_case". When
+these synthesis directives are discovered, Verilator will either
+formally prove the directive to be true, or failing that, will insert
+the appropriate code to detect failing cases at simulation runtime and
+print an "Assertion failed" error message.
+
+=item inline -module "<modulename>"
+
+Specifies the module may be inlined into any modules that use this
+module.  This is useful to speed up simulation runtime with some small
+loss of trace visibility and modularity.  Note signals under inlined
+submodules will be named I<submodule>__DOT__I<subsignal> as C++ does
+not allow "." in signal names.  When tracing such signals the tracing
+routines will replace the __DOT__ with the period.
+
+Same as /*verilator inline_module*/, see L</"LANGUAGE EXTENSIONS"> for
+more information.
+
+=item isolate_assignments -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+=item isolate_assignments -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+=item isolate_assignments -module "<modulename>" -function "<fname>"
+
+Used to indicate the assignments to this signal in any blocks should be
+isolated into new blocks.  When there is a large combinatorial block that
+is resulting in a UNOPTFLAT warning, attaching this to the signal causing
+a false loop may clear up the problem.
+
+Same as /* verilator isolate_assignments */, see L</"LANGUAGE
+EXTENSIONS"> for more information.
+
+=item no_inline -module "<modulename>"
+
+Specifies the module should not be inlined into any modules that use
+this module.  This is useful especially at the top level module to
+reduce the size of the interface class, to aid compile time at a small
+performance loss.
+
+Same as /*verilator no_inline_module*/, see L</"LANGUAGE EXTENSIONS">
+for more information.
+
+=item no_inline [-module "<modulename>"] -task "<taskname>"
+
+=item no_inline [-module "<modulename>"] -function "<funcname>"
+
+Specify the function or task should not be inlined into where it is
+used.  This may reduce the size of the final executable when a task is
+used a very large number of times.  For this flag to work, the task
+and tasks below it must be pure; they cannot reference any variables
+outside the task itself.
+
+Same as /*verilator no_inline_task*/, see L</"LANGUAGE EXTENSIONS">
+for more information.
+
+=item sc_bv -module "<modulename>" [-task "<taskname>"] -var "<signame>"
+
+=item sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>"
+
+Sets the port to be of sc_bv<I<width>> type, instead of bool, vluint32_t or
+vluint64_t.  This may be useful if the port width is parameterized and
+different of such modules interface a templated module (such as a transactor)
+or for other reasons.  In general you should avoid using this attribute when
+not necessary as with increasing usage of sc_bv the performance decreases
+significantly.
+
+Same as /*verilator sc_bv*/, see L</"LANGUAGE EXTENSIONS"> for more
+information.
+
+=item sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"
+
+=item sformat [-module "<modulename>"] [-function "<funcname>"] -var "<signame>"
+
+Final input of a function or task "input string" to indicate the
+function or task should pass all remaining arguments through
+$sformatf.  This allows creation of DPI functions with $display like
+behavior.  See the test_regress/t/t_dpi_display.v file for an example.
+
+Same as /*verilator sformat*/, see L</"LANGUAGE EXTENSIONS"> for more
+information.
+
+=item split_var [-module "<modulename>"] [-task "<taskname>"] -var "<varname>"
+
+=item split_var [-module "<modulename>"] [-function "<funcname>"] -var "<varname>"
+
+Break the variable into multiple pieces typically to resolve UNOPTFLAT
+performance issues. Typically the variables to attach this to are
+recommeded by Verilator itself, see UNOPTFLAT.
+
+Same as /*verilator split_var*/, see L</"LANGUAGE EXTENSIONS"> for more
+information.
 
 =back
 
@@ -2929,7 +3116,8 @@ per the C standard (it's unspecified in Verilog).
 
 Specifies the entire begin/end block should be ignored for coverage
 analysis.  Must be inside a basic block, e.g. within a begin/end pair.
-Same as /* verilator coverage_block_off */.
+Same as /* verilator coverage_block_off */ and C<coverage_block_off> in
+L</"CONFIGURATION FILES">.
 
 =item `systemc_header
 
@@ -2995,7 +3183,7 @@ may `ifdef around compiler specific constructs.
 
 =item `verilator_config
 
-Take remaining text up the the next `verilog mode switch and treat it as
+Take remaining text up to the next `verilog mode switch and treat it as
 Verilator configuration commands.
 
 =item `verilog
@@ -3019,7 +3207,10 @@ analysis.) For example:
 The clock_enable attribute will cause the clock gate to be ignored in the
 scheduling algorithm, sometimes required for correct clock behavior, and
 always improving performance.  It's also a good idea to enable the
-IMPERFECTSCH warning, to insure all clock enables are properly recognized.
+IMPERFECTSCH warning, to ensure all clock enables are properly recognized.
+
+Same as C<clock_enable> in configuration files, see L</"CONFIGURATION
+FILES"> for more information.
 
 =item /*verilator clocker*/
 
@@ -3030,11 +3221,17 @@ not. This information is used by Verilator to mark the signal as clocker
 and propagate the clocker attribute automatically to derived signals. See
 C<--clk> for more information.
 
+Same as C<clocker> and C<no_clocker> in configuration files, see
+L</"CONFIGURATION FILES"> for more information.
+
 =item /*verilator coverage_block_off*/
 
 Specifies the entire begin/end block should be ignored for coverage
 analysis purposes.
 
+Same as C<coverage_block_off> in configuration files, see
+L</"CONFIGURATION FILES"> for more information.
+
 =item /*verilator coverage_off*/
 
 Specifies that following lines of code should have coverage disabled.
@@ -3055,6 +3252,9 @@ submodules will be named I<submodule>__DOT__I<subsignal> as C++ does not
 allow "." in signal names.  When tracing such signals the tracing routines
 will replace the __DOT__ with the period.
 
+Same as C<inline> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
+
 =item /*verilator isolate_assignments*/
 
 Used after a signal declaration to indicate the assignments to this signal
@@ -3091,6 +3291,9 @@ It would then internally break it into (sort of):
       end
     end
 
+Same as C<isolate_assignments> in configuration files, see
+L</"CONFIGURATION FILES"> for more information.
+
 =item /*verilator lint_off I<msg>*/
 
 Disable the specified warning message for any warnings following the comment.
@@ -3126,6 +3329,9 @@ modules that use this module.  This is useful especially at the top level
 module to reduce the size of the interface class, to aid compile time at a
 small performance loss.
 
+Same as C<no_inline> in configuration files, see L</"CONFIGURATION
+FILES"> for more information.
+
 =item /*verilator no_inline_task*/
 
 Used in a function or task variable definition section to specify the
@@ -3134,6 +3340,9 @@ reduce the size of the final executable when a task is used a very large
 number of times.  For this flag to work, the task and tasks below it must
 be pure; they cannot reference any variables outside the task itself.
 
+Same as C<no_inline> in configuration files, see L</"CONFIGURATION
+FILES"> for more information.
+
 =item /*verilator public*/ (parameter)
 
 Used after a parameter declaration to indicate the emitted C code should
@@ -3161,6 +3370,9 @@ Instead of using public variables, consider instead making a DPI or public
 function that accesses the variable.  This is nicer as it provides an
 obvious entry point that is also compatible across simulators.
 
+Same as C<public> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
+
 =item /*verilator public*/ (task/function)
 
 Used inside the declaration section of a function or task declaration to
@@ -3183,6 +3395,9 @@ the model will NOT notice changes made to variables in these functions.
 You may want to use DPI exports instead, as it's compatible with other
 simulators.
 
+Same as C<public> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
+
 =item /*verilator public_flat*/ (variable)
 
 Used after an input, output, register, or wire declaration to indicate the
@@ -3191,11 +3406,17 @@ signal.  This will not declare this module public, which means the name of
 the signal or path to it may change based upon the module inlining which
 takes place.
 
+Same as C<public_flat> in configuration files, see L</"CONFIGURATION
+FILES"> for more information.
+
 =item /*verilator public_flat_rd*/ (variable)
 
 Used after an input, output, register, or wire declaration to indicate the
 signal should be declared public_flat (see above), but read-only.
 
+Same as C<public_flat_rd> in configuration files, see L</"CONFIGURATION
+FILES"> for more information.
+
 =item /*verilator public_flat_rw @(<edge_list>) */ (variable)
 
 Used after an input, output, register, or wire declaration to indicate the
@@ -3204,6 +3425,9 @@ where writes should be considered to have the timing specified by the given
 sensitivity edge list.  Set for all variables, ports and wires using the
 --public-flat-rw switch.
 
+Same as C<public_flat_rw> in configuration files, see L</"CONFIGURATION
+FILES"> for more information.
+
 =item /*verilator public_module*/
 
 Used after a module statement to indicate the module should not be inlined
@@ -3212,9 +3436,12 @@ Verilator automatically sets this attribute when the module contains any
 public signals or `systemc_ directives.  Also set for all modules when
 using the --public switch.
 
+Same as C<public> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
+
 =item /*verilator sc_clock*/
 
-Rarely needed.  Used after an input declaration to indicate the signal
+Deprecated.  Used after an input declaration to indicate the signal
 should be declared in SystemC as a sc_clock instead of a bool.  This was
 needed in SystemC 1.1 and 1.2 only; versions 2.0 and later do not require
 clock pins to be sc_clocks and this is no longer needed.
@@ -3226,7 +3453,10 @@ type, instead of bool, vluint32_t or vluint64_t.  This may be useful if
 the port width is parameterized and different of such modules interface
 a templated module (such as a transactor) or for other reasons.  In general
 you should avoid using this attribute when not necessary as with increasing
-usage of sc_bv the performance increases significantly.
+usage of sc_bv the performance decreases significantly.
+
+Same as C<sc_bv> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
 
 =item /*verilator sformat*/
 
@@ -3235,6 +3465,39 @@ indicate the function or task should pass all remaining arguments through
 $sformatf.  This allows creation of DPI functions with $display like
 behavior.  See the test_regress/t/t_dpi_display.v file for an example.
 
+Same as C<sformat> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
+
+=item /*verilator split_var*/
+
+Attached to a variable or a net declaration to break the variable into
+multiple pieces typically to resolve UNOPTFLAT performance issues.
+Typically the variables to attach this to are recommeded by Verilator
+itself, see UNOPTFLAT below.
+
+For example, Verilator will internally convert a variable with the
+metacomment such as:
+
+    logic [7:0] x [0:1]  /*verilator split_var*/;
+
+To:
+
+    logic [7:0] x__BRA__0__KET__ /*verilator split_var*/;
+    logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
+
+Note that the generated packed variables retain the split_var metacomment
+because they may be split into further smaller pieces accorting to the
+access patterns.
+
+This only supports unpacked arrays, packed arrays, and packed structs of
+integer types (reg, logic, bit, byte, int...); otherwise if a split was
+requested but cannot occur a SPLITVAR warning is issued.  Splitting large
+arrays may slow donw the Verilation speed, so use this only on variables
+that require it.
+
+Same as C<split_var> in configuration files, see L</"CONFIGURATION FILES">
+for more information.
+
 =item /*verilator tag <text...>*/
 
 Attached after a variable or structure member to indicate opaque (to
@@ -3317,7 +3580,7 @@ that Verilator will print a list of known scopes to help your debugging.
 
 =head2 Floating Point
 
-Floating Point (real) numbers are supported.
+Short floating point (shortreal) numbers are converted to real.
 
 =head2 Latches
 
@@ -3507,6 +3770,11 @@ Assignment patterns with order based, default, constant integer (array) or
 member identifier (struct/union) keys are supported.  Data type keys and
 keys which are computed from a constant expression are not supported.
 
+=item `uselib
+
+Uselib, a vendor specific library specification method, is ignored along
+with anything following it until the end of that line.
+
 =item cast operator
 
 Casting is supported only between simple scalar types, signed and unsigned,
@@ -3565,17 +3833,29 @@ $unsigned, $warning.
 
 Generally supported.
 
-=item $display, $write, $fdisplay, $fwrite, $swrite
-
-$display and friends must have a constant format string as the first
-argument (as with C's printf).  The rare usage which lists variables
-standalone without a format is not supported.
-
 =item $displayb, $displayh, $displayo, $writeb, $writeh, $writeo, etc
 
 The sized display functions are rarely used and so not supported.  Replace
 them with a $write with the appropriate format specifier.
 
+=item $dump/$dumpports and related
+
+$dumpfile or $dumpports will create a VCD or FST file (which is based on
+the --trace argument given when the model was Verilated). This will take
+effect starting at the next eval() call.  If you have multiple Verilated
+designs under the same C model, then this will dump signals only from the
+design containing the $dumpvar.
+
+$dumpvars and $dumpports module identifier is ignored; the traced instances
+will always start at the top of the design. The levels argument is also
+ignored, use tracing_on/tracing_off pragmas instead.
+
+$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename argument
+is ignored, only a single trace file may be active at once.
+
+$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
+$dumplimit/$dumpportlimit are currently ignored.
+
 =item $finish, $stop
 
 The rarely used optional parameter to $finish and $stop is ignored.
@@ -3645,7 +3925,24 @@ checking across the designs, and prevents other users from compiling your
 code without knowing the magic set of disables needed to successfully
 compile your design.
 
-List of all warnings:
+=head2 Error and Warning Format
+
+Warnings and errors printed by Verilator always match this regular
+expression:
+
+        %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.*
+
+Errors and warning start with a percent sign (historical heritage from
+Digital Equipment Corporation).  Some errors or warning have a code
+attached, with meanings described below.  Some errors also have a filename,
+line number and optional column number (starting at column 1 to match GCC).
+
+Following an the error message, Verilator will typically show the user's
+source code corresponding to the error, prefixed by the line number and a "
+| ".  Following this is typically an arrow and ~ pointing at the error on
+the source line directly above.
+
+=head2 List of all warnings
 
 =over 4
 
@@ -3743,6 +4040,14 @@ generally unrolls small loops.  You may want to try increasing
 --unroll-count (and occasionally --unroll-stmts) which will raise the small
 loop bar to avoid this error.
 
+=item BOUNDED
+
+This indicates that bounded queues (e.g. "var name[$ : 3]") are
+unsupported.
+
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item BSSPACE
 
 Warns that a backslash is followed by a space then a newline. Likely the
@@ -4185,6 +4490,29 @@ Ignoring this warning may make Verilator simulations differ from other
 simulators, if the increased precision of real affects your model or DPI
 calls.
 
+=item SPLITVAR
+
+Warns that a variable with a C<split_var> metacomment was not split.
+Some possible reasons for this are:
+
+* The datatype of the variable is not supported for splitting. (e.g. is a
+real).
+
+* The access pattern of the variable can not be determined
+statically. (e.g. is accessed as a memory).
+
+* The index of the array exceeds the array size.
+
+* The variable is accessed from outside using dotted reference.
+(e.g. top.instance0.variable0 = 1).
+
+* The variable is not declared in a module, but in a package or an
+interface.
+
+* The variable is a parameter, localparam, genvar, or queue.
+
+* The variable is tirstate or bidirectional. (e.g. inout or ref).
+
 =item STMTDLY
 
 Warns that you have a statement with a delayed time in front of it, for
@@ -4316,6 +4644,11 @@ being generated from an always statement that consumed high bits of the
 same bus processed by another series of always blocks.  The fix is the
 same; split it into two separate signals generated from each block.
 
+Another way to resolve this warning is to add a C<split_var> metacomment
+described above. This will cause the variable to be split internally,
+potentially resolving the conflict. If you run with --report-unoptflat
+Verilator will suggest possible candidates for C<split_var>.
+
 The UNOPTFLAT warning may also be due to clock enables, identified from the
 reported path going through a clock gating cell.  To fix these, use the
 clock_enable meta comment described above.
@@ -4463,6 +4796,37 @@ that is not yet supported in Verilator.  See the Limitations chapter.
 =back
 
 
+=head1 DEPRECATIONS
+
+The following deprecated items are scheduled for future removal:
+
+=over 4
+
+=item Pre-C++11 compiler support
+
+Verilator supports pre-C++11 compilers for non-threaded models when
+configured with --enable-prec11.  This flag will be removed and C++11
+compilers will be required for both compiling Verilator and compiling
+Verilated models no sooner than September 2020.
+
+=item SystemC 2.1 and earlier support
+
+Support for SystemC versions 2.1 and earlier and the related sc_clock
+variable attribute will be removed no sooner than July 2020.
+
+=item Configuration File -msg
+
+The -msg argument to lint_off has been replaced with -rule.  -msg is
+planned for removal no sooner than January 2021.
+
+=item XML locations
+
+The XML C<fl> attribute has been replaced with C<loc>.  C<fl> is planned
+for removal no sooner than January 2021.
+
+=back
+
+
 =head1 FAQ/FREQUENTLY ASKED QUESTIONS
 
 =over 4
@@ -4551,19 +4915,20 @@ designs have topped 16GB.
 
 See the next question for tracing in SystemC mode.
 
-Add the --trace switch to Verilator, and in your top level C code, call
-Verilated::traceEverOn(true).  Then create a VerilatedVcdC object, and
-in your main loop call "trace_object->dump(time)" every time step, and
-finally call "trace_object->close()".  For an example, see below and the
-examples/make_tracing_c/sim_main.cpp file of the distribution.
+A. Add the --trace switch to Verilator, and in your top level C code, call
+Verilated::traceEverOn(true).  Then you may use $dumpfile and $dumpvars to
+enable traces, same as with any Verilog simulator. See
+C<examples/make_tracing_c>.
 
-You also need to compile verilated_vcd_c.cpp and add it to your link,
-preferably by adding the dependencies in $(VK_GLOBAL_OBJS) to your
-Makefile's link rule.  This is done for you if using the Verilator --exe
-flag.
-
-Note you can also call ->trace on multiple Verilated objects with the same
-trace file if you want all data to land in the same output file.
+B. Or, for finer-grained control, or C++ files with multiple Verilated
+modules you may also create the trace purely from C++.  Create a
+VerilatedVcdC object, and in your main loop call "trace_object->dump(time)"
+every time step, and finally call "trace_object->close()".  You also need
+to compile verilated_vcd_c.cpp and add it to your link, preferably by
+adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule.
+This is done for you if using the Verilator --exe flag.  Note you can also
+call ->trace on multiple Verilated objects with the same trace file if you
+want all data to land in the same output file.
 
     #include "verilated_vcd_c.h"
     ...
@@ -4583,11 +4948,17 @@ trace file if you want all data to land in the same output file.
 
 =item How do I generate waveforms (traces) in SystemC?
 
-Add the --trace switch to Verilator, and in your top level C sc_main code,
-include verilated_vcd_sc.h.  Then call Verilated::traceEverOn(true).  Then
-create a VerilatedVcdSc object as you would create a normal SystemC trace
-file.  For an example, see the call to VerilatedVcdSc in the
-examples/make_tracing_sc/sc_main.cpp file of the distribution, and below.
+A. Add the --trace switch to Verilator, and in your top level sc_main, call
+Verilated::traceEverOn(true).  Then you may use $dumpfile and $dumpvars to
+enable traces, same as with any Verilog simulator, see the non-SystemC
+example in C<examples/make_tracing_c>. This will trace only the module
+containing the $dumpvar.
+
+B. Or, you may create a trace purely from SystemC, which may trace all
+Verilated designs in the SystemC model. Create a VerilatedVcdSc object as
+you would create a normal SystemC trace file.  For an example, see the call
+to VerilatedVcdSc in the examples/make_tracing_sc/sc_main.cpp file of the
+distribution, and below.
 
 Alternatively you may use the C++ trace mechanism described in the previous
 question, however the timescale and timeprecision will not inherited from
@@ -4617,23 +4988,23 @@ trace file if you want all data to land in the same output file.
 
 =item How do I generate FST waveforms (traces) in C++?
 
-FST a format by GTKWave.
-This version provides a basic FST support.
-To dump FST format, add the --trace-fst switch to Verilator and change the include
-path in the testbench to:
+FST a format by GTKWave.  This version provides a basic FST support.  To
+dump FST format, add the --trace-fst switch to Verilator and either A. use
+$dumpfile/$dumpvars in Verilog as described in the VCD example above, or
+B. in C++ change the include described in the VCD example above:
 
     #include "verilated_fst_c.h"
     VerilatedFstC* tfp = new VerilatedFstC;
 
-Note that currently supporting both FST and VCD in a single simulation is impossible,
-but such requirement could be rare.
+Note that currently supporting both FST and VCD in a single simulation is
+impossible, but such requirement should be rare.
 
-=item How do I generate FST waveforms (traces) in SystemC?
+=item How do I generate FST waveforms (aka dumps or traces) in SystemC?
 
 The FST library from GTKWave does not currently support SystemC; use VCD
 format instead.
 
-=item How do I view waveforms (traces)?
+=item How do I view waveforms (aka dumps or traces)?
 
 Verilator makes standard VCD (Value Change Dump) and FST files.  VCD files are viewable
 with the public domain GTKWave (recommended) or Dinotrace (legacy)
@@ -4694,7 +5065,7 @@ Most synthesis tools similarly define SYNTHESIS for you.
 =item Why do I get "unexpected `do'" or "unexpected `bit'" errors?
 
 Do, bit, ref, return, and other words are now SystemVerilog keywords.  You
-should change your code to not use them to insure it works with newer
+should change your code to not use them to ensure it works with newer
 tools.  Alternatively, surround them by the Verilog 2005/SystemVerilog
 begin_keywords pragma to indicate Verilog 2001 code.
 
@@ -4844,7 +5215,7 @@ SystemC module *may* be faster.)
 
 =head1 BUGS
 
-First, check the the coding limitations section.
+First, check the coding limitations section.
 
 Next, try the --debug switch.  This will enable additional internal
 assertions, and may help identify the problem.
@@ -5016,11 +5387,15 @@ remain anonymous.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2019 by Wilson Snyder.  Verilator is free software; you can
+Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.
 
+All Verilog and C++/SystemC code quoted within this documentation file are
+released as Creative Commons Public Domain (CC0).  Many example files and
+test files are likewise released under CC0 into effectively the Public
+Domain as described in the files themselves.
 
 =head1 SEE ALSO
 
@@ -5028,7 +5403,7 @@ L<verilator_coverage>, L<verilator_gantt>, L<verilator_profcfunc>, L<make>,
 
 L<verilator --help> which is the source for this document,
 
-and internals.txt in the distribution.
+and docs/internals.adoc in the distribution.
 
 =cut
 

bin/verilator_coverage

@@ -1,18 +1,11 @@
-: # -*-Mode: perl;-*- use perl, wherever it is
-eval 'exec perl -wS $0 ${1+"$@"}'
-  if 0;
+#!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 #
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
 ######################################################################
 
 require 5.006_001;
@@ -271,10 +264,12 @@ Specifies a module search directory.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2003-2019 by Wilson Snyder.  Verilator is free software; you can
-redistribute it and/or modify the Verilator internals under the terms of
-either the GNU Lesser General Public License Version 3 or the Perl Artistic
-License Version 2.0.
+Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify the Verilator internals under the terms
+of either the GNU Lesser General Public License Version 3 or the Perl
+Artistic License Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 =head1 AUTHORS
 

bin/verilator_difftree

@@ -1,10 +1,7 @@
-: # -*-Mode: perl;-*- use perl, wherever it is
-eval 'exec perl -wS $0 ${1+"$@"}'
-  if 0;
+#!/usr/bin/env perl
 # See copyright, etc in below POD section.
 ######################################################################
 
-require 5.006_001;
 use warnings;
 use Getopt::Long;
 use IO::File;
@@ -236,9 +233,12 @@ Do not show differences in line numbering.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2005-2019 by Wilson Snyder.  This package is free software; you can
-redistribute it and/or modify it under the terms of either the GNU Lesser
-General Public License Version 3 or the Perl Artistic License Version 2.0.
+Copyright 2005-2020 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 =head1 AUTHORS
 

bin/verilator_gantt

@@ -1,11 +1,9 @@
-: # -*-Mode: perl;-*- use perl, wherever it is
-eval 'exec perl -wS $0 ${1+"$@"}'
-  if 0;
+#!/usr/bin/env perl
 # See copyright, etc in below POD section.
 ######################################################################
 
-use strict;
 use warnings;
+use strict;
 use Getopt::Long;
 use IO::File;
 use Pod::Usage;
@@ -125,13 +123,13 @@ sub report {
     }
 
     my $nthreads = scalar keys %Threads;
-    $Global{cpus}{cpu_time} = {};
+    $Global{cpus} = {};
     foreach my $thread (keys %Threads) {
         # Make potentially multiple characters per column
         foreach my $start (keys %{$Threads{$thread}}) {
             my $cpu = $Threads{$thread}{$start}{cpu};
             my $elapsed = $Threads{$thread}{$start}{end} - $start;
-            $Global{cpus}{cpu_time}{$cpu} += $elapsed;
+            $Global{cpus}{$cpu}{cpu_time} += $elapsed;
         }
     }
 
@@ -540,9 +538,12 @@ verilator_gantt.vcd.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2018-2019 by Wilson Snyder.  Verilator is free software; you can
-redistribute it and/or modify it under the terms of either the GNU Lesser
-General Public License Version 3 or the Perl Artistic License Version 2.0.
+Copyright 2018-2020 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 =head1 AUTHORS
 

bin/verilator_includer

@@ -1,11 +1,11 @@
-: # -*-Mode: perl;-*- use perl, wherever it is
-eval 'exec perl -wS $0 ${1+"$@"}'
-  if 0;
+#!/usr/bin/env perl
 # DESCRIPTION: Print include statements for each ARGV
 #
-# Copyright 2003-2019 by Wilson Snyder. This package is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU Lesser
-# General Public License Version 3 or the Perl Artistic License Version 2.0.
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ######################################################################
 
 require 5.005;

bin/verilator_profcfunc

@@ -1,6 +1,4 @@
-: # -*-Mode: perl;-*- use perl, wherever it is
-eval 'exec perl -wS $0 ${1+"$@"}'
-  if 0;
+#!/usr/bin/env perl
 # See copyright, etc in below POD section.
 ######################################################################
 
@@ -230,9 +228,12 @@ Displays this message and program version and exits.
 
 The latest version is available from L<https://verilator.org>.
 
-Copyright 2007-2019 by Wilson Snyder.  Verilator is free software; you can
-redistribute it and/or modify it under the terms of either the GNU Lesser
-General Public License Version 3 or the Perl Artistic License Version 2.0.
+Copyright 2007-2020 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 =head1 AUTHORS
 

ci/build_vcddiff.sh

@@ -0,0 +1,19 @@
+#!/bin/bash
+# DESCRIPTION: Verilator: Build script for vcddiff
+#
+# Copyright 2019 by Todd Strader. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+set -e
+
+# NB: it would be better to add this via a PPA
+
+TMP_DIR=$(mktemp -d)
+
+git -C "${TMP_DIR}" clone https://github.com/veripool/vcddiff
+VCDDIFF_DIR=${TMP_DIR}/vcddiff
+git -C "${VCDDIFF_DIR}" checkout 5112f88b7ba8818dce9dfb72619e64a1fc19542c
+make -C "${VCDDIFF_DIR}"
+sudo cp "${VCDDIFF_DIR}/vcddiff" /usr/local/bin

ci/build_verilator.sh

@@ -1,10 +1,11 @@
 #!/bin/bash
 # DESCRIPTION: Verilator: Travis CI build script
 #
-# Copyright 2019 by Todd Strader. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2019 by Todd Strader. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 # This script builds and caches the Verilator binaries for Travis CI
 # (and possibly other CI platforms).  The Verilator CI system uses this

ci/docker/buildenv/Dockerfile

@@ -0,0 +1,58 @@
+# DESCRIPTION: Dockerfile for env to build and fully test Verilator
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+FROM ubuntu:18.04
+
+RUN apt-get update \
+    && DEBIAN_FRONTEND=noninteractive \
+       apt-get install --no-install-recommends -y \
+                        autoconf=2.69-11 \
+                        bc=1.07.1-2 \
+                        bison=2:3.0.4.dfsg-1build1 \
+                        build-essential=12.4ubuntu1 \
+                        ca-certificates=20180409 \
+                        cmake=3.10.2-1ubuntu2.18.04.1 \
+                        flex=2.6.4-6 \
+                        gdb=8.1-0ubuntu3.2 \
+                        gcc-6=6.5.0-2ubuntu1~18.04 \
+                        gcc-5=5.5.0-12ubuntu1 \
+                        gcc-4.8=4.8.5-4ubuntu8 \
+                        git=1:2.17.1-1ubuntu0.5 \
+                        gtkwave=3.3.86-1 \
+                        g++-6=6.5.0-2ubuntu1~18.04 \
+                        g++-5=5.5.0-12ubuntu1 \
+                        g++-4.8=4.8.5-4ubuntu8 \
+                        libfl2=2.6.4-6 \
+                        libfl-dev=2.6.4-6 \
+                        numactl=2.0.11-2.1ubuntu0.1 \
+                        perl=5.26.1-6ubuntu0.3 \
+                        python3=3.6.7-1~18.04 \
+                        wget=1.19.4-1ubuntu2.2 \
+                        zlibc=0.9k-4.3 \
+                        zlib1g=1:1.2.11.dfsg-0ubuntu2 \
+                        zlib1g-dev=1:1.2.11.dfsg-0ubuntu2 \
+    && apt-get clean \
+    && rm -rf /var/lib/apt/lists/*
+
+WORKDIR /tmp
+
+COPY build-systemc.sh /tmp/
+RUN ./build-systemc.sh
+
+RUN cpan install -fi Unix::Processors Parallel::Forker Bit::Vector
+
+RUN git clone https://github.com/veripool/vcddiff.git && \
+    make -C vcddiff && \
+    cp -p vcddiff/vcddiff /usr/local/bin/vcddiff && \
+    rm -rf vcddiff
+
+COPY build.sh /tmp/build.sh
+
+ENV VERILATOR_AUTHOR_SITE=1
+
+ENTRYPOINT [ "/tmp/build.sh" ]

ci/docker/buildenv/README.adoc

@@ -0,0 +1,49 @@
+= Verilator Docker Build Environment
+
+This Verilator Build container is set up to compile and test a Verilator
+build. It uses the following parameters:
+
+* Source repository (default: https://github.com/verilator/verilator)
+* Source revision (default: master)
+* GCC version (4.8.5, 5.5.0, 6.5.0, 7.4.0, default: 7.4.0)
+
+The container is published as `verilator/verilator-buildenv` on
+https://hub.docker.com/repository/docker/verilator/verilator-buildenv[docker hub].
+
+To run the basic build using the current Verilator master:
+
+    docker run -ti verilator/verilator-buildenv
+
+To also run tests:
+
+    docker run -ti verilator/verilator-buildenv test
+
+To change the compiler:
+
+    docker run -ti -e CC=gcc-4.8 -e CXX=g++-4.8 verilator/verilator-buildenv test
+
+The tests that involve gdb are not working due to security restrictions.
+To run those too:
+
+....
+docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` -e CC=gcc-4.8 -e CXX=g++-4.8 --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
+....
+
+Rather then building using a remote git repository you may prefer to use a
+working copy on the local filesystem. Mount the local working copy path as
+a volume and use that in place of git. When doing this be careful to have
+all changes committed to the local git area. To build the current HEAD from
+top of a repository:
+
+....
+docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test
+....
+
+== Rebuilding
+
+To rebuild the Verilator-buildenv docker image, run:
+
+    docker build .
+
+This will also build SystemC under all supported compiler variants to
+reduce the SystemC testing time.

ci/docker/buildenv/build-systemc.sh

@@ -0,0 +1,30 @@
+#!/bin/bash -e
+# DESCRIPTION: Build SystemC in Ubuntu 18.04 with  different g++/gcc
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+build_variant () {
+    version=$($1 --version | grep gcc | awk '{print $4}')
+    mkdir "/usr/local/systemc-2.3.3-gcc$version"
+    mkdir build
+    cd build
+    ../configure --prefix="/usr/local/systemc-2.3.3-gcc$version" CC="$1" CXX="$2" LD="$2"
+    make -j
+    make install
+    cd ..
+    rm -r build
+}
+
+wget https://www.accellera.org/images/downloads/standards/systemc/systemc-2.3.3.tar.gz
+tar -xzf systemc-2.3.3.tar.gz
+cd systemc-2.3.3
+build_variant gcc g++
+build_variant gcc-6 g++-6
+build_variant gcc-5 g++-5
+build_variant gcc-4.8 g++-4.8
+cd ..
+rm -r systemc-2.3.3*

ci/docker/buildenv/build.sh

@@ -0,0 +1,31 @@
+#!/bin/bash -e
+# DESCRIPTION: Build Verilator (inside container)
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+: "${REPO:=https://github.com/verilator/verilator}"
+: "${REV:=master}"
+: "${CC:=gcc}"
+: "${CXX:=g++}"
+
+GCCVERSION=$(${CC} --version | grep gcc | awk '{print $4}')
+
+export SYSTEMC_INCLUDE="/usr/local/systemc-2.3.3-gcc${GCCVERSION}/include"
+export SYSTEMC_LIBDIR="/usr/local/systemc-2.3.3-gcc${GCCVERSION}/lib-linux64"
+export LD_LIBRARY_PATH=${SYSTEMC_LIBDIR}
+
+SRCS=$PWD/verilator
+
+git clone "$REPO" "$SRCS"
+cd "$SRCS"
+git checkout "$REV"
+autoconf
+./configure --enable-longtests
+make -j $(nproc)
+if [ "${1:-''}" == "test" ]; then
+    make test
+fi

ci/docker/run/Dockerfile

@@ -0,0 +1,48 @@
+# DESCRIPTION: Dockerfile for image to run Verilator inside
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+FROM ubuntu:18.04
+
+RUN apt-get update \
+    && apt-get install --no-install-recommends -y \
+                        autoconf=2.69-11 \
+                        bc=1.07.1-2 \
+                        bison=2:3.0.4.dfsg-1build1 \
+                        build-essential=12.4ubuntu1 \
+                        ca-certificates=20180409 \
+                        flex=2.6.4-6 \
+                        git=1:2.17.1-1ubuntu0.5 \
+                        libfl-dev=2.6.4-6 \
+                        perl=5.26.1-6ubuntu0.3 \
+                        python3=3.6.7-1~18.04 \
+    && apt-get clean \
+    && rm -rf /var/lib/apt/lists/*
+
+ARG REPO=https://github.com/verilator/verilator
+ARG SOURCE_COMMIT=master
+
+WORKDIR /tmp
+
+# Add an exception for the linter, we want to cd here in one layer
+# to reduce the number of layers (and thereby size).
+# hadolint ignore=DL3003
+RUN git clone "${REPO}" verilator && \
+    cd verilator && \
+    git checkout "${SOURCE_COMMIT}" && \
+    autoconf && \
+    ./configure && \
+    make -j "$(nproc)" && \
+    make install && \
+    cd .. && \
+    rm -r verilator
+
+COPY verilator-wrap.sh /usr/local/bin/verilator-wrap.sh
+
+WORKDIR /work
+
+ENTRYPOINT [ "/usr/local/bin/verilator-wrap.sh" ]

ci/docker/run/README.adoc

@@ -0,0 +1,59 @@
+= Verilator Executable Docker Container
+
+The Verilator Executable Docker Container allows you to run Verilator
+easily as a docker image, e.g.:
+
+    docker run -ti verilator/verilator:latest --version
+
+This will install the container, run the latest Verilator and print
+Verilator's version.
+
+Containers are automatically built for all released versions, so you may
+easily compare results across versions, e.g.:
+
+    docker run -ti verilator/verilator:4.030 --version
+
+Verilator needs to read and write files on the local system.  To simplify
+this process, use the `verilator-docker` convenience script.  This script
+takes the version number, and all remaining arguments are passed through to
+Verilator. e.g.:
+
+    ./verilator-docker 4.030 --version
+
+or
+
+    ./verilator-docker 4.030 --cc test.v
+
+If you prefer not to use `verilator-docker` you must give the container
+access to your files as a volume with appropriate user rights.  For example
+to Verilate test.v:
+
+....
+docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest --cc test.v
+....
+
+This method can only access files below the current directory. An
+alternative is setup the volume `-workdir`.
+
+You can also work in the container by setting the entrypoint
+(don't forget to mount a volume if you want your work persistent):
+
+    docker run -ti --entrypoint /bin/bash verilator/verilator:latest
+
+You can also use the container to build Verilator at a specific
+commit:
+
+    docker build --build-arg SOURCE_COMMIT=<commit> .
+
+== Internals
+
+The Dockerfile builds Verilator and removes the tree when completed to
+reduce the image size. The entrypoint is set as a wrapper script
+(`verilator-wrap.sh`).  That script 1. calls Verilator, and 2. copies the
+Verilated runtime files to the `obj_dir` or the `-Mdir` respectively. This
+allows the user to have the files to they may later build the C++ output
+with the matching runtime files. The wrapper also patches the Verilated
+Makefile accordingly.
+
+There is also a hook defined that is run by docker hub via automated
+builds.

ci/docker/run/hooks/build

@@ -0,0 +1,10 @@
+#!/bin/bash
+# DESCRIPTION: Docker hub hook to pass SOURCE_COMMIT
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+docker build --build-arg SOURCE_COMMIT=${SOURCE_COMMIT} -f $DOCKERFILE_PATH -t $IMAGE_NAME .

ci/docker/run/hooks/post_push

@@ -0,0 +1,13 @@
+#!/bin/bash
+# DESCRIPTION: Docker hub hook to tag the latest release (stable)
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+if [ "$SOURCE_BRANCH"="stable" ]; then
+    docker tag $IMAGE_NAME $DOCKER_REPO:latest
+    docker push $DOCKER_REPO:latest
+fi

ci/docker/run/verilator-docker

@@ -0,0 +1,11 @@
+#!/bin/bash
+# DESCRIPTION: Wrap a verilator call to run a docker container
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+docker pull verilator/verilator:$1 >/dev/null
+docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:$1 "${@:2}"

ci/docker/run/verilator-wrap.sh

@@ -0,0 +1,31 @@
+#!/bin/bash
+# DESCRIPTION: Wrap a Verilator call and copy vlt includes
+#              (inside docker container)
+#
+# Copyright 2020 by Stefan Wallentowitz. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+perl /usr/local/bin/verilator "$@"
+status=$?
+if [ $status -ne 0 ]; then
+    exit $status
+fi
+
+# Check if user set an obj_dir
+obj_dir=$(echo " $@" | grep -oP '\s--Mdir\s*\K\S+')
+if [ "$obj_dir" == "" ]; then
+    obj_dir="obj_dir"
+fi
+
+# If the run was successful: Copy required files to allow build without this container
+if [ -e ${obj_dir} ]; then
+    # Copy files required for the build
+    mkdir -p ${obj_dir}/vlt
+    cp -r /usr/local/share/verilator/bin ${obj_dir}/vlt
+    cp -r /usr/local/share/verilator/include ${obj_dir}/vlt
+    # Point Makefile to that folder
+    perl -i -pe 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk
+fi

ci/test.sh

@@ -1,10 +1,12 @@
 #!/bin/bash
 # DESCRIPTION: Verilator: Travis CI test script
 #
-# Copyright 2019 by Todd Strader. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2019 by Todd Strader. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
 set -e
 
 export DRIVER_FLAGS='-j 0 --quiet --rerun'
@@ -19,6 +21,12 @@ case $1 in
     vltmt)
         make -C test_regress SCENARIOS=--vltmt
         ;;
+    vltmt0)
+        make -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=0/2
+        ;;
+    vltmt1)
+        make -C test_regress SCENARIOS=--vltmt DRIVER_HASHSET=--hashset=1/2
+        ;;
     *)
     echo "Usage: test.sh (dist|vlt|vltmt)"
     exit -1

configure.ac

@@ -1,12 +1,13 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2019 by Wilson Snyder. Verilator is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU Lesser
+# Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[4.024 2019-12-08],
+AC_INIT([Verilator],[4.032 2020-04-04],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 # When releasing, also update header of Changes file
@@ -25,11 +26,43 @@ AC_ARG_ENABLE([maintainer-mode],
 AC_ARG_ENABLE([silent-rules],
               [AS_HELP_STRING([--disable-silent-rules], [ignored])])
 
+# Flag to enable linking specific libraries statically
+AC_MSG_CHECKING(whether to perform partial static linking of Verilator binary)
+AC_ARG_ENABLE([partial-static],
+              [AS_HELP_STRING([--disable-partial-static],
+                              [By default, for Verilation peformance, Verilator
+                               is linked against some of its dependencies
+                               statically. Use this to link the Verilator binary
+                               fully dynamically.])],
+              [case "${enableval}" in
+                yes) CFG_ENABLE_PARTIAL_STATIC=yes ;;
+                no)  CFG_ENABLE_PARTIAL_STATIC=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --disable-partial-static]) ;;
+               esac],
+               CFG_ENABLE_PARTIAL_STATIC=yes)
+AC_MSG_RESULT($CFG_ENABLE_PARTIAL_STATIC)
+
+# Flag to enable linking Verilator with tcmalloc if available
+AC_MSG_CHECKING(whether to use tcmalloc)
+AC_ARG_ENABLE([tcmalloc],
+              [AS_HELP_STRING([--enable-tcmalloc],
+                              [Use libtcmalloc_minimal for faster dynamic memory
+                               management in Verilator binary@<:@default=check@:>@])],
+              [case "${enableval}" in
+                yes) CFG_WITH_TCMALLOC=yes ;;
+                no)  CFG_WITH_TCMALLOC=no ;;
+                *)   AC_MSG_ERROR([bad value '${enableval}' for --enable-tcmalloc]) ;;
+               esac],
+              [CFG_WITH_TCMALLOC=check;])
+AC_MSG_RESULT($CFG_WITH_TCMALLOC)
+
 # Special Substitutions - CFG_WITH_DEFENV
 AC_MSG_CHECKING(whether to use hardcoded paths)
 AC_ARG_ENABLE([defenv],
               [AS_HELP_STRING([--disable-defenv],
-                              [disable using some hardcoded data paths extracted from some default environment variables (the default is to use hardcoded paths)])],
+                              [disable using some hardcoded data paths extracted
+                              from some default environment variables (the default
+                              is to use hardcoded paths) in Verilator binary])],
               [case "${enableval}" in
                 yes) CFG_WITH_DEFENV=yes ;;
                 no)  CFG_WITH_DEFENV=no ;;
@@ -43,7 +76,8 @@ AC_MSG_RESULT($CFG_WITH_DEFENV)
 AC_MSG_CHECKING(whether to show and stop on compilation warnings)
 AC_ARG_ENABLE([ccwarn],
               [AS_HELP_STRING([--enable-ccwarn],
-                              [enable showing and stopping on compilation warnings])],
+                              [enable showing and stopping on compilation warnings
+                               in Verilator binrary and Verilated makefiles])],
               [case "${enableval}" in
                 yes) CFG_WITH_CCWARN=yes ;;
                 no)  CFG_WITH_CCWARN=no ;;
@@ -79,7 +113,8 @@ AC_MSG_RESULT($CFG_WITH_LONGTESTS)
 AC_MSG_CHECKING(whether allow pre-C++11)
 AC_ARG_ENABLE([prec11],
               [AS_HELP_STRING([--enable-prec11],
-                              [enable pre-C++11 compilers])],
+                              [enable pre-C++11 compilers for Verilator binary
+                               and Verilated makefiles])],
               [case "${enableval}" in
                 yes) CFG_WITH_PREC11=yes ;;
                 no)  CFG_WITH_PREC11=no ;;
@@ -209,15 +244,26 @@ AC_DEFUN([_MY_LDLIBS_CHECK_FLAG],
     LIBS="$ACO_SAVE_LIBS"
    ])
 
-AC_DEFUN([_MY_LDLIBS_CHECK_OPT],
-   [# _MY_LDLIBS_CHECK_OPT(flag) -- Check if linker supports specific options
-    # If it does, append flag to variable
-    _MY_LDLIBS_CHECK_FLAG($2)
+AC_DEFUN([_MY_LDLIBS_CHECK_IFELSE],
+   [# _MY_LDLIBS_CHECK_IFELSE(flag,action-if-supported,action-if-not-supported)
+    # Check if linker supports specific flag, if it does do action-if-supported
+    # otherwise do action-if-not-supported
+    _MY_LDLIBS_CHECK_FLAG($1)
     if test "$_my_result" = "yes" ; then
-       $1="$$1 $2"
+      true
+      $2
+    else
+      true
+      $3
     fi
    ])
 
+AC_DEFUN([_MY_LDLIBS_CHECK_OPT],
+   [# _MY_LDLIBS_CHECK_OPT(variable, flag) -- Check if linker supports specific
+    # options. If it does, append flag to variable.
+    _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2")
+   ])
+
 # Flag to select newest language standard supported
 # Macros work such that first option that passes is the one we take
 # gnu++17 code is clean, but SystemC in 2018 doesn't link with it (bug1339)
@@ -256,7 +302,6 @@ AC_SUBST(CFG_CXXFLAGS_WEXTRA)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter)
-_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-undefined-bool-conversion)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow)
 AC_SUBST(CFG_CXXFLAGS_SRC)
 
@@ -310,6 +355,44 @@ m4_foreach([ldflag], [
 AC_SUBST(CFG_LDLIBS_THREADS)
 AC_SUBST(CFG_LDFLAGS_THREADS_CMAKE)
 
+# When linking partially statically
+if test "$CFG_ENABLE_PARTIAL_STATIC" = "yes"; then
+  _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libgcc)
+  _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libstdc++)
+  _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -Xlinker -gc-sections)
+  LTCMALLOC=-l:libtcmalloc_minimal.a
+else
+  LTCMALLOC=-ltcmalloc_minimal
+fi
+AC_SUBST(CFG_LDFLAGS_SRC)
+
+# The pthread library is required by tcmalloc, so add it if it exists. If it
+# does not, the tcmalloc check below will fail anyway, and linking against
+# pthreads is harmless otherwise.
+CFG_LIBS="$LIBS $CFG_LIBS"
+_MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpthread)
+
+# Check libraries for MingW
+_MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lbcrypt)
+_MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpsapi)
+
+# Check if tcmalloc is available based on --enable-tcmalloc
+_MY_LDLIBS_CHECK_IFELSE(
+  $LTCMALLOC,
+  [if test "$CFG_WITH_TCMALLOC" != "no"; then
+    CFG_LIBS="$LTCMALLOC $CFG_LIBS";
+    # If using tcmalloc, add some extra options to make the compiler not assume
+    # it is using it's own versions of the standard library functions
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-malloc)
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-calloc)
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-realloc)
+    _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-free)
+   fi],
+  [if test "$CFG_WITH_TCMALLOC" = "yes"; then
+    AC_MSG_ERROR([--enable-tcmalloc was given but test for ${LTCMALLOC} failed])
+   fi])
+AC_SUBST(CFG_LIBS)
+
 # Set CFG_WITH_THREADED if can support threading
 AC_MSG_CHECKING(whether $CXX supports Verilated threads)
 ACO_SAVE_CXXFLAGS="$CXXFLAGS"

docs/CONTRIBUTING.adoc

@@ -11,7 +11,7 @@ contributions flow more efficiently.
   https://verilator.org/issues[Verilator Issues].
 
 * If you're unable to find an open issue addressing the problem,
-  https://verilator.org/issues/new[open a new issue].
+  https://verilator.org/issues/new[open a new Verilator issue].
 
 ** Be sure to include a **code sample** or an **executable test case**
    demonstrating the bug and expected behavior that is not occurring.
@@ -24,8 +24,8 @@ contributions flow more efficiently.
 
 * Please https://verilator.org/issues/new[Open a new issue].
 
-* You may attach a patch to the issue, or (preferred) may point to a GitHub
-  repository branch within your GitHub account.
+* You may attach a patch to the issue, or (preferred) may request a GitHub
+  pull request.
 
 ** Verilator uses Travis CI to provide continuous integration. You may
    want to setup Travis CI on your GitHub branch to ensure your changes
@@ -50,13 +50,13 @@ contributions flow more efficiently.
    link:CONTRIBUTORS[docs/CONTRIBUTORS] and you are agreeing all future
    contributions are also certified.
 
-** We occasionally accept contributions where people do not want their
-   name published. Please email us; you must still certify your
-   contribution using email.
+** We occasionally accept contributions where people do not want their name
+   published. Please email us; you must still privately certify your
+   contribution.
 
-* Your test contributions are generally considered released into the public
-  domain, unless you request otherwise or put a GNU/Artistic license on
-  your test file.
+* Your test contributions are generally considered released into the
+  Creative Commons Public Domain (CC0), unless you request otherwise or put
+  a GNU/Artistic license on your file.
 
 * Most important is we get your patch. If you'd like to clean up
   indentation and related issues ahead of our feedback, that is

docs/CONTRIBUTORS

@@ -8,9 +8,11 @@ all.
 Ahmed El-Mahmoudy
 Alex Chadwick
 Chris Randall
+David Stanford
 Driss Hafdi
 Eric Rippey
 Garrett Smith
+Geza Lore
 Gianfranco Costamagna
 Howard Su
 Iztok Jeras
@@ -19,15 +21,24 @@ John Coiner
 Julien Margetts
 Kanad Kanhere
 Kevin Kiningham
+Kuba Ober
 Lukasz Dalek
 Maarten De Braekeleer
+Maciej Sobkowski
+Marco Widmer
 Matthew Ballance
 Mike Popoloski
 Patrick Stewart
+Peter Monsson
 Philipp Wagner
+Pieter Kapsenberg
 Richard Myers
+Sean Cross
 Sebastien Van Cauwenberghe
 Stefan Wallentowitz
+Tobias Rosenkranz
+Tobias Wölfel
 Todd Strader
 Wilson Snyder
+Yutetsu TAKATSUKASA
 Yves Mathieu

docs/Makefile.in

@@ -7,15 +7,11 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
-#
-# Verilator is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 #****************************************************************************/
 #

docs/TODO

@@ -1,9 +1,10 @@
 // DESCRIPTION: Verilator: List of To Do issues.
 //
-// Copyright 2004-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
 // Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 * Language support:
 ** Fix ordering of each bit separately in a signal (mips)
@@ -22,17 +23,10 @@
 ** Assertions
 ** Tristate support
 
-* Configure/Make/Install
-** Distribute with flex/bison already expanded?
-   Flex library not needed.  Probably too difficult to be worth it.
-
 * Testing:
-** Capture all inputs into global "rerun it" file
 ** Code to make wrapper that sets signals, so can do comparison checks
 ** New random program generator
 ** Better graph viewer with search and zoom
-** Port and test against opencores.org code
-** // verilator debug in code so can see only tree affecting those nodes
 
 * Usability:
 ** Detect and pre-remove most UNOPTFLATs

docs/clang-format.txt

@@ -0,0 +1,159 @@
+clang-format is used to standardize the indentation of the internal C++
+code.
+
+For the most part clang-format changes provide good consistency, the two
+main exceptions being the indentation of preprocessor directives, and
+tables of statements.
+
+Reformatting is generally performed only before other large changes are to
+be made to a file.  The following files are not yet clang-format clean:
+
+clang-format -i include/verilated.h
+clang-format -i include/verilated_dpi.h
+clang-format -i include/verilated_fst_c.h
+clang-format -i include/verilated_heavy.h
+clang-format -i include/verilated_imp.h
+clang-format -i include/verilated_save.h
+clang-format -i include/verilated_sym_props.h
+clang-format -i include/verilated_unordered_set_map.h
+clang-format -i include/verilated_vcd_c.h
+clang-format -i include/verilatedos.h
+
+clang-format -i include/verilated.cpp
+clang-format -i include/verilated_cov.cpp
+clang-format -i include/verilated_dpi.cpp
+clang-format -i include/verilated_fst_c.cpp
+clang-format -i include/verilated_save.cpp
+clang-format -i include/verilated_threads.cpp
+clang-format -i include/verilated_vcd_c.cpp
+clang-format -i include/verilated_vpi.cpp
+
+clang-format -i src/V3Ast.h
+clang-format -i src/V3AstNodes.h
+clang-format -i src/V3EmitCBase.h
+clang-format -i src/V3Error.h
+clang-format -i src/V3File.h
+clang-format -i src/V3FileLine.h
+clang-format -i src/V3Global.h
+clang-format -i src/V3Graph.h
+clang-format -i src/V3GraphDfa.h
+clang-format -i src/V3GraphStream.h
+clang-format -i src/V3Hashed.h
+clang-format -i src/V3LanguageWords.h
+clang-format -i src/V3LinkDot.h
+clang-format -i src/V3List.h
+clang-format -i src/V3Number.h
+clang-format -i src/V3Options.h
+clang-format -i src/V3OrderGraph.h
+clang-format -i src/V3Os.h
+clang-format -i src/V3ParseImp.h
+clang-format -i src/V3ParseSym.h
+clang-format -i src/V3Partition.h
+clang-format -i src/V3PartitionGraph.h
+clang-format -i src/V3PreLex.h
+clang-format -i src/V3PreProc.h
+clang-format -i src/V3Scoreboard.h
+clang-format -i src/V3SenTree.h
+clang-format -i src/V3Simulate.h
+clang-format -i src/V3Stats.h
+clang-format -i src/V3String.h
+clang-format -i src/V3SymTable.h
+clang-format -i src/V3TSP.h
+clang-format -i src/V3Task.h
+clang-format -i src/V3WidthCommit.h
+
+clang-format -i src/V3Active.cpp
+clang-format -i src/V3ActiveTop.cpp
+clang-format -i src/V3Assert.cpp
+clang-format -i src/V3AssertPre.cpp
+clang-format -i src/V3Ast.cpp
+clang-format -i src/V3AstNodes.cpp
+clang-format -i src/V3Begin.cpp
+clang-format -i src/V3Branch.cpp
+clang-format -i src/V3Broken.cpp
+clang-format -i src/V3CCtors.cpp
+clang-format -i src/V3Case.cpp
+clang-format -i src/V3Cast.cpp
+clang-format -i src/V3Cdc.cpp
+clang-format -i src/V3Changed.cpp
+clang-format -i src/V3Clean.cpp
+clang-format -i src/V3Clock.cpp
+clang-format -i src/V3Combine.cpp
+clang-format -i src/V3Const.cpp
+clang-format -i src/V3Coverage.cpp
+clang-format -i src/V3CoverageJoin.cpp
+clang-format -i src/V3Dead.cpp
+clang-format -i src/V3Delayed.cpp
+clang-format -i src/V3Depth.cpp
+clang-format -i src/V3DepthBlock.cpp
+clang-format -i src/V3EmitC.cpp
+clang-format -i src/V3EmitCInlines.cpp
+clang-format -i src/V3EmitCMake.cpp
+clang-format -i src/V3EmitCSyms.cpp
+clang-format -i src/V3EmitMk.cpp
+clang-format -i src/V3EmitV.cpp
+clang-format -i src/V3EmitXml.cpp
+clang-format -i src/V3Error.cpp
+clang-format -i src/V3Expand.cpp
+clang-format -i src/V3File.cpp
+clang-format -i src/V3FileLine.cpp
+clang-format -i src/V3Gate.cpp
+clang-format -i src/V3GenClk.cpp
+clang-format -i src/V3Graph.cpp
+clang-format -i src/V3GraphAcyc.cpp
+clang-format -i src/V3GraphAlg.cpp
+clang-format -i src/V3GraphDfa.cpp
+clang-format -i src/V3GraphPathChecker.cpp
+clang-format -i src/V3GraphTest.cpp
+clang-format -i src/V3Hashed.cpp
+clang-format -i src/V3Inline.cpp
+clang-format -i src/V3Inst.cpp
+clang-format -i src/V3InstrCount.cpp
+clang-format -i src/V3Life.cpp
+clang-format -i src/V3LifePost.cpp
+clang-format -i src/V3LinkCells.cpp
+clang-format -i src/V3LinkDot.cpp
+clang-format -i src/V3LinkJump.cpp
+clang-format -i src/V3LinkLValue.cpp
+clang-format -i src/V3LinkLevel.cpp
+clang-format -i src/V3LinkParse.cpp
+clang-format -i src/V3LinkResolve.cpp
+clang-format -i src/V3Localize.cpp
+clang-format -i src/V3Name.cpp
+clang-format -i src/V3Number.cpp
+clang-format -i src/V3Number_test.cpp
+clang-format -i src/V3Options.cpp
+clang-format -i src/V3Order.cpp
+clang-format -i src/V3Os.cpp
+clang-format -i src/V3Param.cpp
+clang-format -i src/V3ParseGrammar.cpp
+clang-format -i src/V3ParseImp.cpp
+clang-format -i src/V3ParseLex.cpp
+clang-format -i src/V3Partition.cpp
+clang-format -i src/V3PreProc.cpp
+clang-format -i src/V3PreShell.cpp
+clang-format -i src/V3Premit.cpp
+clang-format -i src/V3ProtectLib.cpp
+clang-format -i src/V3Reloop.cpp
+clang-format -i src/V3Scope.cpp
+clang-format -i src/V3Scoreboard.cpp
+clang-format -i src/V3Slice.cpp
+clang-format -i src/V3Split.cpp
+clang-format -i src/V3SplitAs.cpp
+clang-format -i src/V3SplitVar.cpp
+clang-format -i src/V3Stats.cpp
+clang-format -i src/V3StatsReport.cpp
+clang-format -i src/V3String.cpp
+clang-format -i src/V3Subst.cpp
+clang-format -i src/V3TSP.cpp
+clang-format -i src/V3Table.cpp
+clang-format -i src/V3Task.cpp
+clang-format -i src/V3Trace.cpp
+clang-format -i src/V3TraceDecl.cpp
+clang-format -i src/V3Tristate.cpp
+clang-format -i src/V3Undriven.cpp
+clang-format -i src/V3Unknown.cpp
+clang-format -i src/V3Unroll.cpp
+clang-format -i src/V3Width.cpp
+clang-format -i src/V3WidthSel.cpp
+clang-format -i src/Verilator.cpp

docs/doxygen-mainpage

@@ -3,4 +3,4 @@
  * \section intro_sec Introduction
  *
  * This is a full doxygen analysis of the Verilator source tree.
- */
+ */

docs/install.adoc

@@ -21,9 +21,14 @@ Git, below, maybe a better alternative.) To install as a package:
 
 If this works, skip down to <<Running Verilator>>.
 
+=== Docker
+
+Verilator is available in pre-built Docker containers. See
+https://github.com/verilator/verilator/blob/master/ci/docker/run/README.adoc
+
 === Git
 
-Alternatively, installing Verilator with Git provides the most flexibility.
+Installing Verilator with Git provides the most flexibility.
 For additional options and details see the additional sections below.  In
 brief:
 
@@ -79,6 +84,10 @@ To build Verilator you will need to install some standard packages:
    sudo apt-get install autoconf
    sudo apt-get install flex bison
 
+The following are optional, but improve compilation speed:
+
+   sudo apt-get install libgoogle-perftools-dev
+
 Additionally, to build or run Verilator you need these standard packages:
 
    sudo apt-get install perl python3
@@ -89,18 +98,20 @@ Additionally, to build or run Verilator you need these standard packages:
 
 Those developing Verilator may also want these (see internals.adoc):
 
-   sudo apt-get install gdb asciidoctor graphviz
+   sudo apt-get install gdb asciidoctor graphviz cmake
    cpan install Pod::Perldoc
    cpan install Unix::Processors
+   cpan install Parallel::Forker
+   cpan install Bit::Vector
 
 ==== Install SystemC
 
 If you will be using SystemC (vs straight C++ output), download
-http://www.systemc.org[SystemC].  Follow their installation instructions.
-You will need to set `SYSTEMC_INCLUDE` to point to the include directory
-with systemc.h in it, and `SYSTEMC_LIBDIR` to points to the directory with
-libsystemc.a in it.  (Older installations may set `SYSTEMC` and
-`SYSTEMC_ARCH` instead.)
+https://www.accellera.org/downloads/standards/systemc[SystemC].
+Follow their installation instructions.  You will need to set `SYSTEMC_INCLUDE`
+to point to the include directory with `systemc.h` in it, and `SYSTEMC_LIBDIR`
+to points to the directory with `libsystemc.a` in it.  (Older installations
+may set `SYSTEMC` and `SYSTEMC_ARCH` instead.)
 
 ==== Install GTKWave
 
@@ -289,6 +300,7 @@ or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)].
 
 == License
 
-Copyright 2008-2019 by Wilson Snyder.  Verilator is free software; you can
+Copyright 2008-2020 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

docs/internals.adoc

@@ -70,7 +70,10 @@ The AST is represented at the top level by the class `AstNode`. This
 abstract class has derived classes for the individual components
 (e.g. `AstGenerate` for a generate block) or groups of components
 (e.g. `AstNodeFTask` for functions and tasks, which in turn has `AstFunc`
-and `AstTask` as derived classes).
+and `AstTask` as derived classes). An important property of the `AstNode`
+type hierarchy is that all non-final subclasses of `AstNode` (i.e.: those
+which themselves have subclasses) must be abstract as well, and be named
+with the prefix `AstNode*`. The `astgen` (see below) script relies on this.
 
 Each `AstNode` has pointers to up to four children, accessed by the `op1p`
 through `op4p` methods.  These methods are then abstracted in a specific
@@ -382,12 +385,19 @@ changed; if clear, checking those signals for changes may be skipped.
 
 == Coding Conventions
 
+=== Compiler Version and C++11
+
+Verilator supports GCC 4.4.7 and newer.  GCC 4.4.7 does not support C++11,
+therefore C++11 is generally not required.  Exceptions may be made to
+require C++11 for features that are only practical with C++11,
+e.g. threads.
+
 === Indentation and Naming Style
 
 We will work with contributors to fix up indentation style issues, but it
 is appreciated if you could match our style:
 
-* All files should contain the magic header to insure standard indentation:
+* All files should contain the magic header to ensure standard indentation:
 +
    // -*- mode: C++; c-file-style: "cc-mode" -*-
 +
@@ -615,13 +625,17 @@ with e.g. "sudo cpan install Parallel::Forker".
 * vcddiff to find differences in VCD outputs. See the readme at
 https://github.com/veripool/vcddiff
 
+* Cmake for build paths that use it.
+
+* Bit::Vector to test vgen.pl
+
 === Controlling the Test Driver
 
 Test drivers are written in PERL. All invoke the main test driver script,
 which can provide detailed help on all the features available when writing
 a test driver.
 
-   test_regress/t/driver.pl --help
+   test_regress/driver.pl --help
 
 For convenience, a summary of the most commonly used features is provided
 here. All drivers require a call to `compile` subroutine to compile the
@@ -706,6 +720,13 @@ respectively 16,384 and 4,096. The method of doing this is system
 dependent, but on Fedora Linux it would require editing the
 `/etc/security/limits.conf` file as root.
 
+=== Manual Test Execution
+
+A specific regression test can be executed manually. To start the "EXAMPLE"
+test, run the following command.
+
+   test_regress/t/t_EXAMPLE.pl
+
 === Continuous Integration
 
 Verilator has a https://travis-ci.com/verilator/verilator[Travis CI environment]
@@ -952,7 +973,8 @@ src/VParseGrammar.y, as this grammar supports the full SystemVerilog
 language and has a lot of back-and-forth with Verilator's grammar.  Copy
 the appropriate rules to src/verilog.y and modify the productions.
 
-. If a new Ast type is needed, add it to V3AstNodes.h.
+. If a new Ast type is needed, add it to V3AstNodes.h. Follow the convention
+described above about the AstNode type hierarchy.
 
 . Now you can run "test_regress/t/t_{new testcase}.pl --debug" and it'll
 probably fail but you'll see a test_regress/obj_dir/t_{newtestcase}/*.tree
@@ -973,6 +995,7 @@ list in `src/Makefile_obj.in` and reconfigure.
 
 == Distribution
 
-Copyright 2008-2019 by Wilson Snyder.  Verilator is free software; you can
+Copyright 2008-2020 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

docs/xml.adoc

@@ -0,0 +1,72 @@
+= Verilator XML Output
+:toc: right
+
+// Github doesn't render unless absolute URL
+image::https://www.veripool.org/img/verilator_256_200_min.png[Logo,256,200,role="right"]
+
+== Introduction
+
+This document describes Verilator's XML output. For more general information
+please see https://verilator.org[verilator.org].
+
+== General
+
+Verilator's XML output is enabled with the `--xml-only` flag. It contains
+limited information about the elaborated design including files, modules,
+instance hierarchy, logic and data types. There is no formal schema since part
+of the structure of the XML document matches the compiled code which would
+require the schema to describe legal SystemVerilog structure. The intended
+usage is to enable other downstream tools to take advantage of Verilator's
+parser.
+
+== Structure
+
+The XML document is consists of 4 sections within the top level `verilator_xml`
+element:
+
+`<files>`...`</files>`::
+
+This section contains a list of all design files read, including the
+built-in constructs and the command line as their own entries.  Each
+`<file>` has an attribute `id` which is a short ASCII string unique to that
+file. Other elements' `loc` attributes use this id to refer to a particular
+file.
+
+`<module_files>`...`</module_files>`::
+
+All files containing Verilog module definitions are listed in this section.
+This element's contents is a subset of the `<files>` element's contents.
+
+`<cells>`...`</cells>`::
+
+The cells section of the XML document contains the design instance
+hierarchy.  Each instance is represented with the `<cell>` element with the
+following attributes:
+
+* `fl` (deprecated): The file id and line number where the module was
+  instanced.  Use `loc` instead.
+
+* `loc`: The file id, first line number, last line number, first column
+   number and last column number of the identifier where the module was
+   instanced, separated by commas.
+
+* `name`: The instance name.
+
+* `submodname`: The module name uniquified with particular parameter values (if any).
+
+* `hier`: The full hierarchy path.
+
+`<netlist>`...`</netlist>`::
+
+The netlist section contains a number of `<module>`...`</module>` elements,
+each describing the contents of that module, and a single `<typetable>`...
+`</typetable>` element which lists all used types used within the
+modules. Each type has a numeric `id` attribute that is referred to by
+elements in the `<module>` elements using the `dtype_id` attribute.
+
+== Distribution
+
+Copyright 2020-2020 by Wilson Snyder.  Verilator is free software; you can
+redistribute it and/or modify it under the terms of either the GNU Lesser
+General Public License Version 3 or the Perl Artistic License Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

examples/cmake_hello_c/CMakeLists.txt

@@ -5,10 +5,11 @@
 # This is an example cmake script to build a verilog to systemc project
 # using cmake and verilator.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_hello_c/Makefile

@@ -6,10 +6,11 @@
 # This makefile is here for testing the examples and should
 # generally not be added to a CMake project.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_hello_sc/CMakeLists.txt

@@ -5,10 +5,11 @@
 # This is an example cmake script to build a verilog to SystemC project
 # using CMake and Verilator.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_hello_sc/Makefile

@@ -6,10 +6,11 @@
 # This makefile is here for testing the examples and should
 # generally not be added to a CMake project.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_protect_lib/CMakeLists.txt

@@ -5,10 +5,11 @@
 # This is an example cmake script to build a verilog to systemc project
 # using cmake and verilator.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_protect_lib/Makefile

@@ -6,10 +6,11 @@
 # This makefile is here for testing the examples and should
 # generally not be added to a CMake project.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_tracing_c/CMakeLists.txt

@@ -5,10 +5,11 @@
 # This is an example cmake script to build a verilog to systemc project
 # using cmake and verilator.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 
@@ -34,5 +35,5 @@ add_executable(example ../make_tracing_c/sim_main.cpp)
 # Add the Verilated circuit to the target
 verilate(example COVERAGE TRACE
   INCLUDE_DIRS "../make_tracing_c"
-  VERILATOR_ARGS -f ../make_tracing_c/input.vc -O2 -x-assign 0
+  VERILATOR_ARGS -f ../make_tracing_c/input.vc -Os -x-assign 0
   SOURCES ../make_tracing_c/top.v)

examples/cmake_tracing_c/Makefile

@@ -6,10 +6,11 @@
 # This makefile is here for testing the examples and should
 # generally not be added to a CMake project.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/cmake_tracing_sc/CMakeLists.txt

@@ -5,10 +5,11 @@
 # This is an example cmake script to build a verilog to SystemC project
 # using CMake and Verilator.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 
@@ -41,7 +42,7 @@ add_executable(example ../make_tracing_sc/sc_main.cpp)
 # Add the Verilated circuit to the target
 verilate(example SYSTEMC COVERAGE TRACE
   INCLUDE_DIRS "../make_tracing_sc"
-  VERILATOR_ARGS -f ../make_tracing_sc/input.vc -O2 -x-assign 0
+  VERILATOR_ARGS -f ../make_tracing_sc/input.vc -Os -x-assign 0
   SOURCES ../make_tracing_sc/top.v)
 
 verilator_link_systemc(example)

examples/cmake_tracing_sc/Makefile

@@ -6,10 +6,11 @@
 # This makefile is here for testing the examples and should
 # generally not be added to a CMake project.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/make_hello_c/Makefile

@@ -5,10 +5,11 @@
 # This calls the object directory makefile.  That allows the objects to
 # be placed in the "current directory" which simplifies the Makefile.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 # Check for sanity to avoid later confusion

examples/make_hello_c/sim_main.cpp

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2017 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 //======================================================================
 
 // Include common routines

examples/make_hello_c/top.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2017 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 
 // See also the EXAMPLE section in the verilator manpage/document.
 module top;

examples/make_hello_sc/Makefile

@@ -5,10 +5,11 @@
 # This calls the object directory makefile.  That allows the objects to
 # be placed in the "current directory" which simplifies the Makefile.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 # Check for sanity to avoid later confusion

examples/make_hello_sc/sc_main.cpp

@@ -1,8 +1,9 @@
 // -*- SystemC -*-
 // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2017 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 //======================================================================
 
 // SystemC global header

examples/make_hello_sc/top.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2017 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 
 // See also the EXAMPLE section in the verilator manpage/document.
 module top;

examples/make_protect_lib/Makefile

@@ -5,10 +5,11 @@
 # This calls the object directory makefiles.  That allows the objects to
 # be placed in the "current directory" which simplifies the Makefile.
 #
-# Copyright 2019 by Todd Strader. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 # Check for sanity to avoid later confusion
@@ -34,7 +35,7 @@ VERILATOR_FLAGS =
 # Generate C++
 VERILATOR_FLAGS += -cc
 # Optimize
-VERILATOR_FLAGS += -O2 -x-assign 0
+VERILATOR_FLAGS += -Os -x-assign 0
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms

examples/make_protect_lib/secret_impl.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: --protect-lib example secret module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2019 by Todd Strader.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
 
 // This module will be used as libsecret.a or libsecret.so without
 // exposing the source.

examples/make_protect_lib/sim_main.cpp

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: --protect-lib example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2019 by Todd Strader.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
 //======================================================================
 
 // See examples/tracing_c for notes on tracing

examples/make_protect_lib/top.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: --protect-lib example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2019 by Todd Strader.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
 
 // See also the EXAMPLE section in the verilator manpage/document.
 module top (input clk);

examples/make_tracing_c/Makefile

@@ -5,10 +5,11 @@
 # This calls the object directory makefile.  That allows the objects to
 # be placed in the "current directory" which simplifies the Makefile.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 # Check for sanity to avoid later confusion
@@ -38,7 +39,7 @@ VERILATOR_FLAGS += -cc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 #VERILATOR_FLAGS += -MMD
 # Optimize
-VERILATOR_FLAGS += -O2 -x-assign 0
+VERILATOR_FLAGS += -Os -x-assign 0
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms
@@ -52,6 +53,9 @@ VERILATOR_FLAGS += --coverage
 # Add this trace to get a backtrace in gdb
 #VERILATOR_FLAGS += --gdbbt
 
+# Input files for Verilator
+VERILATOR_INPUT = -f input.vc top.v sim_main.cpp
+
 ######################################################################
 default: run
 
@@ -61,7 +65,7 @@ run:
 
 	@echo
 	@echo "-- VERILATE ----------------"
-	$(VERILATOR) $(VERILATOR_FLAGS) -f input.vc top.v sim_main.cpp
+	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
 
 	@echo
 	@echo "-- COMPILE -----------------"
@@ -72,11 +76,13 @@ run:
 
 	@echo
 	@echo "-- RUN ---------------------"
+	@rm -rf logs
 	@mkdir -p logs
 	obj_dir/Vtop +trace
 
 	@echo
 	@echo "-- COVERAGE ----------------"
+	@rm -rf logs/annotated
 	$(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat
 
 	@echo

examples/make_tracing_c/Makefile_obj

@@ -5,10 +5,11 @@
 #
 # This is executed in the object directory, and called by ../Makefile
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 #######################################################################
 
@@ -38,7 +39,7 @@ endif
 # SystemC takes minutes to optimize, thus it is off by default.
 OPT_SLOW =
 # Fast path optimizations.  Most time is spent in these classes.
-OPT_FAST = -O2 -fstrict-aliasing
+OPT_FAST = -Os -fstrict-aliasing
 #OPT_FAST = -O
 #OPT_FAST =
 

examples/make_tracing_c/sim_main.cpp

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2017 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 //======================================================================
 
 // Include common routines
@@ -10,11 +11,6 @@
 // Include model header, generated from Verilating "top.v"
 #include "Vtop.h"
 
-// If "verilator --trace" is used, include the tracing class
-#if VM_TRACE
-# include <verilated_vcd_c.h>
-#endif
-
 // Current simulation time (64-bit unsigned)
 vluint64_t main_time = 0;
 // Called by $time in Verilog
@@ -36,31 +32,21 @@ int main(int argc, char** argv, char** env) {
     // May be overridden by commandArgs
     Verilated::randReset(2);
 
+    // Verilator must compute traced signals
+    Verilated::traceEverOn(true);
+
     // Pass arguments so Verilated code can see them, e.g. $value$plusargs
     // This needs to be called before you create any model
     Verilated::commandArgs(argc, argv);
 
+    // Create logs/ directory in case we have traces to put under it
+    Verilated::mkdir("logs");
+
     // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
     Vtop* top = new Vtop;  // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper
 
-#if VM_TRACE
-    // If verilator was invoked with --trace argument,
-    // and if at run time passed the +trace argument, turn on tracing
-    VerilatedVcdC* tfp = NULL;
-    const char* flag = Verilated::commandArgsPlusMatch("trace");
-    if (flag && 0==strcmp(flag, "+trace")) {
-        Verilated::traceEverOn(true);  // Verilator must compute traced signals
-        VL_PRINTF("Enabling waves into logs/vlt_dump.vcd...\n");
-        tfp = new VerilatedVcdC;
-        top->trace(tfp, 99);  // Trace 99 levels of hierarchy
-        Verilated::mkdir("logs");
-        tfp->open("logs/vlt_dump.vcd");  // Open the dump file
-    }
-#endif
-
     // Set some inputs
     top->reset_l = !0;
-    top->fastclk = 0;
     top->clk = 0;
     top->in_small = 1;
     top->in_quad = 0x1234;
@@ -72,31 +58,29 @@ int main(int argc, char** argv, char** env) {
     while (!Verilated::gotFinish()) {
         main_time++;  // Time passes...
 
-        // Toggle clocks and such
-        top->fastclk = !top->fastclk;
-        if ((main_time % 10) == 3) {
-            top->clk = 1;
-        }
-        if ((main_time % 10) == 8) {
-            top->clk = 0;
-        }
-        if (main_time > 1 && main_time < 10) {
-            top->reset_l = !1;  // Assert reset
-        } else {
-            top->reset_l = !0;  // Deassert reset
-        }
+        // Toggle a fast (time/2 period) clock
+        top->clk = !top->clk;
 
-        // Assign some other inputs
-        top->in_quad += 0x12;
+        // Toggle control signals on an edge that doesn't correspond
+        // to where the controls are sampled; in this example we do
+        // this only on a negedge of clk, because we know
+        // reset is not sampled there.
+        if (!top->clk) {
+            if (main_time > 1 && main_time < 10) {
+                top->reset_l = !1;  // Assert reset
+            } else {
+                top->reset_l = !0;  // Deassert reset
+            }
+            // Assign some other inputs
+            top->in_quad += 0x12;
+        }
 
         // Evaluate model
+        // (If you have multiple models being simulated in the same
+        // timestep then instead of eval(), call eval_step() on each, then
+        // eval_end_step() on each.)
         top->eval();
 
-#if VM_TRACE
-        // Dump trace data for this cycle
-        if (tfp) tfp->dump(main_time);
-#endif
-
         // Read outputs
         VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
                   " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n",
@@ -107,11 +91,6 @@ int main(int argc, char** argv, char** env) {
     // Final model cleanup
     top->final();
 
-    // Close trace if opened
-#if VM_TRACE
-    if (tfp) { tfp->close(); tfp = NULL; }
-#endif
-
     //  Coverage analysis (since test passed)
 #if VM_COVERAGE
     Verilated::mkdir("logs");

examples/make_tracing_c/sub.v

@@ -1,31 +1,17 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
 module sub
   (
    input clk,
-   input fastclk,
    input reset_l
    );
 
    // Example counter/flop
-   reg [31:0] count_f;
-   always_ff @ (posedge fastclk) begin
-      if (!reset_l) begin
-         /*AUTORESET*/
-         // Beginning of autoreset for uninitialized flops
-         count_f <= 32'h0;
-         // End of automatics
-      end
-      else begin
-         count_f <= count_f + 1;
-      end
-   end
-
-   // Another example flop
    reg [31:0] count_c;
    always_ff @ (posedge clk) begin
       if (!reset_l) begin
@@ -37,8 +23,6 @@ module sub
       else begin
          count_c <= count_c + 1;
          if (count_c >= 3) begin
-            $display("[%0t] fastclk is %0d times faster than clk\n",
-                     $time, count_f/count_c);
             // This write is a magic value the Makefile uses to make sure the
             // test completes successfully.
             $write("*-* All Finished *-*\n");

examples/make_tracing_c/top.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
 // This is intended to be a complex example of several features, please also
@@ -11,7 +12,6 @@ module top
   (
    // Declare some signals so we can see how I/O works
    input         clk,
-   input         fastclk,
    input         reset_l,
 
    output wire [1:0]  out_small,
@@ -31,11 +31,15 @@ module top
    sub sub (/*AUTOINST*/
             // Inputs
             .clk                        (clk),
-            .fastclk                    (fastclk),
             .reset_l                    (reset_l));
 
    // Print some stuff as an example
    initial begin
+      if ($test$plusargs("trace") != 0) begin
+         $display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
+         $dumpfile("logs/vlt_dump.vcd");
+         $dumpvars();
+      end
       $display("[%0t] Model running...\n", $time);
    end
 

examples/make_tracing_sc/Makefile

@@ -5,10 +5,11 @@
 # This calls the object directory makefile.  That allows the objects to
 # be placed in the "current directory" which simplifies the Makefile.
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 # Check for sanity to avoid later confusion
@@ -38,7 +39,7 @@ VERILATOR_FLAGS += -sc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 #VERILATOR_FLAGS += -MMD
 # Optimize
-VERILATOR_FLAGS += -O2 -x-assign 0
+VERILATOR_FLAGS += -Os -x-assign 0
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms
@@ -52,6 +53,9 @@ VERILATOR_FLAGS += --coverage
 # Add this trace to get a backtrace in gdb
 #VERILATOR_FLAGS += --gdbbt
 
+# Input files for Verilator
+VERILATOR_INPUT = -f input.vc top.v sc_main.cpp
+
 # Check if SC exists via a verilator call (empty if not)
 SYSTEMC_EXISTS := $(shell $(VERILATOR) --getenv SYSTEMC_INCLUDE)
 
@@ -69,10 +73,10 @@ run:
 
 	@echo
 	@echo "-- VERILATE ----------------"
-	$(VERILATOR) $(VERILATOR_FLAGS) -f input.vc top.v sc_main.cpp
+	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
 
 	@echo
-	@echo "-- COMPILE ----------------="
+	@echo "-- COMPILE -----------------"
 # To compile, we can either just do what Verilator asks,
 # or call a submakefile where we can override the rules ourselves
 #	$(MAKE) -j 4 -C obj_dir -f Vtop.mk
@@ -80,11 +84,13 @@ run:
 
 	@echo
 	@echo "-- RUN ---------------------"
+	@rm -rf logs
 	@mkdir -p logs
 	obj_dir/Vtop +trace
 
 	@echo
 	@echo "-- COVERAGE ----------------"
+	@rm -rf logs/annotated
 	$(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat
 
 	@echo
@@ -92,6 +98,7 @@ run:
 	@echo "To see waveforms, open vlt_dump.vcd in a waveform viewer"
 	@echo
 
+
 ######################################################################
 # Other targets
 

examples/make_tracing_sc/Makefile_obj

@@ -5,10 +5,11 @@
 #
 # This is executed in the object directory, and called by ../Makefile
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 #######################################################################
 
@@ -46,7 +47,7 @@ endif
 # SystemC takes minutes to optimize, thus it is off by default.
 OPT_SLOW =
 # Fast path optimizations.  Most time is spent in these classes.
-OPT_FAST = -O2 -fstrict-aliasing
+OPT_FAST = -Os -fstrict-aliasing
 #OPT_FAST = -O
 #OPT_FAST =
 

examples/make_tracing_sc/sc_main.cpp

@@ -1,8 +1,9 @@
 // -*- SystemC -*-
 // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2017 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 //======================================================================
 
 // SystemC global header
@@ -37,6 +38,9 @@ int sc_main(int argc, char* argv[]) {
     // This needs to be called before you create any model
     Verilated::commandArgs(argc, argv);
 
+    // Create logs/ directory in case we have traces to put under it
+    Verilated::mkdir("logs");
+
     // General logfile
     ios::sync_with_stdio();
 

examples/make_tracing_sc/sub.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
 module sub

examples/make_tracing_sc/top.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
 // This is intended to be a complex example of several features, please also

examples/xml_py/Makefile

@@ -2,10 +2,11 @@
 #
 # DESCRIPTION: Verilator Example: XML tests
 #
-# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 ######################################################################
 

examples/xml_py/sub.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2019 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
 module sub

examples/xml_py/top.v

@@ -1,7 +1,8 @@
 // DESCRIPTION: Verilator: Verilog example module
 //
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2019 by Wilson Snyder.
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
 module top

examples/xml_py/vl_file_copy

@@ -84,8 +84,10 @@ Example usage:
   -v <filename>              Verilog library
   -y <dir>                   Directory to search for modules
 
-This file ONLY is placed into the Public Domain, for any use, without
-warranty, 2019 by Wilson Snyder."""
+This file ONLY is placed under the Creative Commons Public Domain, for
+any use, without warranty, 2019 by Wilson Snyder.
+SPDX-License-Identifier: CC0-1.0
+"""
     )
     parser.add_argument('-debug', '--debug',
                         action='store_const', const=9,

examples/xml_py/vl_hier_graph

@@ -108,8 +108,10 @@ Example usage:
   -v <filename>              Verilog library
   -y <dir>                   Directory to search for modules
 
-This file ONLY is placed into the Public Domain, for any use, without
-warranty, 2019 by Wilson Snyder."""
+This file ONLY is placed under the Creative Commons Public Domain, for
+any use, without warranty, 2019 by Wilson Snyder.
+SPDX-License-Identifier: CC0-1.0
+"""
     )
     parser.add_argument('-debug', '--debug',
                         action='store_const', const=9,

include/gtkwave/fastlz.c

@@ -22,6 +22,8 @@
   LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   THE SOFTWARE.
+
+  SPDX-License-Identifier: MIT
 */
 
 #include "fastlz.h"
@@ -418,9 +420,7 @@ static FASTLZ_INLINE int FASTLZ_DECOMPRESSOR(const void* input, int length, void
   const flzuint8* ip = (const flzuint8*) input;
   const flzuint8* ip_limit  = ip + length;
   flzuint8* op = (flzuint8*) output;
-#ifdef FASTLZ_SAFE
   flzuint8* op_limit = op + maxout;
-#endif
   flzuint32 ctrl = (*ip++) & 31;
   int loop = 1;
 

include/gtkwave/fastlz.h

@@ -22,6 +22,8 @@
   LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   THE SOFTWARE.
+
+  SPDX-License-Identifier: MIT
 */
 
 #ifndef FASTLZ_H

include/gtkwave/fstapi.c

@@ -18,6 +18,8 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: MIT
  */
 
 /*
@@ -133,9 +135,9 @@ void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint3
 #endif
 
 #ifdef __GNUC__
-// Boolean expression more often true than false
+/* Boolean expression more often true than false */
 #define FST_LIKELY(x) __builtin_expect(!!(x), 1)
-// Boolean expression more often false than true
+/* Boolean expression more often false than true */
 #define FST_UNLIKELY(x) __builtin_expect(!!(x), 0)
 #else
 #define FST_LIKELY(x) (!!(x))
@@ -737,6 +739,9 @@ off_t hier_file_len;
 uint32_t *valpos_mem;
 unsigned char *curval_mem;
 
+unsigned char *outval_mem; /* for two-state / Verilator-style value changes */
+uint32_t outval_alloc_siz;
+
 char *filename;
 
 fstHandle maxhandle;
@@ -1021,7 +1026,9 @@ if(!xc->curval_mem)
 
 static void fstDestroyMmaps(struct fstWriterContext *xc, int is_closing)
 {
+#if !defined __CYGWIN__ && !defined __MINGW32__
 (void)is_closing;
+#endif
 
 fstMunmap(xc->valpos_mem, xc->maxhandle * 4 * sizeof(uint32_t));
 xc->valpos_mem = NULL;
@@ -1944,6 +1951,11 @@ if(xc && !xc->already_in_close && !xc->already_in_flush)
                         }
                 }
         fstDestroyMmaps(xc, 1);
+	if(xc->outval_mem)
+		{
+		free(xc->outval_mem); xc->outval_mem = NULL;
+		xc->outval_alloc_siz = 0;
+		}
 
         /* write out geom section */
         fflush(xc->geom_handle);
@@ -2913,7 +2925,7 @@ if(FST_LIKELY((xc) && (handle <= xc->maxhandle)))
                                 {
                                 xc->vchg_alloc_siz += (xc->fst_break_add_size + len); /* +len added in the case of extremely long vectors and small break add sizes */
                                 xc->vchg_mem = (unsigned char *)realloc(xc->vchg_mem, xc->vchg_alloc_siz);
-                                if(VL_UNLIKELY(!xc->vchg_mem))
+                                if(FST_UNLIKELY(!xc->vchg_mem))
                                         {
                                         fprintf(stderr, FST_APIMESS "Could not realloc() in fstWriterEmitValueChange, exiting.\n");
                                         exit(255);
@@ -2998,6 +3010,127 @@ if(FST_LIKELY((xc) && (handle <= xc->maxhandle)))
         }
 }
 
+void fstWriterEmitValueChange32(void *ctx, fstHandle handle,
+                                uint32_t bits, uint32_t val) {
+        char buf[32];
+        char *s = buf;
+        uint32_t i;
+        for (i = 0; i < bits; ++i)
+        {
+                *s++ = '0' + ((val >> (bits - i - 1)) & 1);
+        }
+        fstWriterEmitValueChange(ctx, handle, buf);
+}
+void fstWriterEmitValueChange64(void *ctx, fstHandle handle,
+                                uint32_t bits, uint64_t val) {
+        char buf[64];
+        char *s = buf;
+        uint32_t i;
+        for (i = 0; i < bits; ++i)
+        {
+                *s++ = '0' + ((val >> (bits - i - 1)) & 1);
+        }
+        fstWriterEmitValueChange(ctx, handle, buf);
+}
+void fstWriterEmitValueChangeVec32(void *ctx, fstHandle handle,
+                                   uint32_t bits, const uint32_t *val) {
+        struct fstWriterContext *xc = (struct fstWriterContext *)ctx;
+        if (FST_UNLIKELY(bits <= 32))
+        {
+                fstWriterEmitValueChange32(ctx, handle, bits, val[0]);
+        }
+        else if(FST_LIKELY(xc))
+        {
+                int bq = bits / 32;
+                int br = bits & 31;
+                int i;
+                int w;
+                uint32_t v;
+                unsigned char* s;
+                if (FST_UNLIKELY(bits > xc->outval_alloc_siz))
+                {
+                        xc->outval_alloc_siz = bits*2 + 1;
+                        xc->outval_mem = (unsigned char*)realloc(xc->outval_mem, xc->outval_alloc_siz);
+                        if (FST_UNLIKELY(!xc->outval_mem))
+                        {
+                                fprintf(stderr,
+                                        FST_APIMESS "Could not realloc() in fstWriterEmitValueChangeVec32, exiting.\n");
+                                exit(255);
+                        }
+                }
+                s = xc->outval_mem;
+                {
+                        w = bq;
+                        v = val[w];
+                        for (i = 0; i < br; ++i)
+                        {
+                                *s++ = '0' + ((v >> (br - i - 1)) & 1);
+                        }
+                }
+                for (w = bq - 1; w >= 0; --w)
+                {
+                        v = val[w];
+                        for (i = (32 - 4); i >= 0; i -= 4) {
+                                s[0] = '0' + ((v >> (i + 3)) & 1);
+                                s[1] = '0' + ((v >> (i + 2)) & 1);
+                                s[2] = '0' + ((v >> (i + 1)) & 1);
+                                s[3] = '0' + ((v >> (i + 0)) & 1);
+                                s += 4;
+                        }
+                }
+                fstWriterEmitValueChange(ctx, handle, xc->outval_mem);
+        }
+}
+void fstWriterEmitValueChangeVec64(void *ctx, fstHandle handle,
+                                   uint32_t bits, const uint64_t *val) {
+        struct fstWriterContext *xc = (struct fstWriterContext *)ctx;
+        if (FST_UNLIKELY(bits <= 64))
+        {
+                fstWriterEmitValueChange64(ctx, handle, bits, val[0]);
+        }
+        else if(FST_LIKELY(xc))
+        {
+                int bq = bits / 64;
+                int br = bits & 63;
+                int i;
+                int w;
+                uint32_t v;
+                unsigned char* s;
+                if (FST_UNLIKELY(bits > xc->outval_alloc_siz))
+                {
+                        xc->outval_alloc_siz = bits*2 + 1;
+                        xc->outval_mem = (unsigned char*)realloc(xc->outval_mem, xc->outval_alloc_siz);
+                        if (FST_UNLIKELY(!xc->outval_mem))
+                        {
+                                fprintf(stderr,
+                                        FST_APIMESS "Could not realloc() in fstWriterEmitValueChangeVec64, exiting.\n");
+                                exit(255);
+                        }
+                }
+                s = xc->outval_mem;
+                {
+                        w = bq;
+                        v = val[w];
+                        for (i = 0; i < br; ++i)
+                        {
+                                *s++ = '0' + ((v >> (br - i - 1)) & 1);
+                        }
+                }
+                for (w = bq - 1; w >= 0; --w) {
+                        v = val[w];
+                        for (i = (64 - 4); i >= 0; i -= 4)
+                        {
+                                s[0] = '0' + ((v >> (i + 3)) & 1);
+                                s[1] = '0' + ((v >> (i + 2)) & 1);
+                                s[2] = '0' + ((v >> (i + 1)) & 1);
+                                s[3] = '0' + ((v >> (i + 0)) & 1);
+                                s += 4;
+                        }
+                }
+                fstWriterEmitValueChange(ctx, handle, xc->outval_mem);
+        }
+}
+
 
 void fstWriterEmitVariableLengthValueChange(void *ctx, fstHandle handle, const void *val, uint32_t len)
 {

include/gtkwave/fstapi.h

@@ -18,6 +18,8 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: MIT
  */
 
 #ifndef FST_API_H
@@ -355,6 +357,14 @@ fstHandle       fstWriterCreateVar2(void *ctx, enum fstVarType vt, enum fstVarDi
 void            fstWriterEmitDumpActive(void *ctx, int enable);
 void 		fstWriterEmitEnumTableRef(void *ctx, fstEnumHandle handle);
 void            fstWriterEmitValueChange(void *ctx, fstHandle handle, const void *val);
+void            fstWriterEmitValueChange32(void *ctx, fstHandle handle,
+                        uint32_t bits, uint32_t val);
+void            fstWriterEmitValueChange64(void *ctx, fstHandle handle,
+                        uint32_t bits, uint64_t val);
+void            fstWriterEmitValueChangeVec32(void *ctx, fstHandle handle,
+                        uint32_t bits, const uint32_t *val);
+void            fstWriterEmitValueChangeVec64(void *ctx, fstHandle handle,
+                        uint32_t bits, const uint64_t *val);
 void            fstWriterEmitVariableLengthValueChange(void *ctx, fstHandle handle, const void *val, uint32_t len);
 void            fstWriterEmitTimeChange(void *ctx, uint64_t tim);
 void            fstWriterFlushContext(void *ctx);

include/gtkwave/lz4.c

@@ -27,6 +27,8 @@
    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+   SPDX-License-Identifier: BSD-2-Clause
+
    You can contact the author at :
    - LZ4 source repository : https://github.com/Cyan4973/lz4
    - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c

include/gtkwave/lz4.h

@@ -28,6 +28,8 @@
    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+   SPDX-License-Identifier: BSD-2-Clause
+
    You can contact the author at :
    - LZ4 source repository : https://github.com/Cyan4973/lz4
    - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c

include/gtkwave/wavealloca.h

@@ -18,6 +18,8 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: MIT
  */
 
 #ifndef WAVE_ALLOCA_H
@@ -33,9 +35,6 @@
 #else
 #include <malloc.h>
 #endif
-#elif defined(_MSC_VER)
-#include <malloc.h>
-#define alloca _alloca
 #endif
 #define wave_alloca alloca
 #endif

include/verilated.mk.in

@@ -2,9 +2,11 @@
 ######################################################################
 # DESCRIPTION: Makefile commands for all verilated target files
 #
-# Copyright 2003-2019 by Wilson Snyder. Verilator is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU Lesser
-# General Public License Version 3 or the Perl Artistic License Version 2.0.
+# Copyright 2003-2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ######################################################################
 
 PERL = @PERL@
@@ -86,7 +88,7 @@ LDLIBS   += $(VM_USER_LDLIBS)
 # SystemC takes minutes to optimize, thus it is off by default.
 #OPT_SLOW =
 # Fast path optimizations.  Most time is spent in these classes.
-#OPT_FAST = -O2 -fstrict-aliasing
+#OPT_FAST = -Os -fstrict-aliasing
 #OPT_FAST = -O
 #OPT_FAST =
 

include/verilated.v

@@ -4,15 +4,11 @@
 //
 //*************************************************************************
 //
-// Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License.
+// Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
-//
-// This is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=========================================================================
 //

include/verilated_config.h.in

@@ -1,15 +1,11 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //*************************************************************************
 //
-// Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License.
+// Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
-//
-// Verilator is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //*************************************************************************
 ///

include/verilated_cov.cpp

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2001-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///
@@ -73,12 +70,12 @@ private:
 public:
     // METHODS
     // cppcheck-suppress truncLongCastReturn
-    virtual vluint64_t count() const { return *m_countp; }
-    virtual void zero() const { *m_countp = 0; }
+    virtual vluint64_t count() const VL_OVERRIDE { return *m_countp; }
+    virtual void zero() const VL_OVERRIDE { *m_countp = 0; }
     // CONSTRUCTORS
     // cppcheck-suppress noExplicitConstructor
-    VerilatedCoverItemSpec(T* countp) : m_countp(countp) { *m_countp = 0; }
-    virtual ~VerilatedCoverItemSpec() {}
+    explicit VerilatedCoverItemSpec(T* countp) : m_countp(countp) { *m_countp = 0; }
+    virtual ~VerilatedCoverItemSpec() VL_OVERRIDE {}
 };
 
 //=============================================================================
@@ -222,7 +219,7 @@ private:
     void clearGuts() VL_REQUIRES(m_mutex) {
         for (ItemList::const_iterator it=m_items.begin(); it!=m_items.end(); ++it) {
             VerilatedCovImpItem* itemp = *(it);
-            delete itemp;
+            VL_DO_DANGLING(delete itemp, itemp);
         }
         m_items.clear();
         m_indexValues.clear();
@@ -244,7 +241,7 @@ public:
             for (ItemList::iterator it=m_items.begin(); it!=m_items.end(); ++it) {
                 VerilatedCovImpItem* itemp = *(it);
                 if (!itemMatchesString(itemp, matchp)) {
-                    delete itemp;
+                    VL_DO_DANGLING(delete itemp, itemp);
                 } else {
                     newlist.push_back(itemp);
                 }

include/verilated_cov.h

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2001-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///
@@ -32,9 +29,15 @@
 /// Conditionally compile coverage code
 
 #ifdef VM_COVERAGE
-# define VL_IF_COVER(stmts) do { stmts ; } while(0)
+# define VL_IF_COVER(stmts) \
+    do { \
+        stmts; \
+    } while (false)
 #else
-# define VL_IF_COVER(stmts) do { if(0) { stmts ; } } while(0)
+# define VL_IF_COVER(stmts) \
+    do { \
+        if (false) { stmts; } \
+    } while (false)
 #endif
 
 //=============================================================================
@@ -65,10 +68,10 @@
 ///             VL_COVER_INSERT(&m_cases[i], "comment", "Coverage Case", "i", cvtToNumStr(i));
 ///     }
 
-#define VL_COVER_INSERT(countp,args...) \
+#define VL_COVER_INSERT(countp,...) \
     VL_IF_COVER(VerilatedCov::_inserti(countp); \
                 VerilatedCov::_insertf(__FILE__, __LINE__); \
-                VerilatedCov::_insertp("hier", name(), args))
+                VerilatedCov::_insertp("hier", name(), __VA_ARGS__))
 
 //=============================================================================
 /// Convert VL_COVER_INSERT value arguments to strings

include/verilated_cov_key.h

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2001-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///

include/verilated_dpi.cpp

@@ -1,15 +1,11 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //*************************************************************************
 //
-// Copyright 2009-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License.
+// Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
-//
-// Verilator is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=========================================================================
 ///
@@ -46,8 +42,8 @@
     VL_FATAL_MT(__FILE__, __LINE__, "", \
                 (std::string("%%Error: Unsupported DPI function: ")+VL_FUNC).c_str())
 
-#define _VL_SVDPI_WARN(message...) \
-    VL_PRINTF_MT(message)
+#define _VL_SVDPI_WARN(...) \
+    VL_PRINTF_MT(__VA_ARGS__)
 
 // Function requires a "context" in the import declaration
 #define _VL_SVDPI_CONTEXT_WARN() \

include/verilated_dpi.h

@@ -1,15 +1,11 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //*************************************************************************
 //
-// Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License.
+// Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
-//
-// Verilator is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //*************************************************************************
 ///

include/verilated_fst_c.cpp

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2001-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///
@@ -20,6 +17,7 @@
 //=============================================================================
 // SPDIFF_OFF
 
+#define __STDC_LIMIT_MACROS  // UINT64_MAX
 #include "verilatedos.h"
 #include "verilated.h"
 #include "verilated_fst_c.h"
@@ -47,6 +45,7 @@
 #if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__)
 # include <io.h>
 #else
+# include <stdint.h>
 # include <unistd.h>
 #endif
 
@@ -62,9 +61,12 @@ protected:
     vluint32_t m_code;  ///< Starting code number
     // CONSTRUCTORS
     VerilatedFstCallInfo(VerilatedFstCallback_t icb, VerilatedFstCallback_t fcb,
-                         VerilatedFstCallback_t changecb,
-                         void* ut, vluint32_t code)
-        : m_initcb(icb), m_fullcb(fcb), m_changecb(changecb), m_userthis(ut), m_code(code) {}
+                         VerilatedFstCallback_t changecb, void* ut)
+        : m_initcb(icb)
+        , m_fullcb(fcb)
+        , m_changecb(changecb)
+        , m_userthis(ut)
+        , m_code(1) {}
     ~VerilatedFstCallInfo() {}
 };
 
@@ -72,10 +74,11 @@ protected:
 // VerilatedFst
 
 VerilatedFst::VerilatedFst(void* fst)
-    : m_fst(fst),
-      m_fullDump(true),
-      m_scopeEscape('.') {
-    m_valueStrBuffer.reserve(64+1);  // Need enough room for quad
+    : m_fst(fst)
+    , m_fullDump(true)
+    , m_nextCode(1)
+    , m_scopeEscape('.') {
+    m_valueStrBuffer.reserve(64 + 1);  // Need enough room for quad
 }
 
 void VerilatedFst::open(const char* filename) VL_MT_UNSAFE {
@@ -86,10 +89,12 @@ void VerilatedFst::open(const char* filename) VL_MT_UNSAFE {
     fstWriterSetParallelMode(m_fst, 1);
 #endif
     m_curScope.clear();
+    m_nextCode = 1;
 
     for (vluint32_t ent = 0; ent< m_callbacks.size(); ++ent) {
         VerilatedFstCallInfo* cip = m_callbacks[ent];
-        cip->m_code = 1;
+        cip->m_code = m_nextCode;
+        // Initialize; callbacks will call decl* which update m_nextCode
         (cip->m_initcb)(this, cip->m_userthis, cip->m_code);
     }
 
@@ -116,9 +121,15 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elem
     m_local2fstdtype[dtypenum] = enumNum;
 }
 
-void VerilatedFst::declSymbol(vluint32_t code, const char* name,
-                              int dtypenum, fstVarDir vardir, fstVarType vartype,
-                              int arraynum, vluint32_t len) {
+void VerilatedFst::declSymbol(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                              fstVarType vartype, bool array, int arraynum, vluint32_t len,
+                              vluint32_t bits) {
+
+    // Make sure deduplicate tracking increments for future declarations
+    int codesNeeded = 1 + int(bits / 32);
+    //Not supported: if (tri) codesNeeded *= 2;  // Space in change array for __en signals
+    m_nextCode = std::max(m_nextCode, code + codesNeeded);
+
     std::pair<Code2SymbolType::iterator, bool> p
         = m_code2symbol.insert(std::make_pair(code, static_cast<fstHandle>(NULL)));
     std::istringstream nameiss(name);
@@ -153,8 +164,7 @@ void VerilatedFst::declSymbol(vluint32_t code, const char* name,
 
     std::stringstream name_ss;
     name_ss << symbol_name;
-    if (arraynum >= 0)
-        name_ss << "(" << arraynum << ")";
+    if (array) name_ss << "(" << arraynum << ")";
     std::string name_str = name_ss.str();
 
     if (dtypenum > 0) {
@@ -172,17 +182,16 @@ void VerilatedFst::declSymbol(vluint32_t code, const char* name,
 //=============================================================================
 // Callbacks
 
-void VerilatedFst::addCallback(
-    VerilatedFstCallback_t initcb, VerilatedFstCallback_t fullcb,
-    VerilatedFstCallback_t changecb, void* userthis) VL_MT_UNSAFE_ONE {
+void VerilatedFst::addCallback(VerilatedFstCallback_t initcb, VerilatedFstCallback_t fullcb,
+                               VerilatedFstCallback_t changecb, void* userthis) VL_MT_UNSAFE_ONE {
     m_assertOne.check();
     if (VL_UNLIKELY(isOpen())) {
-        std::string msg = (std::string("Internal: ")+__FILE__+"::"+__FUNCTION__
-                           +" called with already open file");
+        std::string msg = (std::string("Internal: ") + __FILE__ + "::" + __FUNCTION__
+                           + " called with already open file");
         VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str());
     }
-    VerilatedFstCallInfo* vci = new VerilatedFstCallInfo(initcb, fullcb, changecb, userthis, 1);
-    m_callbacks.push_back(vci);
+    VerilatedFstCallInfo* cip = new VerilatedFstCallInfo(initcb, fullcb, changecb, userthis);
+    m_callbacks.push_back(cip);
 }
 
 //=============================================================================
@@ -191,7 +200,7 @@ void VerilatedFst::addCallback(
 void VerilatedFst::dump(vluint64_t timeui) {
     if (!isOpen()) return;
     if (VL_UNLIKELY(m_fullDump)) {
-        m_fullDump = false;  // No need for more full dumps
+        m_fullDump = false;  // No more need for next dump to be full
         for (vluint32_t ent = 0; ent< m_callbacks.size(); ++ent) {
             VerilatedFstCallInfo* cip = m_callbacks[ent];
             (cip->m_fullcb)(this, cip->m_userthis, cip->m_code);
@@ -205,51 +214,6 @@ void VerilatedFst::dump(vluint64_t timeui) {
     }
 }
 
-//=============================================================================
-// Helpers
-
-char* VerilatedFst::word2Str(vluint32_t newval, int bits) {
-    // Constructor makes sure m_valueStrBuffer.reserve() > 32+1
-    char* s = m_valueStrBuffer.data();
-    for (int i = 0; i < bits; ++i) {
-        *s++ = '0' + ((newval>>(bits-i-1))&1);
-    }
-    *s = '\0';
-    return m_valueStrBuffer.data();
-}
-
-char* VerilatedFst::quad2Str(vluint64_t newval, int bits) {
-    // Constructor makes sure m_valueStrBuffer.reserve() > 64+1
-    char* s = m_valueStrBuffer.data();
-    for (int i = 0; i < bits; ++i) {
-        *s++ = '0' + ((newval>>(bits-i-1))&1);
-    }
-    *s = '\0';
-    return m_valueStrBuffer.data();
-}
-
-char* VerilatedFst::array2Str(const vluint32_t* newval, int bits) {
-    int bq = VL_BITWORD_I(bits), br = VL_BITBIT_I(bits);
-    m_valueStrBuffer.reserve(bits+1);
-    char* s = m_valueStrBuffer.data();
-    vluint32_t v = newval[bq];
-    for (int i = 0; i < br; ++i) {
-        *s++ = '0' + ((v>>(br-i-1))&1);
-    }
-    for (int w = bq-1; w >= 0; --w) {
-        v = newval[w];
-        for (int i = 28; i >= 0; i-=4) {
-            s[0] = '0' + ((v>>(i+3))&1);
-            s[1] = '0' + ((v>>(i+2))&1);
-            s[2] = '0' + ((v>>(i+1))&1);
-            s[3] = '0' + ((v>>(i+0))&1);
-            s+=4;
-        }
-    }
-    *s = '\0';
-    return m_valueStrBuffer.data();
-}
-
 //********************************************************************
 // Local Variables:
 // End:

include/verilated_fst_c.h

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2001-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///
@@ -50,6 +47,7 @@ private:
     void* m_fst;
     VerilatedAssertOneThread m_assertOne;  ///< Assert only called from single thread
     bool m_fullDump;
+    vluint32_t m_nextCode;  ///< Next code number to assign
     char m_scopeEscape;
     std::string m_module;
     CallbackVec m_callbacks;  ///< Routines to perform dumping
@@ -60,15 +58,13 @@ private:
     VL_UNCOPYABLE(VerilatedFst);
     void declSymbol(vluint32_t code, const char* name,
                     int dtypenum, fstVarDir vardir, fstVarType vartype,
-                    int arraynum, vluint32_t len);
+                    bool array, int arraynum, vluint32_t len, vluint32_t bits);
     // helpers
     std::vector<char> m_valueStrBuffer;
-    char* word2Str(vluint32_t newval, int bits);
-    char* quad2Str(vluint64_t newval, int bits);
-    char* array2Str(const vluint32_t *newval, int bits);
 public:
     explicit VerilatedFst(void* fst=NULL);
     ~VerilatedFst() { if (m_fst == NULL) { fstWriterClose(m_fst); } }
+    void changeThread() { m_assertOne.changeThread(); }
     bool isOpen() const { return m_fst != NULL; }
     void open(const char* filename) VL_MT_UNSAFE;
     void flush() VL_MT_UNSAFE { fstWriterFlushContext(m_fst); }
@@ -106,33 +102,36 @@ public:
     /// Inside dumping routines, declare a signal
     void declBit(vluint32_t code, const char* name,
                  int dtypenum, fstVarDir vardir, fstVarType vartype,
-                 int arraynum) {
-        declSymbol(code, name, dtypenum, vardir, vartype, arraynum, 1);
+                 bool array, int arraynum) {
+        declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, 1, 1);
     }
     void declBus(vluint32_t code, const char* name,
                  int dtypenum, fstVarDir vardir, fstVarType vartype,
-                 int arraynum, int msb, int lsb) {
-        declSymbol(code, name, dtypenum, vardir, vartype, arraynum, msb - lsb + 1);
+                 bool array, int arraynum, int msb, int lsb) {
+        declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, msb - lsb + 1,
+                   msb - lsb + 1);
     }
     void declDouble(vluint32_t code, const char* name,
                     int dtypenum, fstVarDir vardir, fstVarType vartype,
-                    int arraynum) {
-        declSymbol(code, name, dtypenum, vardir, vartype, arraynum, 2);
+                    bool array, int arraynum) {
+        declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, 2, 64);
     }
     void declFloat(vluint32_t code, const char* name,
                    int dtypenum, fstVarDir vardir, fstVarType vartype,
-                   int arraynum) {
-        declSymbol(code, name, dtypenum, vardir, vartype, arraynum, 1);
+                   bool array, int arraynum) {
+        declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, 1, 32);
     }
     void declQuad(vluint32_t code, const char* name,
                   int dtypenum, fstVarDir vardir, fstVarType vartype,
-                  int arraynum, int msb, int lsb) {
-        declSymbol(code, name, dtypenum, vardir, vartype, arraynum, msb - lsb + 1);
+                  bool array, int arraynum, int msb, int lsb) {
+        declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, msb - lsb + 1,
+                   msb - lsb + 1);
     }
     void declArray(vluint32_t code, const char* name,
                    int dtypenum, fstVarDir vardir, fstVarType vartype,
-                   int arraynum, int msb, int lsb) {
-        declSymbol(code, name, dtypenum, vardir, vartype, arraynum, msb - lsb + 1);
+                   bool array, int arraynum, int msb, int lsb) {
+        declSymbol(code, name, dtypenum, vardir, vartype, array, arraynum, msb - lsb + 1,
+                   msb - lsb + 1);
     }
 
     /// Inside dumping routines, dump one signal if it has changed
@@ -140,7 +139,7 @@ public:
         fstWriterEmitValueChange(m_fst, m_code2symbol[code], newval ? "1" : "0");
     }
     void chgBus(vluint32_t code, const vluint32_t newval, int bits) {
-        fstWriterEmitValueChange(m_fst, m_code2symbol[code], word2Str(newval, bits));
+        fstWriterEmitValueChange32(m_fst, m_code2symbol[code], bits, newval);
     }
     void chgDouble(vluint32_t code, const double newval) {
         double val = newval;
@@ -151,10 +150,10 @@ public:
         fstWriterEmitValueChange(m_fst, m_code2symbol[code], &val);
     }
     void chgQuad(vluint32_t code, const vluint64_t newval, int bits) {
-        fstWriterEmitValueChange(m_fst, m_code2symbol[code], quad2Str(newval, bits));
+        fstWriterEmitValueChange64(m_fst, m_code2symbol[code], bits, newval);
     }
     void chgArray(vluint32_t code, const vluint32_t* newval, int bits) {
-        fstWriterEmitValueChange(m_fst, m_code2symbol[code], array2Str(newval, bits));
+        fstWriterEmitValueChangeVec32(m_fst, m_code2symbol[code], bits, newval);
     }
 
     void fullBit(vluint32_t code, const vluint32_t newval) {
@@ -170,10 +169,10 @@ public:
     void fullArray(vluint32_t code, const vluint32_t* newval, int bits) {
         chgArray(code, newval, bits); }
 
-    void declTriBit   (vluint32_t code, const char* name, int arraynum);
-    void declTriBus   (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
-    void declTriQuad  (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
-    void declTriArray (vluint32_t code, const char* name, int arraynum, int msb, int lsb);
+    void declTriBit(vluint32_t code, const char* name, int arraynum);
+    void declTriBus(vluint32_t code, const char* name, int arraynum, int msb, int lsb);
+    void declTriQuad(vluint32_t code, const char* name, int arraynum, int msb, int lsb);
+    void declTriArray(vluint32_t code, const char* name, int arraynum, int msb, int lsb);
     void fullTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri);
     void fullTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, int bits);
     void fullTriQuad(vluint32_t code, const vluint64_t newval, const vluint32_t newtri, int bits);
@@ -201,7 +200,9 @@ class VerilatedFstC {
     VL_UNCOPYABLE(VerilatedFstC);
 public:
     explicit VerilatedFstC(void* filep=NULL) : m_sptrace(filep) {}
-    ~VerilatedFstC() {}
+    ~VerilatedFstC() { close(); }
+    /// Routines can only be called from one thread; allow next call from different thread
+    void changeThread() { spTrace()->changeThread(); }
 public:
     // ACCESSORS
     /// Is file open?

include/verilated_heavy.h

@@ -1,15 +1,11 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //*************************************************************************
 //
-// Copyright 2010-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2010-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License.
+// Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
-//
-// Verilator is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //*************************************************************************
 ///
@@ -37,11 +33,43 @@
 //===================================================================
 // String formatters (required by below containers)
 
-extern std::string VL_TO_STRING(CData obj);
-extern std::string VL_TO_STRING(SData obj);
-extern std::string VL_TO_STRING(IData obj);
-extern std::string VL_TO_STRING(QData obj);
-inline std::string VL_TO_STRING(const std::string& obj) { return "\""+obj+"\""; }
+extern std::string VL_TO_STRING(CData lhs);
+extern std::string VL_TO_STRING(SData lhs);
+extern std::string VL_TO_STRING(IData lhs);
+extern std::string VL_TO_STRING(QData lhs);
+inline std::string VL_TO_STRING(const std::string& obj) { return "\"" + obj + "\""; }
+extern std::string VL_TO_STRING_W(int words, WDataInP obj);
+
+//===================================================================
+// Readmem/Writemem operation classes
+
+class VlReadMem {
+    bool m_hex;  // Hex format
+    int m_bits;  // Bit width of values
+    const std::string& m_filename;  // Filename
+    QData m_end;  // End address (as specified by user)
+    FILE* m_fp;  // File handle for filename
+    QData m_addr;  // Next address to read
+    int m_linenum;  // Line number last read from file
+public:
+    VlReadMem(bool hex, int bits, const std::string& filename, QData start, QData end);
+    ~VlReadMem();
+    bool isOpen() const { return m_fp != NULL; }
+    int linenum() const { return m_linenum; }
+    bool get(QData& addrr, std::string& valuer);
+    void setData(void* valuep, const std::string& rhs);
+};
+
+class VlWriteMem {
+    int m_bits;  // Bit width of values
+    FILE* m_fp;  // File handle for filename
+    QData m_addr;  // Next address to write
+public:
+    VlWriteMem(bool hex, int bits, const std::string& filename, QData start, QData end);
+    ~VlWriteMem();
+    bool isOpen() const { return m_fp != NULL; }
+    void print(QData addr, bool addrstamp, const void* valuep);
+};
 
 //===================================================================
 // Verilog array container
@@ -72,6 +100,10 @@ VlWide<T_Words>& VL_CVT_W_A(WDataInP inp, const VlWide<T_Words>&) {
     return *((VlWide<T_Words>*)inp);
 }
 
+template <std::size_t T_Words>
+std::string VL_TO_STRING(const VlWide<T_Words>& obj) {
+    return VL_TO_STRING_W(T_Words, obj.data());
+}
 
 //===================================================================
 // Verilog associative array container
@@ -126,7 +158,7 @@ public:
     int next(T_Key& indexr) const {
         typename Map::const_iterator it = m_map.find(indexr);
         if (VL_UNLIKELY(it == m_map.end())) return 0;
-        it++;
+        ++it;
         if (VL_UNLIKELY(it == m_map.end())) return 0;
         indexr = it->first;
         return 1;
@@ -180,12 +212,42 @@ std::string VL_TO_STRING(const VlAssocArray<T_Key, T_Value>& obj) {
     return obj.to_string();
 }
 
+template <class T_Key, class T_Value>
+void VL_READMEM_N(bool hex, int bits, const std::string& filename,
+                  VlAssocArray<T_Key, T_Value>& obj, QData start, QData end) VL_MT_SAFE {
+    VlReadMem rmem(hex, bits, filename, start, end);
+    if (VL_UNLIKELY(!rmem.isOpen())) return;
+    while (true) {
+        QData addr;
+        std::string data;
+        if (rmem.get(addr /*ref*/, data /*ref*/)) {
+            rmem.setData(&(obj.at(addr)), data);
+        } else {
+            break;
+        }
+    }
+}
+
+template <class T_Key, class T_Value>
+void VL_WRITEMEM_N(bool hex, int bits, const std::string& filename,
+                   const VlAssocArray<T_Key, T_Value>& obj, QData start, QData end) VL_MT_SAFE {
+    VlWriteMem wmem(hex, bits, filename, start, end);
+    if (VL_UNLIKELY(!wmem.isOpen())) return;
+    for (typename VlAssocArray<T_Key, T_Value>::const_iterator it = obj.begin(); it != obj.end();
+         ++it) {
+        QData addr = it->first;
+        if (addr >= start && addr <= end) wmem.print(addr, true, &(it->second));
+    }
+}
+
 //===================================================================
-// Verilog queue container
+// Verilog queue and dynamic array container
 // There are no multithreaded locks on this; the base variable must
 // be protected by other means
 //
-template <class T_Value> class VlQueue {
+// Bound here is the maximum size() allowed, e.g. 1 + SystemVerilog bound
+// For dynamic arrays it is always zero
+template <class T_Value, size_t T_MaxSize = 0> class VlQueue {
 private:
     // TYPES
     typedef std::deque<T_Value> Deque;
@@ -214,10 +276,30 @@ public:
     void clear() { m_deque.clear(); }
     void erase(size_t index) { if (VL_LIKELY(index < m_deque.size())) m_deque.erase(index); }
 
+    // Dynamic array new[] becomes a renew()
+    void renew(size_t size) {
+        clear();
+        m_deque.resize(size, atDefault());
+    }
+    // Dynamic array new[]() becomes a renew_copy()
+    void renew_copy(size_t size, const VlQueue<T_Value,T_MaxSize>& rhs) {
+        if (size == 0) {
+            clear();
+        } else {
+            *this = rhs;
+            m_deque.resize(size, atDefault());
+        }
+    }
+
     // function void q.push_front(value)
-    void push_front(const T_Value& value) { m_deque.push_front(value); }
+    void push_front(const T_Value& value) {
+        m_deque.push_front(value);
+        if (VL_UNLIKELY(T_MaxSize != 0 && m_deque.size() > T_MaxSize)) m_deque.pop_back();
+    }
     // function void q.push_back(value)
-    void push_back(const T_Value& value) { m_deque.push_back(value); }
+    void push_back(const T_Value& value) {
+        if (VL_LIKELY(T_MaxSize == 0 || m_deque.size() < T_MaxSize)) m_deque.push_back(value);
+    }
     // function value_t q.pop_front();
     T_Value pop_front() {
         if (m_deque.empty()) return m_defaultValue;
@@ -234,6 +316,7 @@ public:
     // because we need to be able to insert only when the value is set
     T_Value& at(size_t index) {
         static T_Value s_throwAway;
+        // Needs to work for dynamic arrays, so does not use T_MaxSize
         if (VL_UNLIKELY(index >= m_deque.size())) {
             s_throwAway = atDefault();
             return s_throwAway;
@@ -243,6 +326,7 @@ public:
     // Accessing. Verilog: v = assoc[index]
     const T_Value& at(size_t index) const {
         static T_Value s_throwAway;
+        // Needs to work for dynamic arrays, so does not use T_MaxSize
         if (VL_UNLIKELY(index >= m_deque.size())) return atDefault();
         else return m_deque[index];
     }
@@ -278,14 +362,14 @@ std::string VL_TO_STRING(const VlQueue<T_Value>& obj) {
 
 extern std::string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp) VL_MT_SAFE;
 inline std::string VL_CVT_PACK_STR_NQ(QData lhs) VL_PURE {
-    WData lw[2];  VL_SET_WQ(lw, lhs);
-    return VL_CVT_PACK_STR_NW(2, lw);
+    WData lw[VL_WQ_WORDS_E]; VL_SET_WQ(lw, lhs);
+    return VL_CVT_PACK_STR_NW(VL_WQ_WORDS_E, lw);
 }
 inline std::string VL_CVT_PACK_STR_NN(const std::string& lhs) VL_PURE {
     return lhs;
 }
 inline std::string VL_CVT_PACK_STR_NI(IData lhs) VL_PURE {
-    WData lw[1];  lw[0] = lhs;
+    WData lw[VL_WQ_WORDS_E];  VL_SET_WI(lw, lhs);
     return VL_CVT_PACK_STR_NW(1, lw);
 }
 inline std::string VL_CONCATN_NNN(const std::string& lhs, const std::string& rhs) VL_PURE {
@@ -298,7 +382,7 @@ inline std::string VL_REPLICATEN_NNQ(int,int,int, const std::string& lhs, IData
 }
 inline std::string VL_REPLICATEN_NNI(int obits,int lbits,int rbits,
                                      const std::string& lhs, IData rep) VL_PURE {
-    return VL_REPLICATEN_NNQ(obits,lbits,rbits,lhs,rep);
+    return VL_REPLICATEN_NNQ(obits, lbits, rbits, lhs, rep);
 }
 
 inline IData VL_LEN_IN(const std::string& ld) { return ld.length(); }
@@ -306,12 +390,12 @@ extern std::string VL_TOLOWER_NN(const std::string& ld);
 extern std::string VL_TOUPPER_NN(const std::string& ld);
 
 extern IData VL_FOPEN_NI(const std::string& filename, IData mode) VL_MT_SAFE;
-extern void VL_READMEM_N(bool hex, int width, int depth, int array_lsb,
-                         const std::string& filename,
-                         void* memp, IData start, IData end) VL_MT_SAFE;
-extern void VL_WRITEMEM_N(bool hex, int width, int depth, int array_lsb,
-                          const std::string& filename,
-                          const void* memp, IData start, IData end) VL_MT_SAFE;
+extern void VL_READMEM_N(bool hex, int bits, QData depth, int array_lsb,
+                         const std::string& filename, void* memp, QData start,
+                         QData end) VL_MT_SAFE;
+extern void VL_WRITEMEM_N(bool hex, int bits, QData depth, int array_lsb,
+                          const std::string& filename, const void* memp, QData start,
+                          QData end) VL_MT_SAFE;
 extern IData VL_SSCANF_INX(int lbits, const std::string& ld,
                            const char* formatp, ...) VL_MT_SAFE;
 extern void VL_SFORMAT_X(int obits_ignored, std::string& output,
@@ -320,18 +404,18 @@ extern std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE;
 extern IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_MT_SAFE;
 inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, CData& rdr) VL_MT_SAFE {
     WData rwp[2];  // WData must always be at least 2
-    IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp);
+    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
     if (got) rdr = rwp[0];
     return got;
 }
 inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, SData& rdr) VL_MT_SAFE {
     WData rwp[2];  // WData must always be at least 2
-    IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp);
+    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
     if (got) rdr = rwp[0];
     return got;
 }
 inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, IData& rdr) VL_MT_SAFE {
-    WData rwp[2];  // WData must always be at least 2
+    WData rwp[2];
     IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
     if (got) rdr = rwp[0];
     return got;
@@ -344,10 +428,37 @@ inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, QData& rdr)
 }
 inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, double& rdr) VL_MT_SAFE {
     WData rwp[2];
-    IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp);
+    IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp);
     if (got) rdr = VL_CVT_D_Q(VL_SET_QW(rwp));
     return got;
 }
 extern IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE;
 
+//======================================================================
+// Strings
+
+extern std::string VL_PUTC_N(const std::string& lhs, IData rhs, CData ths) VL_PURE;
+extern CData VL_GETC_N(const std::string& lhs, IData rhs) VL_PURE;
+extern std::string VL_SUBSTR_N(const std::string& lhs, IData rhs, IData ths) VL_PURE;
+
+inline IData VL_CMP_NN(const std::string& lhs, const std::string& rhs, bool ignoreCase) VL_PURE {
+    // SystemVerilog does not allow a string variable to contain '\0'.
+    // So C functions such as strcmp() can correctly compare strings.
+    int result;
+    if (ignoreCase) {
+        result = VL_STRCASECMP(lhs.c_str(), rhs.c_str());
+    } else {
+        result = std::strcmp(lhs.c_str(), rhs.c_str());
+    }
+    return result;
+}
+
+extern IData VL_ATOI_N(const std::string& str, int base) VL_PURE;
+
+//======================================================================
+// Dumping
+
+extern const char* vl_dumpctl_filenamep(bool setit = false,
+                                        const std::string& filename = "") VL_MT_SAFE;
+
 #endif  // Guard

include/verilated_imp.h

@@ -1,15 +1,11 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //*************************************************************************
 //
-// Copyright 2009-2019 by Wilson Snyder. This program is free software; you can
+// Copyright 2009-2020 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License.
+// Lesser General Public License Version 3 or the Perl Artistic License
 // Version 2.0.
-//
-// Verilator is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=========================================================================
 ///

include/verilated_save.cpp

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2001-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2001-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///
@@ -187,7 +184,7 @@ void VerilatedSave::flush() VL_MT_UNSAFE_ONE {
     m_assertOne.check();
     if (VL_UNLIKELY(!isOpen())) return;
     vluint8_t* wp = m_bufp;
-    while (1) {
+    while (true) {
         ssize_t remaining = (m_cp - wp);
         if (remaining==0) break;
         errno = 0;
@@ -216,7 +213,7 @@ void VerilatedRestore::fill() VL_MT_UNSAFE_ONE {
     m_endp = m_bufp + (m_endp - m_cp);
     m_cp = m_bufp;  // Reset buffer
     // Read into buffer starting at m_endp
-    while (1) {
+    while (true) {
         ssize_t remaining = (m_bufp+bufferSize() - m_endp);
         if (remaining==0) break;
         errno = 0;

include/verilated_save.h

@@ -3,14 +3,11 @@
 //
 // THIS MODULE IS PUBLICLY LICENSED
 //
-// Copyright 2012-2019 by Wilson Snyder.  This program is free software;
-// you can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
-//
-// This is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// for more details.
+// Copyright 2000-2020 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //=============================================================================
 ///
@@ -35,14 +32,14 @@ class VerilatedSerialize {
 protected:
     // MEMBERS
     // For speed, keep m_cp as the first member of this structure
-    vluint8_t*          m_cp;           ///< Current pointer into m_bufp buffer
-    vluint8_t*          m_bufp;         ///< Output buffer
-    bool                m_isOpen;       ///< True indicates open file/stream
-    std::string         m_filename;     ///< Filename, for error messages
+    vluint8_t* m_cp;  ///< Current pointer into m_bufp buffer
+    vluint8_t* m_bufp;  ///< Output buffer
+    bool m_isOpen;  ///< True indicates open file/stream
+    std::string m_filename;  ///< Filename, for error messages
     VerilatedAssertOneThread m_assertOne;  ///< Assert only called from single thread
 
-    inline static size_t bufferSize() { return 256*1024; }  // See below for slack calculation
-    inline static size_t bufferInsertSize() { return 16*1024; }
+    inline static size_t bufferSize() { return 256 * 1024; }  // See below for slack calculation
+    inline static size_t bufferInsertSize() { return 16 * 1024; }
 
     void header() VL_MT_UNSAFE_ONE;
     void trailer() VL_MT_UNSAFE_ONE;
@@ -94,15 +91,15 @@ class VerilatedDeserialize {
 protected:
     // MEMBERS
     // For speed, keep m_cp as the first member of this structure
-    vluint8_t*          m_cp;           ///< Current pointer into m_bufp buffer
-    vluint8_t*          m_bufp;         ///< Output buffer
-    vluint8_t*          m_endp;         ///< Last valid byte in m_bufp buffer
-    bool                m_isOpen;       ///< True indicates open file/stream
-    std::string         m_filename;     ///< Filename, for error messages
-    VerilatedAssertOneThread m_assertOne;       ///< Assert only called from single thread
+    vluint8_t* m_cp;  ///< Current pointer into m_bufp buffer
+    vluint8_t* m_bufp;  ///< Output buffer
+    vluint8_t* m_endp;  ///< Last valid byte in m_bufp buffer
+    bool m_isOpen;  ///< True indicates open file/stream
+    std::string m_filename;  ///< Filename, for error messages
+    VerilatedAssertOneThread m_assertOne;  ///< Assert only called from single thread
 
-    inline static size_t bufferSize() { return 256*1024; }  // See below for slack calculation
-    inline static size_t bufferInsertSize() { return 16*1024; }
+    inline static size_t bufferSize() { return 256 * 1024; }  // See below for slack calculation
+    inline static size_t bufferInsertSize() { return 16 * 1024; }
 
     virtual void fill() = 0;
     void header() VL_MT_UNSAFE_ONE;
@@ -164,12 +161,12 @@ private:
 public:
     // CONSTRUCTORS
     VerilatedSave() { m_fd = -1; }
-    virtual ~VerilatedSave() { close(); }
+    virtual ~VerilatedSave() VL_OVERRIDE { close(); }
     // METHODS
     void open(const char* filenamep) VL_MT_UNSAFE_ONE;  ///< Open the file; call isOpen() to see if errors
     void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); }
-    virtual void close() VL_MT_UNSAFE_ONE;
-    virtual void flush() VL_MT_UNSAFE_ONE;
+    virtual void close() VL_OVERRIDE VL_MT_UNSAFE_ONE;
+    virtual void flush() VL_OVERRIDE VL_MT_UNSAFE_ONE;
 };
 
 //=============================================================================
@@ -183,68 +180,68 @@ private:
 public:
     // CONSTRUCTORS
     VerilatedRestore() { m_fd = -1; }
-    virtual ~VerilatedRestore() { close(); }
+    virtual ~VerilatedRestore() VL_OVERRIDE { close(); }
 
     // METHODS
     void open(const char* filenamep) VL_MT_UNSAFE_ONE;  ///< Open the file; call isOpen() to see if errors
     void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); }
-    virtual void close() VL_MT_UNSAFE_ONE;
-    virtual void flush() VL_MT_UNSAFE_ONE {}
-    virtual void fill() VL_MT_UNSAFE_ONE;
+    virtual void close() VL_OVERRIDE VL_MT_UNSAFE_ONE;
+    virtual void flush() VL_OVERRIDE VL_MT_UNSAFE_ONE {}
+    virtual void fill() VL_OVERRIDE VL_MT_UNSAFE_ONE;
 };
 
 //=============================================================================
 
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   vluint64_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint64_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
-inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint64_t& rhs){
+inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint64_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   vluint32_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint32_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint32_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   vluint16_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint16_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint16_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   vluint8_t& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, vluint8_t& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint8_t& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   bool& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, bool& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, bool& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   double& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, double& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, double& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   float& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, float& rhs) {
     return os.write(&rhs, sizeof(rhs));
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, float& rhs) {
     return os.read(&rhs, sizeof(rhs));
 }
-inline VerilatedSerialize&   operator<<(VerilatedSerialize& os,   std::string& rhs) {
+inline VerilatedSerialize& operator<<(VerilatedSerialize& os, std::string& rhs) {
     vluint32_t len = rhs.length();
-    os<<len;
+    os << len;
     return os.write(rhs.data(), len);
 }
 inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, std::string& rhs) {
     vluint32_t len = 0;
-    os>>len;
+    os >> len;
     rhs.resize(len);
     return os.read((void*)rhs.data(), len);
 }