Commentary

src/verilog.y

@@ -1664,6 +1664,7 @@ member_decl_assignment<memberp>:	// Derived from IEEE: variable_decl_assignment
                           }
 	|	id variable_dimensionListE '=' variable_declExpr
 			{ $4->v3error("Unsupported: Initial values in struct/union members.");
+			  // But still need error if packed according to IEEE 7.2.2
 			  $$ = NULL; }
 	|	idSVKwd					{ $$ = NULL; }
 	//

test_regress/t/t_typedef.v

@@ -7,6 +7,8 @@
 program t;
    parameter SIZE = 5;
 
+   typedef vec_t;  // Forward
+
    typedef reg [SIZE-1:0] vec_t ;
    vec_t a; initial a =0;