No assign alias for unpacked public variables (#2089)
Public variables are all emitted in the C code and unpacked arrays arrays are sliced up for this. After inlining public unpacked array assignments should not be alias assignments but actual assignments, so that they are sliced and hence emitted properly. Fixes #2073
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@ -322,6 +322,15 @@ private:
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new AstAssignW(nodep->fileline(),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), true),
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new AstVarRef(nodep->fileline(), nodep, false)));
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} else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) {
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// Public variable at this end and it is an unpacked array. We need to assign
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// instead of aliased, because otherwise it will pass V3Slice and invalid
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// code will be emitted.
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UINFO(9,"assign to public and unpacked: "<<nodep<<endl);
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m_modp->addStmtp(
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new AstAssignW(nodep->fileline(),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), true),
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new AstVarRef(nodep->fileline(), nodep, false)));
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} else if (nodep->isIfaceRef()) {
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m_modp->addStmtp(
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new AstAssignVarScope(nodep->fileline(),
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@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ["--public-flat-rw"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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@ -0,0 +1,21 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Stefan Wallentowitz
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module t();
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logic din [0:15];
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array_test array_test_inst(.din(din));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module array_test(
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input din [0:15]
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);
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endmodule
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