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Tests: Add two-design trace tests.

This commit is contained in:
Wilson Snyder 2020-02-29 09:44:51 -05:00
parent a7bd934fe3
commit 082c9e0b1d
11 changed files with 556 additions and 14 deletions
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2
test_regress/driver.pl
View File

@ -1742,7 +1742,7 @@ sub _print_advance_time {
if ($self->sc) {
print $fh "#if (SYSTEMC_VERSION>=20070314)\n";
print $fh " sc_start(${time},SC_NS);\n";
print $fh " sc_start(${time}, SC_NS);\n";
print $fh "#else\n";
print $fh " sc_start(${time});\n";
print $fh "#endif\n";

2
test_regress/t/t_mem_multi_io2.cpp
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@ -48,7 +48,7 @@ int main()
// loop through every possibility and check the result
#ifdef SYSTEMC_VERSION
sc_start(1,SC_NS);
sc_start(1, SC_NS);
# define ASSIGN(s,v) s.write(v)
# define READ(s) s.read()
#else

24
test_regress/t/t_trace_ena.v
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@ -15,7 +15,7 @@ module t (/*AUTOARG*/
integer b_trace_off;
// verilator tracing_on
integer c_trace_on;
real r;
real r;
// verilator tracing_off
sub sub ();
@ -23,17 +23,17 @@ module t (/*AUTOARG*/
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
b_trace_off <= cyc;
c_trace_on <= b_trace_off;
r <= r + 0.1;
if (cyc==4) begin
if (c_trace_on != 2) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
cyc <= cyc + 1;
b_trace_off <= cyc;
c_trace_on <= b_trace_off;
r <= r + 0.1;
if (cyc==4) begin
if (c_trace_on != 2) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end

33
test_regress/t/t_trace_two_a.v Normal file
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@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer c_trace_on;
sub sub ();
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
c_trace_on <= cyc + 2;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub;
integer inside_sub_a = 1;
endmodule

28
test_regress/t/t_trace_two_b.v Normal file
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@ -0,0 +1,28 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer c_trace_on;
real r;
sub sub ();
always @ (posedge clk) begin
if (cyc!=0) begin
r <= r + 0.1;
end
end
endmodule
module sub;
integer inside_sub_a = 2;
endmodule

70
test_regress/t/t_trace_two_cc.cpp Normal file
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@ -0,0 +1,70 @@
// DESCRIPTION: Verilator: Verilog Test
//
// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
#include "verilatedos.h"
#include VM_PREFIX_INCLUDE
#include "Vt_trace_two_b.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
// Compile in place
#include "Vt_trace_two_b.cpp"
#include "Vt_trace_two_b__Syms.cpp"
#include "Vt_trace_two_b__Trace.cpp"
#include "Vt_trace_two_b__Trace__Slow.cpp"
VM_PREFIX* ap;
Vt_trace_two_b* bp;
vluint64_t main_time = 0;
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) {
double sim_time = 1100;
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
srand48(5);
ap = new VM_PREFIX("topa");
bp = new Vt_trace_two_b("topb");
ap->eval();
bp->eval();
#if VM_TRACE
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
ap->trace(tfp, 99);
bp->trace(tfp, 99);
tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
if (tfp) tfp->dump(main_time);
#endif
{
ap->clk = false;
ap->clk = false;
main_time += 10;
}
while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
ap->clk = !ap->clk;
bp->clk = ap->clk;
ap->eval();
bp->eval();
#if VM_TRACE
if (tfp) tfp->dump(main_time);
#endif // VM_TRACE
main_time += 5;
}
if (!Verilated::gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
}
ap->final();
bp->final();
#if VM_TRACE
if (tfp) tfp->close();
#endif // VM_TRACE
VL_DO_DANGLING(delete ap, ap);
VL_DO_DANGLING(delete bp, bp);
exit(0L);
}

128
test_regress/t/t_trace_two_cc.out Normal file
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@ -0,0 +1,128 @@
$version Generated by VerilatedVcd $end
$date Sat Feb 29 09:09:40 2020
$end
$timescale 1ns $end
$scope module topa $end
$var wire 1 3 clk $end
$scope module t $end
$var wire 32 + c_trace_on [31:0] $end
$var wire 1 3 clk $end
$var wire 32 # cyc [31:0] $end
$scope module sub $end
$var wire 32 ; inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$var wire 1 N clk $end
$scope module t $end
$var wire 32 ^ c_trace_on [31:0] $end
$var wire 1 N clk $end
$var wire 32 V cyc [31:0] $end
$var real 64 > r $end
$scope module sub $end
$var wire 32 f inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b00000000000000000000000000000001 #
b00000000000000000000000000000000 +
03
b00000000000000000000000000000001 ;
r0 >
0N
b00000000000000000000000000000001 V
b00000000000000000000000000000000 ^
b00000000000000000000000000000010 f
#10
b00000000000000000000000000000010 #
b00000000000000000000000000000011 +
13
r0.1 >
1N
#15
03
0N
#20
b00000000000000000000000000000011 #
b00000000000000000000000000000100 +
13
r0.2 >
1N
#25
03
0N
#30
b00000000000000000000000000000100 #
b00000000000000000000000000000101 +
13
r0.3 >
1N
#35
03
0N
#40
b00000000000000000000000000000101 #
b00000000000000000000000000000110 +
13
r0.4 >
1N
#45
03
0N
#50
b00000000000000000000000000000110 #
b00000000000000000000000000000111 +
13
r0.5 >
1N
#55
03
0N
#60
b00000000000000000000000000000111 #
b00000000000000000000000000001000 +
13
r0.6 >
1N
#65
03
0N
#70
b00000000000000000000000000001000 #
b00000000000000000000000000001001 +
13
r0.7 >
1N
#75
03
0N
#80
b00000000000000000000000000001001 #
b00000000000000000000000000001010 +
13
r0.7999999999999999 >
1N
#85
03
0N
#90
b00000000000000000000000000001010 #
b00000000000000000000000000001011 +
13
r0.8999999999999999 >
1N
#95
03
0N
#100
b00000000000000000000000000001011 #
b00000000000000000000000000001100 +
13
r0.9999999999999999 >
1N

39
test_regress/t/t_trace_two_cc.pl Executable file
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@ -0,0 +1,39 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# Test tracing with two models instanced
scenarios(vlt_all => 1);
top_filename("t_trace_two_a.v");
compile(
make_main => 0,
verilator_make_gmake => 0,
top_filename => 't_trace_two_b.v',
VM_PREFIX => 'Vt_trace_two_b',
verilator_flags2 => ['-trace'],
);
compile(
make_main => 0,
top_filename => 't_trace_two_a.v',
verilator_flags2 => ['-exe', '-trace', "$Self->{t_dir}/t_trace_two_cc.cpp"],
);
execute(
check_finished => 1,
);
if ($Self->{vlt_all}) {
file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
}
ok(1);
1;

74
test_regress/t/t_trace_two_sc.cpp Normal file
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@ -0,0 +1,74 @@
// DESCRIPTION: Verilator: Verilog Test
//
// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
#include "verilatedos.h"
#include VM_PREFIX_INCLUDE
#include "Vt_trace_two_b.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
// Compile in place
#include "Vt_trace_two_b.cpp"
#include "Vt_trace_two_b__Syms.cpp"
#include "Vt_trace_two_b__Trace.cpp"
#include "Vt_trace_two_b__Trace__Slow.cpp"
// General headers
#include "verilated.h"
#include "systemc.h"
#include "verilated_vcd_sc.h"
VM_PREFIX* ap;
Vt_trace_two_b* bp;
int sc_main(int argc, char** argv) {
sc_signal<bool> clk;
sc_time sim_time(1100, SC_NS);
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
srand48(5);
ap = new VM_PREFIX("topa");
bp = new Vt_trace_two_b("topb");
ap->clk(clk);
bp->clk(clk);
#if VM_TRACE
Verilated::traceEverOn(true);
VerilatedVcdSc* tfp = new VerilatedVcdSc;
ap->trace(tfp, 99);
bp->trace(tfp, 99);
tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
#endif
{
clk = false;
#if (SYSTEMC_VERSION>=20070314)
sc_start(10, SC_NS);
#else
sc_start(10);
#endif
}
while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
clk = !clk;
#if (SYSTEMC_VERSION>=20070314)
sc_start(5, SC_NS);
#else
sc_start(5);
#endif
}
if (!Verilated::gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
}
ap->final();
bp->final();
#if VM_TRACE
if (tfp) tfp->close();
#endif // VM_TRACE
VL_DO_DANGLING(delete ap, ap);
VL_DO_DANGLING(delete bp, bp);
exit(0L);
}

126
test_regress/t/t_trace_two_sc.out Normal file
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@ -0,0 +1,126 @@
$version Generated by VerilatedVcd $end
$date Sat Feb 29 09:18:19 2020
$end
$timescale 1ps $end
$scope module topa $end
$scope module t $end
$var wire 32 3 c_trace_on [31:0] $end
$var wire 1 # clk $end
$var wire 32 + cyc [31:0] $end
$scope module sub $end
$var wire 32 ; inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
$scope module t $end
$var wire 32 ^ c_trace_on [31:0] $end
$var wire 1 > clk $end
$var wire 32 V cyc [31:0] $end
$var real 64 F r $end
$scope module sub $end
$var wire 32 f inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
b00000000000000000000000000000001 +
b00000000000000000000000000000000 3
b00000000000000000000000000000001 ;
0>
r0 F
b00000000000000000000000000000001 V
b00000000000000000000000000000000 ^
b00000000000000000000000000000010 f
#10000
1#
b00000000000000000000000000000010 +
b00000000000000000000000000000011 3
1>
r0.1 F
#15000
0#
0>
#20000
1#
b00000000000000000000000000000011 +
b00000000000000000000000000000100 3
1>
r0.2 F
#25000
0#
0>
#30000
1#
b00000000000000000000000000000100 +
b00000000000000000000000000000101 3
1>
r0.3 F
#35000
0#
0>
#40000
1#
b00000000000000000000000000000101 +
b00000000000000000000000000000110 3
1>
r0.4 F
#45000
0#
0>
#50000
1#
b00000000000000000000000000000110 +
b00000000000000000000000000000111 3
1>
r0.5 F
#55000
0#
0>
#60000
1#
b00000000000000000000000000000111 +
b00000000000000000000000000001000 3
1>
r0.6 F
#65000
0#
0>
#70000
1#
b00000000000000000000000000001000 +
b00000000000000000000000000001001 3
1>
r0.7 F
#75000
0#
0>
#80000
1#
b00000000000000000000000000001001 +
b00000000000000000000000000001010 3
1>
r0.7999999999999999 F
#85000
0#
0>
#90000
1#
b00000000000000000000000000001010 +
b00000000000000000000000000001011 3
1>
r0.8999999999999999 F
#95000
0#
0>
#100000
1#
b00000000000000000000000000001011 +
b00000000000000000000000000001100 3
1>
r0.9999999999999999 F

44
test_regress/t/t_trace_two_sc.pl Executable file
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@ -0,0 +1,44 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(simulator => 1);
if (!$Self->have_sc) {
skip("No SystemC installed");
}
else {
top_filename("t_trace_two_a.v");
compile(
make_main => 0,
verilator_make_gmake => 0,
top_filename => 't_trace_two_b.v',
VM_PREFIX => 'Vt_trace_two_b',
verilator_flags2 => ['-sc -trace'],
);
compile(
make_main => 0,
top_filename => 't_trace_two_a.v',
verilator_flags2 => ['-sc', '-exe', '-trace',
"$Self->{t_dir}/t_trace_two_sc.cpp"],
);
execute(
check_finished => 1,
);
if ($Self->{vlt_all}) {
file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
}
}
ok(1);
1;