Add lint check for bad enum 4-state values.

This commit is contained in:
Wilson Snyder 2019-12-08 22:26:54 -05:00
parent 700f2072c0
commit 62b0d15d2e
4 changed files with 54 additions and 2 deletions

View File

@ -1452,6 +1452,8 @@ private:
if (!itemp->valuep()) {
if (num.isEqZero() && itemp != nodep->itemsp())
itemp->v3error("Enum value illegally wrapped around (IEEE 2017 6.19)");
if (num.isFourState())
itemp->v3error("Enum value that is unassigned cannot follow value with X/Zs (IEEE 2017 6.19)");
if (!nodep->dtypep()->basicp()
&& !nodep->dtypep()->basicp()->keyword().isIntNumeric()) {
itemp->v3error("Enum names without values only allowed on numeric types");
@ -1459,7 +1461,12 @@ private:
}
itemp->valuep(new AstConst(itemp->fileline(), num));
}
num.opAssign(VN_CAST(itemp->valuep(), Const)->num());
AstConst* constp = VN_CAST(itemp->valuep(), Const);
if (constp->num().isFourState() && nodep->dtypep()->basicp()
&& !nodep->dtypep()->basicp()->isFourstate())
itemp->v3error("Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 2019 6.19)");
num.opAssign(constp->num());
// Look for duplicates
if (inits.find(num) != inits.end()) { // IEEE says illegal
AstNode* otherp = inits.find(num)->second;
@ -1471,7 +1478,7 @@ private:
} else {
inits.insert(make_pair(num, itemp));
}
num.opAdd(one, VN_CAST(itemp->valuep(), Const)->num());
num.opAdd(one, constp->num());
}
}
virtual void visit(AstEnumItem* nodep) {

View File

@ -0,0 +1,9 @@
%Error: t/t_enum_x_bad.v:8: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 2019 6.19)
: ... In instance t
enum bit [1:0] { BADX = 2'b1x } BAD1;
^~~~
%Error: t/t_enum_x_bad.v:11: Enum value that is unassigned cannot follow value with X/Zs (IEEE 2017 6.19)
: ... In instance t
e1
^~
%Error: Exiting due to

18
test_regress/t/t_enum_x_bad.pl Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

View File

@ -0,0 +1,18 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
enum bit [1:0] { BADX = 2'b1x } BAD1;
enum logic [3:0] { e0 = 4'b1xx1,
e1
} BAD2;
initial begin
$stop;
end
endmodule