Add lint check for bad enum 4-state values.
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@ -1452,6 +1452,8 @@ private:
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if (!itemp->valuep()) {
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if (num.isEqZero() && itemp != nodep->itemsp())
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itemp->v3error("Enum value illegally wrapped around (IEEE 2017 6.19)");
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if (num.isFourState())
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itemp->v3error("Enum value that is unassigned cannot follow value with X/Zs (IEEE 2017 6.19)");
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if (!nodep->dtypep()->basicp()
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&& !nodep->dtypep()->basicp()->keyword().isIntNumeric()) {
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itemp->v3error("Enum names without values only allowed on numeric types");
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@ -1459,7 +1461,12 @@ private:
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}
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itemp->valuep(new AstConst(itemp->fileline(), num));
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}
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num.opAssign(VN_CAST(itemp->valuep(), Const)->num());
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AstConst* constp = VN_CAST(itemp->valuep(), Const);
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if (constp->num().isFourState() && nodep->dtypep()->basicp()
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&& !nodep->dtypep()->basicp()->isFourstate())
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itemp->v3error("Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 2019 6.19)");
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num.opAssign(constp->num());
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// Look for duplicates
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if (inits.find(num) != inits.end()) { // IEEE says illegal
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AstNode* otherp = inits.find(num)->second;
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@ -1471,7 +1478,7 @@ private:
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} else {
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inits.insert(make_pair(num, itemp));
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}
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num.opAdd(one, VN_CAST(itemp->valuep(), Const)->num());
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num.opAdd(one, constp->num());
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}
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}
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virtual void visit(AstEnumItem* nodep) {
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@ -0,0 +1,9 @@
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%Error: t/t_enum_x_bad.v:8: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 2019 6.19)
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: ... In instance t
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enum bit [1:0] { BADX = 2'b1x } BAD1;
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^~~~
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%Error: t/t_enum_x_bad.v:11: Enum value that is unassigned cannot follow value with X/Zs (IEEE 2017 6.19)
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: ... In instance t
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e1
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^~
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%Error: Exiting due to
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@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(linter => 1);
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lint(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -0,0 +1,18 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/);
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enum bit [1:0] { BADX = 2'b1x } BAD1;
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enum logic [3:0] { e0 = 4'b1xx1,
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e1
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} BAD2;
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initial begin
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$stop;
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end
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endmodule
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