Fix `pragma pedantic check to work with -E.

src/V3ParseImp.cpp

@@ -73,15 +73,6 @@ V3ParseImp::~V3ParseImp() {
 //######################################################################
 // Parser utility methods
 
-void V3ParseImp::pragma(const char* textp) {
-    // Handle `pragma directive
-    if (0 == strncmp(textp, "`pragma", strlen("`pragma"))) textp += strlen("`pragma");
-    while (isspace(*textp)) ++textp;
-    if (!*textp) {
-        if (v3Global.opt.pedantic()) yyerrorf("`pragma is missing a pragma_expression.");
-    }
-}
-
 void V3ParseImp::ppline(const char* textp) {
     // Handle `line directive
     FileLine* prevFl = copyOrSameFileLine();

src/V3ParseImp.h

@@ -146,7 +146,6 @@ public:
     static bool optFuture(const string& flag) { return v3Global.opt.isFuture(flag); }
 
     void ppline(const char* textp);
-    void pragma(const char* textp);
     void linenoInc() { fileline()->linenoInc(); }
     void verilatorCmtLint(const char* textp, bool on);
     void verilatorCmtLintSave();

src/V3PreLex.l

@@ -106,6 +106,13 @@ bom             [\357\273\277]
 <INITIAL>"`undef"       { FL_FWDC; return VP_UNDEF; }
 <INITIAL>"`undefineall" { FL_FWDC; return VP_UNDEFINEALL; }
 <INITIAL>"`error"       { FL_FWDC; if (!pedantic()) return VP_ERROR; else return VP_DEFREF; }
+<INITIAL>"`pragma"{wsn}*[^\n\r]*  { FL_FWDC;
+                          const char* pointp = yytext + strlen("`pragma");
+                          while (isspace(*pointp)) ++pointp;
+                          if (!*pointp && v3Global.opt.pedantic()) {
+                              yyerrorf("`pragma is missing a pragma_expression.");
+                          }
+                          return VP_TEXT; }
 <INITIAL,STRIFY>"`__FILE__"     { FL_FWDC;
                           static string rtnfile;
                           rtnfile = '"'; rtnfile += LEXP->curFilelinep()->filename();

src/verilog.l

@@ -954,7 +954,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "`nosuppress_faults"                  { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`nounconnected_drive"                { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`portcoerce"                         { FL_FWD; FL_BRK; }
-  "`pragma"{ws}*[^\n\r]*                { FL_FWD; PARSEP->pragma(yytext); FL_BRK; }  // Verilog 2005
+  "`pragma"{ws}*[^\n\r]*                { FL_FWD; FL_BRK; }  // Verilog 2005
   "`protect"                            { FL_FWD; FL_BRK; }
   "`remove_gatenames"                   { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`remove_netnames"                    { FL_FWD; FL_BRK; }  // Verilog-XL compatibility

test_regress/t/t_pp_pragma_bad.out

@@ -1,7 +1,15 @@
 %Error: t/t_pp_pragma_bad.v:6: `pragma is missing a pragma_expression.
 `pragma
 ^~~~~~~
-%Error: t/t_pp_pragma_bad.v:10: syntax error, unexpected `resetall
-`resetall   
-^~~~~~~~~
-%Error: Cannot continue
+`line 1 "t/t_pp_pragma_bad.v" 1
+ 
+
+`line 3 "t/t_pp_pragma_bad.v" 0
+ 
+ 
+
+`line 6 "t/t_pp_pragma_bad.v" 0
+`pragma
+
+`line 8 "t/t_pp_pragma_bad.v" 2
+%Error: Exiting due to

test_regress/t/t_pp_pragma_bad.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(linter => 1);
 
 lint(
-    verilator_flags2 => ["-Wpedantic"],
+    verilator_flags2 => ["-E -Wpedantic"],
     fails => 1,
     expect_filename => $Self->{golden_filename},
     );

test_regress/t/t_pp_pragma_bad.v

@@ -4,9 +4,3 @@
 // without warranty, 2019 by Wilson Snyder.
 
 `pragma
-
-`resetall  // Ok
-module t;
-`resetall  // Bad
-endmodule
-`resetall  // Ok

test_regress/t/t_pp_resetall_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_pp_resetall_bad.v:8: syntax error, unexpected `resetall
+`resetall   
+^~~~~~~~~
+%Error: Cannot continue

test_regress/t/t_pp_resetall_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["-Wpedantic"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_pp_resetall_bad.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+`resetall  // Ok
+module t;
+`resetall  // Bad
+endmodule
+`resetall  // Ok