De-tabify

test_regress/t/t_prot_lib.v

@@ -15,14 +15,14 @@ if (cyc > 0 && sig``_in != sig``_out) begin \
        end
 
 module t #(parameter GATED_CLK = 0) (/*AUTOARG*/
-				     // Inputs
-				     clk
-				     );
+                                    // Inputs
+                                    clk
+                                    );
    input clk;
 
    localparam last_cyc =
 `ifdef TEST_BENCHMARK
-			`TEST_BENCHMARK;
+                       `TEST_BENCHMARK;
 `else
    10;
 `endif