Wilson Snyder
b14539569f
Internals: Check and enforce member brace initialization. No functional change intended
2025-08-17 13:20:52 -04:00
Wilson Snyder
7126293086
Support enum.next with a parameter
2025-08-16 21:06:35 -04:00
Wilson Snyder
36c4a24661
Internals: constifyParamsEdit return value was unused. No functional change.
2025-08-16 21:03:12 -04:00
Wilson Snyder
49ca1cfdd7
Commentary
2025-08-16 18:32:40 -04:00
Geza Lore
a300bfc538
Internals: Add AstNodeStmt.h ( #6295 )
...
Move AstNodeStmt and all its subtypes into AstNodeStmt.h.
This is the first step for #6280 .
No functional change
2025-08-16 09:46:18 +01:00
Geza Lore
6f69c990fd
Internals: Remove AstCondBound and AstNodeCond ( #6293 ) ( #6294 )
...
Fixes #6293
2025-08-15 15:49:06 -07:00
Geza Lore
d273e2cbd0
Internals: Do not astgen useless Dfg vertex subtypes
2025-08-15 20:06:58 +01:00
Geza Lore
9c11f5e05d
Fix DFG circular driver tracing
2025-08-15 10:20:20 +01:00
Wilson Snyder
047a12cc62
Fix variables hiding package imports ( #6289 ).
2025-08-13 18:05:37 -04:00
Wilson Snyder
60cbbf0ec1
Add error on mismatching prototypes ( #6207 ).
2025-08-11 19:50:47 -04:00
Geza Lore
762c5f573c
Improve DFG to enable breaking more combinational cycles
2025-08-11 09:44:31 +01:00
Geza Lore
7696b0651c
Internals: Improve DFG dumping functions
2025-08-10 16:48:40 +01:00
Wilson Snyder
eb80db9397
Clarify extern error message
2025-08-10 08:38:26 -04:00
Wilson Snyder
641dd756c0
Add check for mis-assignment of dynamic/automatics per IEEE
2025-08-10 07:23:28 -04:00
Wilson Snyder
a74a3bb689
Internals: No need for 'if' before VL_FFLUSH_I
2025-08-10 06:13:18 -04:00
Geza Lore
d28436dccc
Fix stray ']' in Verilog code output for non-constant select ( #6277 )
2025-08-09 14:59:58 +01:00
Wilson Snyder
3ca1c9b6dd
Internals: Fix and enforce brace new constructors. No functional change intended.
2025-08-08 18:21:12 -04:00
Geza Lore
16d32cdd4a
Internals: Refactor Ast to Dfg conversion for reusability. ( #6276 )
...
This is mainly code motion, with minimal algorithmic changes to
facilitate reusing parts in future code. No functional change intended.
2025-08-08 22:53:12 +01:00
Wilson Snyder
d1f851e1e1
Internals: Optimize empty 'if' into StmtExpr
2025-08-08 05:10:40 -04:00
Wilson Snyder
6a225d5d00
Internals: Remove AstSysFuncAsTask
2025-08-08 05:09:54 -04:00
Artur Bieniek
5b7188fcaf
Fix same variable on the RHS forced to two different LHSs. ( #6269 )
2025-08-06 17:37:00 -04:00
github action
dc049fdd74
Apply 'make format'
2025-08-06 21:30:37 +00:00
Michael Bedford Taylor
218659f4e8
Support parameter resolution of 1D unpacked array slices ( #6257 ) ( #6268 )
2025-08-06 17:29:40 -04:00
Igor Zaworski
6c1cfc68cf
Fix dynamic cast purity ( #6267 )
...
Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
2025-08-06 07:09:44 -04:00
Wilson Snyder
c005486acf
Support by ignoring delay2 on UDPs
2025-08-05 17:34:42 -04:00
Wilson Snyder
6467351752
Add error on class 'function static'.
2025-08-05 17:12:00 -04:00
Wilson Snyder
870c398094
Fix incorrect Non-ANSI I/O declaration conflict error ( #6258 ) broke with #bd1ac038
2025-08-05 16:33:28 -04:00
Geza Lore
86c56e8e14
Fix true cycle detection in DFG
2025-08-05 15:04:07 +01:00
Geza Lore
25d968b833
Fix infinite loop in VString::replaceSubstr
...
If the replaced string was a suffix of the replacement, we used to get
an infinite loop.
2025-08-05 14:41:38 +01:00
Geza Lore
158a54a7ff
Defer deletion of eliminated Ast variables until end of Dfg pass. ( #6263 )
...
This is currently unnecessary but future patch will depend on it.
2025-08-05 14:29:33 +01:00
Geza Lore
8c9a4fec83
Emit memory addresses of vertices in Dfg dumps
2025-08-05 13:03:57 +01:00
Geza Lore
53332ae03e
Unify the two DFG cycle finding algorithms. ( #6262 )
...
Both V3DfgBreakCycles.cpp and V3DfgDecomposition.cpp used to contain an
implementation of the same algorithm to color strongly connected
components. Now there is only one, and it lives in V3DfgColorSCCs.cpp.
2025-08-05 13:03:30 +01:00
Geza Lore
4a5935d248
Merge DFG components made acyclic into the original acyclic sub-graph. ( #6261 )
...
After making a cyclic DFG component acyclic, merge that component back
into the acyclic sub-graph of the input graph. This enables optimizing
through the components that were made acyclic in their larger context.
2025-08-05 12:11:02 +01:00
Geza Lore
78c9e7773a
Allow more variable removal in scoped DFG ( #6260 )
2025-08-05 11:18:33 +01:00
Geza Lore
d2edab458e
Refactor Dfg variable flags ( #6259 )
...
Store all flags in a DfgVertexVar relating to the underlying
AstVar/AstVarScope stored via AstNode::user1(). user2/user3/user4 are
then usable by DFG algorithms as needed.
2025-08-05 10:24:54 +01:00
Geza Lore
d415757b0e
Remove unhelpful DFG debug dumps
2025-08-05 05:06:44 +01:00
Ryszard Rozak
7d2b6bd921
Internals: Optimize updates of Vtogcov signals. No functional change intended. ( #6110 )
2025-08-04 13:29:56 +01:00
Wilson Snyder
52ac3b3a0d
Add error on too many pattern members for structure
2025-08-03 17:26:51 -04:00
Wilson Snyder
f106c1eaec
Fix genvar check to be more strict about generate-for usage only
2025-08-03 16:57:12 -04:00
Wilson Snyder
309129ebcf
Add PARAMNODEFAULT error, for parameters without defaults.
2025-08-03 15:27:37 -04:00
Geza Lore
deed20fb78
Fix partial DFG conversion of concat assignments ( #6255 )
...
When we had a `{a, b} = ...`, and the DFG conversion of `a = ...`
succeeded, but `b = ...` failed, we still used to include `a = ...` in
the DFG, which then caused a spurious multi-driver error for `a` on
a subsequent DFG pass, as the original `{a, b} = ...` was still present
in the Ast, but we also had the extra `a = ...` from converting out of
DFG on the previous pass.
In this patch we only convert assignments with a concatenation on the
LHS, if all target LValues can be converted into DFG.
This is the proper fix for #4231
2025-08-03 14:52:20 +01:00
Wilson Snyder
36577bb549
Add check for missing 'parameter' on implicit types
2025-08-02 17:02:45 -04:00
Wilson Snyder
473d54aa95
Internals: Fis emit spacing etc. No functional change
2025-08-02 13:47:07 -04:00
Wilson Snyder
dca504c706
Internals: Use UINFOTREE istead of dumpTree
2025-08-02 13:44:40 -04:00
Ryszard Rozak
f9bdab65f0
Fix coverage of variables of complex types ( #6250 )
2025-08-01 13:24:18 +02:00
Szymon Gizler
61f4c97f40
Support unassigned virtual interfaces ( #5265 ) ( #6245 )
2025-08-01 12:39:13 +02:00
Rodrigo Batista de Moraes
d0f0919830
Fix write of 0 in '%c' ( #6248 ) ( #6249 )
2025-08-01 07:54:18 +02:00
Wilson Snyder
bd1ac03828
Add I/O versus data declaration checking.
2025-07-31 18:38:50 -04:00
Ryszard Rozak
d8f1e1113a
Fix error when force assignment is used with ref function args ( #6244 )
2025-07-31 12:48:37 +02:00
Wilson Snyder
9d38e63269
Remove error on missing forward declarations of typedef in class ( #6207 ).
2025-07-30 09:14:13 -04:00
Geza Lore
9d2adf3e49
Internals: Enable EmitV to output formatted code to std::ostream ( #6239 )
...
Introduce V3OutStream as a V3OutFormatter that writes to a stream
instead of a file. This can be used to emit formatted code fragments
e.g. in debug prints and graph dumps.
2025-07-30 13:41:21 +02:00
Igor Zaworski
2b62f5a625
Add error when trying to assign class object to variable of non-class types ( #6237 )
2025-07-30 09:48:02 +02:00
Wilson Snyder
0da9f6eb03
Fix queue typedef with unbounded slice ( #6236 ).
2025-07-28 19:36:52 -04:00
Ryszard Rozak
a5b0a0d9dd
Add support for `$countones` in constraints ( #6144 ) ( #6235 )
2025-07-28 16:14:03 +02:00
Wilson Snyder
0bd291e6cd
Fix unused variable compile error ( #6222 partial)
2025-07-28 02:27:55 -04:00
Wilson Snyder
5c1d7f3ce9
Fix negate of wide structure selections ( #6186 ).
2025-07-28 02:20:57 -04:00
Wilson Snyder
e69df457fd
Fix MODDUP with duplicate packages to take first package ( #6222 ).
2025-07-28 01:45:03 -04:00
Wilson Snyder
47c5b220b3
Support non-ansi ports with `wire` before `input`
2025-07-27 17:13:56 -04:00
Wilson Snyder
64a82508f2
Fix error on `with` to give UNSUPPORTED ( #6134 )
2025-07-27 16:12:16 -04:00
Paul Swirhun
bd2cb989d1
Support bit queue streaming ( #5830 ) ( #6103 ).
2025-07-27 15:29:56 -04:00
github action
92a4bff047
Apply 'make format'
2025-07-27 14:31:15 +00:00
Wilson Snyder
d359fffcdc
Internals: Refactor V3Task and add loop assert ( #6218 )
2025-07-27 10:30:19 -04:00
Wilson Snyder
c4b3f1e99c
Tests: Add test and assert for nested simulated loops ( #6223 )
2025-07-27 09:43:46 -04:00
Geza Lore
895b85a16e
Fix Replicate with unsigned count but MSB set ( #6231 ) ( #6233 )
...
Correctly compute witdh of AstReplicate in its constructor when the
count is unsigned but its MSB is set.
2025-07-27 12:30:19 +02:00
Wilson Snyder
1725ee9c52
Fix loop initialization visibility outside loop ( #4237 ).
2025-07-27 03:42:41 -04:00
Wilson Snyder
d93abd002f
Internals: V3Unroll refactoring. No functional change intended
2025-07-27 03:36:41 -04:00
Wilson Snyder
470f99694e
Revert d8dbb08a: Support bit queue streaming ( #5830 ) ( #6103 )
2025-07-26 17:59:52 -04:00
Wilson Snyder
f3560837ec
Add error on missing forward declarations ( #6207 ).
2025-07-26 17:11:35 -04:00
Paul Swirhun
d8dbb08a95
Support bit queue streaming ( #5830 ) ( #6103 )
2025-07-26 16:53:51 -04:00
Wilson Snyder
c2e0f496bd
Internals: Free up 32 bits in FileLine.
...
Limits columns to 16M columns, or may report wrong column on such long lines.
Limits single token to 64K lines, or may report wrong line for that token.
2025-07-26 15:55:33 -04:00
Wilson Snyder
39a5c731ac
Tests: Fix missing forward decls ( #6202 partial)
2025-07-26 15:48:19 -04:00
Wilson Snyder
42e1c83875
Internals: Add some FileLine stats
2025-07-26 15:46:25 -04:00
Geza Lore
504884b7d5
Refactor DFG context objects ( #6232 )
...
- Move All DFG context objects to V3DfgContext.h
- Add separate object for ast2dfg and dfg2ast passes
- Factor out commonalities
No functional change
2025-07-26 20:37:01 +01:00
github action
94ef630490
Apply 'make format'
2025-07-26 06:45:26 +00:00
Wilson Snyder
d289934ca9
Improve `--skip-identical` to skip on identical input file contents ( #6109 ).
2025-07-26 02:43:57 -04:00
George Polack
f1826a7c20
Support Verilog real to SystemC double ( #6136 ) ( #6158 )
2025-07-25 20:05:36 +02:00
Wilson Snyder
fa62cd3486
Fix `--stats` overridden by skipping identical build ( #6220 ).
2025-07-25 07:23:02 -04:00
Yilou Wang
10ac99ac05
Support randomization of scope variables with 'std::randomize()' ( #5438 ) ( #6185 )
2025-07-25 12:13:46 +02:00
Wilson Snyder
b408e097f6
Fix unsigned replicate ( #6229 )
2025-07-24 22:55:26 -04:00
Geza Lore
94bebb2bcb
Fix dereferencing stale iterator in DfgVertex::scopep() ( #6227 )
...
Fix dereferencing stale iterator in DfgVertex::scopep()
Fixes part of #6225
2025-07-24 15:31:31 +01:00
Geza Lore
2be257369a
Fix component numbers of new Vertices in V3DfgBreakCycles ( #6228 )
...
Fix component numbers of new Vertices in V3DfgBreakCycles
Fixes part of #6225
2025-07-24 15:31:09 +01:00
Wilson Snyder
e995646898
Internals: Favor std::array. No functional change intended.
2025-07-24 02:39:03 -04:00
Wilson Snyder
2287d420ee
Optimize to return memory when using -build ( #6192 ) ( #6226 ).
2025-07-24 08:36:58 +02:00
Wilson Snyder
db5b2669fc
Add current memory usage statistic ( #6192 partial)
2025-07-24 08:36:58 +02:00
Wilson Snyder
460bfbf181
Fix replicate of negative giving 'REPLICATE has no expected width' internal error ( #6048 ).
2025-07-23 18:07:50 -04:00
Wilson Snyder
050e5ddb5b
Fix internal error after bad method
2025-07-23 17:17:35 -04:00
Geza Lore
7c5d462564
Remove AstJumpLabel ( #6221 )
...
Remove AstJumpLabel
AstJumpGo now references one if its enclosing AstJumpBlocks, and
branches straight after the referenced block.
That is:
```
JumpBlock a {
...
JumpGo(a);
...
}
// <--- the JumpGo(a) goes here
```
This is sufficient for all use cases and makes control flow much easier to
reason about. As a result, V3Const can optimize a bit more aggressively.
Second half of, and fixes #6216
2025-07-23 17:51:16 +01:00
Geza Lore
763183f067
Internals: Remove AstWhile::precondsp() ( #6219 ). No functional change intended.
2025-07-23 08:50:39 -04:00
Geza Lore
2958a5aaae
Internals: Do not emit temporaries for atomic assignments. ( #6217 )
...
Added test for a particularly convoluted case requiring fixup in
V3Premit. To help with statistics stability, also prevent V3Premit from
introducing temporaries for assignment where the RHS reads the LHS, but
the assignment is known to be atomic (by emitted C++ semantics).
Also rename `createWideTemp` to `createTemp`, as it is used for non-wide
expressions as well.
2025-07-23 11:48:55 +02:00
Geza Lore
344fabf56a
Fix incorrect assumption in V3DfgDecomposition ( #6215 )
...
Due to SCC merging the deleted assumption/assertion can be violated.
Fixes #6211 .
2025-07-22 14:03:35 +01:00
Geza Lore
9f04ee68c8
Optimize combinational cycles through arrays in DFG ( #6210 )
...
Extending V3DfgBreakCycles to handle common cases involving unpacked
arrays.
2025-07-22 08:23:45 +01:00
github action
b5126a6abe
Apply 'make format'
2025-07-21 23:29:42 +00:00
Danny Oler
74d4b0c0ea
Fix automatic task variables in unrolled loops with forks ( #6194 ) ( #6201 ).
2025-07-21 19:28:50 -04:00
Geza Lore
7401a8a43a
Refactor DFG IndependentBits analysis to work for any vertex. ( #6209 )
...
This used to be restricted to variable vertices, but now can handle
arbitrary circular vertices that represent packed values. It also
converges faster than the earlier version. Prep for resolving loops
through arrays.
2025-07-21 19:57:02 +01:00
Geza Lore
7646e7d89c
Exclude SystemC variables from DFG ( #6208 )
...
SystemC variables are fairly special (they can only be assigned to/from,
but not otherwise participate in expressions), which complicates some
DFG code. These variables only ever appear as port on the top level
wrapper, so excluding them from DFG does not make us loose any
optimizations, but simplifies internals.
2025-07-21 18:32:08 +01:00
Geza Lore
a8dca71ed0
Support more complex combinational assignments in DFG. ( #6205 )
...
Previously DFG was limited to having a Sel, or an ArraySel potentially
under a Concat on the LHS of combinational assignments. Other forms or
combinations were not representable in the graph.
This adds support for arbitrary combinations of the above by
combining DfgSplicePacked and DfgSpliceArray vertices introduced in
#6176 . In particular, Sel(ArraySel(VarRef,_),_) enables a lot more code
to be represented in DFG.
2025-07-21 12:33:12 -04:00
Igor Zaworski
98b8d43a4a
Fix parameter-dependent type linking ( #6170 )
2025-07-21 07:30:10 -04:00
Bartłomiej Chmiel
d419c49921
Internals: Fix unused variable, no functional change ( #6204 )
...
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
2025-07-21 07:28:01 -04:00
Max Wipfli
a50ea2a1a6
Optimize 2 ** X to 1 << X if base is signed ( #6203 )
2025-07-20 09:56:34 -04:00
Wilson Snyder
078bb21a89
Add wire data type checking per IEEE.
2025-07-20 07:21:30 -04:00
Wilson Snyder
b8b9478938
Improve enum base type checking error message.
2025-07-19 22:37:07 -04:00
Wilson Snyder
641e0e5672
Internals: Fix assertion if bad display
2025-07-19 21:12:10 -04:00
Ibrahim Burak Yorulmaz
9d146eae16
Fix VPI signal range order ( #6189 ) ( #6200 )
2025-07-19 20:22:02 -04:00
Wilson Snyder
7d43a935bd
Add SPECIFYIGN warning for specify constructs that were previously silently ignored.
2025-07-18 19:32:34 -04:00
Yilou Wang
9b99d9697f
Fix virtual interface member propagation ( #6175 ) ( #6184 )
2025-07-18 09:07:31 -04:00
Ryszard Rozak
a21ecb2ab9
Add support for randomize..with on objects of aliased types ( #6195 )
2025-07-18 13:04:47 +02:00
Ryszard Rozak
28808f38bb
Dump function to which AstAddrOfCFunc points ( #6188 )
2025-07-18 08:37:00 +02:00
Wilson Snyder
7a6775ca84
Internals: Rename memPeakUsageBytes
2025-07-17 22:16:59 -04:00
Wilson Snyder
e527ff49a3
Report `--stats` final results after build phase
2025-07-17 20:41:46 -04:00
Wilson Snyder
c1506deef9
Add enum base type checking per IEEE.
2025-07-17 20:20:43 -04:00
Wilson Snyder
87050670b4
Fix structure select causing 'Wide Op' error ( #6191 ).
2025-07-17 18:17:49 -04:00
Wilson Snyder
7f1011e5f7
Make some CVTREAL fatal where IEEE requires it.
2025-07-16 18:07:07 -04:00
Igor Zaworski
8c5ba3a0d7
Fix conflicting function/class name linking error ( #6182 )
2025-07-16 17:25:01 -04:00
Igor Zaworski
826e5b0826
Fix `--coverage-expr` null pointer dereference ( #6181 )
2025-07-16 12:07:34 -04:00
Artur Bieniek
abd509ce53
Support delays in emitted Verilog ( #6177 )
2025-07-16 11:52:56 -04:00
Ryszard Rozak
1bf24c7eb4
Add support for disabling begin just under fork from outside that begin ( #5432 partial) ( #6183 )
2025-07-16 16:04:17 +02:00
Wilson Snyder
1f0357ba93
Add NOEFFECT warning, replacing previous `foreach` error.
2025-07-16 08:18:57 -04:00
Wilson Snyder
db6b17fdb4
Fix error message
2025-07-15 17:41:08 -04:00
Artur Bieniek
f3e109d8c5
Support covergroup extends, etc. ( #6160 )
2025-07-15 09:31:08 -04:00
Wilson Snyder
371ac07c6f
Fix CVTREAL not being able to be disabled in e.g. primitive terminals.
2025-07-14 20:08:44 -04:00
Wilson Snyder
caf3522364
Support implicit enum declarations with packed dimensions
2025-07-14 19:50:02 -04:00
Geza Lore
03e0d49d99
Optimize DFG partial assignments ( #6176 )
...
This is mostly a refactoring, but also enables handling some more
UNOPTFLAT, when the variable is only partially assigned in the cycle.
Previously the way partial assignments to variables were handled were
through the DfgVerexVar types themselves, which kept track of all
drivers. This has been replaced by DfgVertexSplice (which always drives
a DfgVeretexVar), and all DfgVertexVar now only have a single source,
either a DfgVertexSplice, if partially assigned, or an arbitrary
DfgVertex when updated as a whole.
2025-07-14 17:09:34 -04:00
Ryszard Rozak
e2e5d9eaf1
Support disabling a fork from outside that fork ( #6174 )
2025-07-14 06:51:58 -04:00
Wilson Snyder
2f199f20cf
Add ENUMITEMWIDTH error, and apply to X-extended and ranged values.
2025-07-12 14:14:17 -04:00
Yilou Wang
1044398f95
Support member-level triggers for virtual interfaces ( #5166 ) ( #6148 )
2025-07-11 21:04:51 -04:00
Geza Lore
77180c4020
Optimize more cycles in DFG ( #6173 )
...
Added a second algorithm to break cycles in DFG by identifying which
bits of a circular variable are actually independent of the variable,
then reuse the existing (but extended) driver tracing algorithm to
eliminate them.
This can fix up things like: `assign gray = binary ^ (gray >> 1)`
2025-07-11 14:19:09 -04:00
github action
2fc12d951e
Apply 'make format'
2025-07-11 17:11:31 +00:00
Petr Nohavica
0982260d3b
Fix constructor parameters in inheritance hierarchies ( #6036 ) ( #6070 )
2025-07-11 13:10:36 -04:00
Artur Bieniek
58b867c39c
Support multiple variables on RHS of a `force` assignment ( #6163 )
2025-07-10 21:12:44 -04:00
Igor Zaworski
4e8a8a0398
Fix param-dependent class typedef linking ( #6171 )
2025-07-10 21:11:09 -04:00
Artur Bieniek
4dc6a31276
Fix omitting error when assigning to an input ( #6169 )
2025-07-10 20:37:55 -04:00
Geza Lore
ce77bac99a
Break some combinational cycles in DFG ( #6168 )
...
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:
```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
2025-07-10 18:46:45 +01:00
Igor Zaworski
31c279a7b3
Support randomize() on class member selects ( #6161 )
2025-07-10 04:59:05 -04:00
Wilson Snyder
d89df33fcd
Change control file `public_flat_*` and other signal attributes to support __ in names ( #6140 ).
2025-07-09 20:48:00 -04:00
Wilson Snyder
9fc7143fce
Fix genvar error with `-O0` ( #6165 ).
2025-07-09 19:11:48 -04:00
Wilson Snyder
597b973f7b
Internals: Fix some style issues. No functional change.
2025-07-09 18:52:26 -04:00
Igor Zaworski
dbfbc657e1
Fix class extends dotted error ( #6162 )
2025-07-09 17:12:11 -04:00
Ryszard Rozak
8b3a6ba542
Support disable dotted references ( #6154 )
2025-07-09 16:59:26 -04:00
Igor Zaworski
5777ab75c7
Fix crash with --dumpi-V3LinkDot without --debug ( #6159 )
2025-07-08 10:28:17 -04:00
Geza Lore
e494cf22a4
Add DfgPeephole patterns ( #6149 )
2025-07-07 16:25:29 +01:00
Wilson Snyder
5a6d5ed96b
Support property `iff` and `implies`.
2025-07-03 21:13:04 -04:00
Wilson Snyder
f77af4e6f6
Important: Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes.
2025-07-03 19:36:28 -04:00
Wilson Snyder
e3c7dee6ef
Internals: Add UINFOTREE method
2025-07-03 19:07:50 -04:00
Wilson Snyder
6c9cbaef62
Internals: Clean up some constructors. No functional change intended.
2025-07-03 18:59:32 -04:00
Todd Strader
08fef668cd
Fix more wide ternary + coverage cases ( #6155 )
2025-07-03 18:00:39 -04:00
Paul Swirhun
e0c3b42262
Fix developer build error on MacOS/Flex2.6.4 ( https://github.com/verilator/verilator/pull/6153 )
2025-07-02 19:56:10 -07:00
Wilson Snyder
4ddc649836
Add UNSUPPORTED rather than syntax error on pullup/pulldown strengths
2025-07-02 20:54:47 -04:00
Wilson Snyder
77908447e6
Support scoped `new` ( #4199 ).
2025-07-02 19:54:57 -04:00
Wilson Snyder
bb41c6b26b
Internals: Fix wrong fileline on some parsing scan-aheads.
2025-07-02 18:47:27 -04:00
Todd Strader
ae0f29ed37
Fix wide non-blocking assignment mis-optimization ( #6150 ) ( #6152 )
2025-07-02 18:43:10 -04:00
Wilson Snyder
73ca2ab997
Support `$past_gclk`
2025-07-01 18:00:04 -04:00
Geza Lore
7a3f1f16ca
Optimize DFG before V3Gate ( #6141 )
2025-07-01 17:55:08 -04:00
Wilson Snyder
e015805194
Fix stripping on randomize ( #6144 partial)
2025-07-01 08:57:08 -04:00
Wilson Snyder
9598ef9315
Internals: Avoid - in enum name
2025-07-01 05:45:10 -04:00
Wilson Snyder
cd0f35fe67
Fix recursive module assertion, broken recent lib commit ( #5891 partial fix)
2025-06-30 20:30:27 -04:00
Wilson Snyder
d455ec6229
Fix `specparam` PATHPULSE broken recent commit ( #6142 ).
2025-06-30 18:33:50 -04:00
github action
b27bd6526a
Apply 'make format'
2025-06-30 01:00:56 +00:00
Wilson Snyder
916a89761e
Add `--work` library-selection option ( #5891 partial).
2025-06-29 20:17:27 -04:00
Geza Lore
c3d86626ee
Internals: Remove unused AstNodeModule 'activesp' child ( #6138 )
2025-06-29 09:56:44 -04:00
Wilson Snyder
5d32fc56ac
Support 'config' parsing, but not functionally
2025-06-28 20:32:19 -04:00
Wilson Snyder
93f447dd4a
Support constant functions with left-hand-side concatenates.
2025-06-28 17:12:03 -04:00
Geza Lore
bc892deacc
Safely support non-overlapping blocking/non-blocking assignments ( #6137 )
...
The manual for the BLKANDNBLK warning describes that it is safe to
disable that error if the updated ranges are non-overlapping. This
however was not true (see the added t_nba_mixed_update* tests).
In this patch we change V3Delayed to use a new ShadowVarMasked
scheme for variables that have mixed blocking and non-blocking
updates (or the FlagUnique scheme for unpacked variables), which
is in fact safe to use when the updated parts are non-overlapping.
Furthermore, mixed assignments are safe as far as scheduling is
concerned if either:
- They are to independent parts (bits/members/etc) (with this patch)
- Or if the blocking assignment is in clocked (or suspendable) logic.
The risk in scheduling is a race between the Post scheduled NBA
commit, and blocking assignments in combinational logic, which might
order incorrectly.
The second point highlights that we can handle stuff like this safely,
which is sometimes used in testbenches:
```systemverilog
always @(posedge clk) begin
if ($time == 0) a = 0;
end
always @(posedge clk) begin
if ($time > 0) a <= 2;
end
````
The only dangerous case is:
```systemverilog
always @(posedge clk) foo[idx] <= val;
assign foo[0] = bar;
```
Whit this patch, this will still resolve fine at run-time if 'idx' is
never zero, but might resolve incorrectly if 'idx' is zero.
With the above in mind, the BLKANDNBLK warning is now only issued if:
- We can't prove that the assignments are to non-overlapping bits
- And the blocking assignment is in combinational logic
These are the cases that genuinely require user attention to resolve.
With this patch, there are no more BLKANDNBLK warnings in the RTLMeter
designs.
Fixes #6122 .
2025-06-28 20:45:45 +01:00
Wilson Snyder
b914cda1c7
Internals: cppcheck cleanups. No functional change.
2025-06-28 12:29:41 -04:00
Wilson Snyder
62e5e3aa0c
Fix interface array connections with non-zero low declaration index.
2025-06-28 09:43:02 -04:00
Wilson Snyder
f508dadc97
Support `specparam` ( #5767 ).
2025-06-28 08:23:43 -04:00
Wilson Snyder
3defaf8ffb
Rename Verilator Config Files to Verilator Control Files.
...
Avoids conflict with IEEE `config`. No functional change intended.
2025-06-27 20:38:01 -04:00
Wilson Snyder
75229cc03d
Fix `pre_randomize`/`post_randomize` when no randomize ( #6122 ).
2025-06-26 18:34:20 -04:00
Wilson Snyder
e422c183ff
Fix method calls without parenthesis ( #6127 ).
2025-06-26 18:16:21 -04:00
Wilson Snyder
2c5e9a785a
Standardize indent of emitted makefile
2025-06-26 17:36:15 -04:00
Kamil Rakoczy
d183b4edde
Fix variables declared in fork after taskify ( #6126 )
2025-06-26 10:28:58 -04:00
Wilson Snyder
2df0390c04
Commentary
2025-06-25 21:14:25 -04:00
Wilson Snyder
3209bee3b3
Fix colon-divide operator without space ( #6121 ).
2025-06-25 04:56:52 -04:00
Wilson Snyder
51545b36ca
Internals: Add format-make rule and standardize Makefile indents. No functional change intended.
2025-06-24 17:58:55 -04:00
Wilson Snyder
6af694b04b
Support `$timeformat` with missing arguments ( #6113 ).
2025-06-24 17:30:05 -04:00
Wilson Snyder
f9f70383fa
Fix instability in non-data type internal error
2025-06-24 17:29:44 -04:00
Geza Lore
916d473eff
Internals: Replace unnecessary AstSel::widthp() child node with const in node ( #6117 )
2025-06-24 11:59:09 -04:00
Wilson Snyder
544cb4a90f
Fix decoding octal string escapes with 1-2 digits ( #6108 ).
2025-06-23 18:37:44 -04:00
Geza Lore
2daa09a255
Optimize constify within Expand and Subst ( #6111 )
...
These passes blow up the Ast size on some designs, so delaying running V3Const
until after the whole pass can notably increase peak memory usage. In this
patch we apply V3Const per CFunc within these passes, which saves on memory.
Added -fno-const-eager to disable the intra-pass V3Const application, for
debugging.
2025-06-23 17:58:26 -04:00
Geza Lore
d35e4a2b60
Improve memory usage for SenTrees in V3OrderProcessDomains ( #6112 )
2025-06-23 14:22:10 -04:00
Wilson Snyder
49fe129634
Fix `--lib-create` with double-underscore ( #6099 ).
2025-06-18 08:56:32 -04:00
Peter Birch
75df36bc8f
Add hint of the signed rhsval in oversized replication error ( #6098 )
2025-06-17 16:59:18 -07:00
Geza Lore
48600c77b5
Fix DFG binToOneHot table index missing driver ( #6100 )
2025-06-17 15:53:47 +01:00
Geza Lore
277611bcdd
Add DFG binToOneHot pass to generate one-hot decoders ( #6096 )
...
Somewhat commonly, there is code out there that compares an expression (or
variable) against many different constants, e.g. a one-hot decoder:
```systemverilog
assign oneHot = {x == 3, x == 2, x == 1, x == 0};
```
If the width of the expression is sufficiently large, this can blow up
a GCC pass and take an egregious amount of memory and time to compile.
Adding a new DFG pass that will generate a cheap one-hot decoder:
to compute:
```systemverilog
wire [$bits(x)-1:0] idx = <the expression being compared many times>
reg tab [1<<$bits(x)] = '{default: 0};
reg [$bits(x)-1:0] pre = '0;
always_comb begin
tab[pre] = 0;
tab[idx] = 1;
pre = idx ; // This assignment marked to avoid a false UNOPFTLAT
end
```
We then replace the comparisons `x == CONST` with `tab[CONST]`.
This is generally performance neutral, but avoids the compile time and memory
blowup with GCC (128GB+ -> 1GB in one example).
We do not apply this if the comparisons seem to be part of a `COMPARE ?
val : COND` conditional tree, which the C++ compilers can turn into jump
tables.
This enables all XiangShan configurations from RTLMeter to now build with GCC,
so in this patch we enabled those in the nightly runs.
2025-06-16 23:14:24 +01:00
Geza Lore
832629c602
Internals: Refactor DFG getCanonicalVariable for reusability ( #6094 )
...
This changes hashed names in the generated code, but otherwise no
functional change.
2025-06-16 07:25:44 -04:00
Geza Lore
5e5b5ab69d
Restrict Dfg PUSH_SEL_THROUGH_CONCAT pattern ( #6092 )
...
This pattern is bit dubious and can blow up the size of the logic.
Restrict it to only apply if it strictly does not increase DFG size.
2025-06-15 18:10:42 -04:00
Geza Lore
d059806dbd
Fix Dfg eliminateVar pass to remove more variables ( #6091 )
...
Failing to reset the work list pointer in vertices leads to not removing
some redundant variables if they become redundant after having been
considered once already.
2025-06-15 18:12:37 +01:00
Geza Lore
bca2e2c16e
Optimize DFG De Morgan patterns ( #6090 )
...
It's ok if the replaced vertex has multiple sinks, this pattern cannot
increase the size of logic even then.
2025-06-15 11:00:11 -04:00
Todd Strader
47f5a6a52b
Fix unpacked to packed parameter assignment ( #6088 ) ( #6081 )
2025-06-12 12:47:58 -04:00
Todd Strader
206a0b4fd2
Fix casting reals to large integrals ( #6085 )
2025-06-12 11:53:10 -04:00
Bartłomiej Chmiel
dc307270f7
Fix nested hier blocks workers error ( #6087 )
...
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
2025-06-12 07:15:46 -04:00
Wilson Snyder
4990b44120
Fix trace hierarchicalName runtime errors ( #5668 ) ( #6076 ).
2025-06-10 20:17:32 -04:00
Paul Swirhun
4925f9ad73
Support 1-bit params with -G and -pvalue ( #6051 ) ( #6082 )
2025-06-10 17:39:13 -04:00
Kamil Rakoczy
58ea7ad361
Fix class typedef elaboration ( #6080 )
2025-06-10 12:03:26 -04:00
Wilson Snyder
b553502d8a
Fix number dumps to show 'null'
2025-06-10 08:17:45 -04:00
Bartłomiej Chmiel
86d2ea8c70
Optimize DPI temporary 'for' loop performance ( #6079 )
...
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
2025-06-10 08:17:26 -04:00
Todd Strader
d9534ec626
Fix x assign vs init randomization ( #6075 )
2025-06-09 17:59:01 -04:00
Geza Lore
a6bae7f196
DFG peephole: Only push SEL through COND when SEL is the only sink. ( #6071 )
...
This avoids potential O(n) logic duplication where 'n' is the fanout of
the COND node.
Fixes #6064 .
2025-06-08 11:12:39 +01:00
Wilson Snyder
5b2dc52681
Fix array bounds checking with class member selects ( #5996 ) ( #5997 ).
2025-06-07 17:20:48 -04:00
Todd Strader
a044697990
Fix signed cast ( #6912 ) ( #6068 )
2025-06-06 21:13:31 -04:00
Wilson Snyder
54e637c72b
Fix `--skip-identical` skipping on some errors ( #6066 ).
2025-06-06 17:18:02 -04:00