luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,114 Commits 2 Branches 167 Tags 188 MiB
Commit Graph

4666 Commits

Author SHA1 Message Date
Kamil Danecki 2ce417e476 Fix message 
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
 2026-02-13 11:27:53 +01:00
Kamil Danecki db39bc0d3d Comment for negative exponents 
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
 2026-02-12 18:18:52 +01:00
Kamil Danecki 5610989e1a Apply suggestion 
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
 2026-02-12 18:17:07 +01:00
Kamil Danecki b24b89207d Fix message 
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
 2026-02-12 15:56:50 +01:00
Kamil Danecki dd155627f2 Fix t_constraint_unsup out message 
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
 2026-02-12 12:20:09 +01:00
Kamil Danecki eeff109379 Add support for power expressions with constant exponent in constraints 
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
 2026-02-12 11:42:41 +01:00
Igor Zaworski 446bec3d1a
Fix event triggering (#6932) 2026-02-11 10:35:59 -08:00
Yilou Wang e41436bd4a
Support inherited and nested pre/post_randomize callbacks (#7049) (#7053) 2026-02-11 09:33:57 -08:00
Yilou Wang 554fcef627
Fix rand_mode()/constraint_mode() when used as function arguments (#7051) (#7055) 2026-02-11 09:33:09 -08:00
Yilou Wang 996a4b6e1a
Fix constraint_mode()/rand_mode() in constructor being overwritten by init code (#7054) 2026-02-11 09:32:08 -08:00
Yilou Wang 84350859e0
Support System Functions in Constraint Blocks (#7028) (#7036) 2026-02-11 05:19:25 -08:00
Pawel Kojma 5d12ae3a2f
Fix non-member identifiers used inside constraints (#7033) 2026-02-11 05:18:24 -08:00
Yilou Wang 22dc437dbb
Support std::randomize() for queue, dynamic array, and associative array variables (#7044) 2026-02-10 18:24:25 -08:00
Wilson Snyder 67bff893bf Fix whitespace 2026-02-10 20:17:22 -05:00
Yilou Wang 2bb807a931
Fix Inline foreach constraints on dynamic arrays of class objects (#7030) (#7037) 2026-02-10 15:22:31 -08:00
Geza Lore a031dd1a22
Fix tracing without module inlining to match with inlining (#7041) 
This is an attempt to generate an identical trace file scope hierarchy
both with and without -fno-inline. Primarily because it's needed for
testing in upcoming patch, but also improves consitency prior to #7001
 2026-02-10 21:05:41 +00:00
Yilou Wang 925543676e
Fix rand_mode() on nested object variables causes Z3 solver error (#7031) (#7034) 2026-02-10 13:59:09 -05:00
Yilou Wang 8791e6c5f2
Support constraint_mode() on static constraints (#7027) (#7038) 2026-02-10 13:58:35 -05:00
Ryszard Rozak 6303eb45ce
Fix multidim dynamic array elements passed to ref argument (#7023) 2026-02-10 08:46:04 +01:00
Igor Zaworski a660fa54a7
Fix unique constraint in derived class (#7022) 2026-02-09 09:56:38 -05:00
github action a28bd5a085 Apply 'make format' 2026-02-09 03:48:11 +00:00
Leela Pakanati e36838ad8e
Fix tristate enables for -fno-inline (#7016) (#7019) 2026-02-08 22:47:09 -05:00
Wilson Snyder 5a236dd35d
Change INITIALSTATIC to also report on processes, per IEEE (#7020) 2026-02-08 20:47:12 -05:00
Wilson Snyder ba194f3790 Tests: Avoid implied static variables, to avoid future warning 2026-02-08 18:20:28 -05:00
Wilson Snyder 9ba625225d Internals: Minor cleanups preparing for initialization fixes. No functional change. 2026-02-08 17:54:04 -05:00
Wilson Snyder 8700617fae Internals: Cleanup CRESET verilog and other misc fixes 2026-02-08 17:53:56 -05:00
Wilson Snyder e12c62c070 Change JSON dumps to not include booleans that are false (#6977). 
Fixes #6977.
 2026-02-08 07:59:55 -05:00
Wilson Snyder 0c83594e1e Fix variable conflict when multiple cells with unused input defaults 2026-02-07 18:11:55 -05:00
Wilson Snyder bbb231dfe2 Internals: Minor cleanups preparing for initialization fixes. No functional change. 2026-02-07 14:16:12 -05:00
Geza Lore bb0e1c8c61
Optimize temporary insertion for concatenations in Dfg (#7013) 
Add a new Dfg pass 'pushDownSel'. This will try to move selects through
a tree of concatenations in order to eliminate temporary nodes holding
intermediate concatenation results. This can get rid of a lot of
variables when packed arrays are assigned in parts (e.g. bit-wise).
 2026-02-07 18:06:12 +00:00
github action abdac02b50 Apply 'make format' 2026-02-07 15:07:33 +00:00
Leela Pakanati 8922794088
Tests: Add test cases for interface array access with loop variable index (#1418 tests) (#7011) 2026-02-07 10:06:37 -05:00
Igor Zaworski dc26dd601d
Fix internal error - virtual interface not found (#7010) 2026-02-06 22:20:10 +00:00
Pawel Kojma 9a8538fafa
Support signed multiplication in constraints (#7008) 2026-02-06 10:14:54 -05:00
github action 60b52a4986 Apply 'make format' 2026-02-06 11:39:13 +00:00
Leela Pakanati b14d65a787
Support modport expression syntax + nested (#2601) (#5581) (#7005) 2026-02-06 06:38:16 -05:00
Leela Pakanati 2215d01d6b
Fix hierarchical interface/modport issues (#5941) (#6997) 2026-02-05 22:15:30 -05:00
Veripool API Bot b82f6beffb Verilog format 2026-02-05 17:45:24 -05:00
Wilson Snyder 9fab6bfcf0 Tests: Fix t_assert_elab_p.py reruns 2026-02-05 17:42:39 -05:00
Wilson Snyder 1adedd0bfa Tests: Cover deassign 2026-02-05 12:57:26 -05:00
Geza Lore 4e9792c34c
Fix C++ types of non-inlined module ports (#7002) 
We use special C++ types for ports, e.g. SystemC types in --sc mode, and native C arrays for unpacked arrays in --cc mode. These types are not substitutable for internal types, e.g. VlUnpacked, however all the runtime primitives expect internal types.

I think the intention was to use these special IO types only for top level ports, but the current implementation also uses them for the ports of all non-inlined modules. This means the output C++ will not compile if such a port is passed to a runtime primitive (e.g. array 'sort' as in the new test) or DPI import.

Changed to use the special IO types only on the top level ports.

Note these are likely still broken if attempting to invoke on a top level port (we might be saved by wrapTop, but later optimizations might eliminate the intermediary)
 2026-02-05 14:49:07 +00:00
github action 55eaa64386 Apply 'make format' 2026-02-04 21:27:14 +00:00
Leela Pakanati 57c3b8e51b
Support nested interface as port connection (#5066) (#6986) 2026-02-04 16:26:20 -05:00
Oleh Maksymenko 229a696ab8
Add decoded Verilog name in JSON output (#6919) (#6995) 2026-02-04 07:08:33 -05:00
Wilson Snyder 1dd80996cd Fix some error capitalization 2026-02-03 19:57:23 -05:00
Wilson Snyder aaa5c5e857 Tests: t_dist_warn_coverage.py: Understand wildcards (#6994 comment) 2026-02-03 19:51:23 -05:00
Christian Hecken 3c680ba5a4
Tests: Fix LCOV_EXCL matching in fully commented lines (#6994) 2026-02-03 19:03:43 -05:00
Krzysztof Bieganski ad85d89817
Support `foreach` with nested dots (#6991) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2026-02-03 08:44:18 -05:00
Wilson Snyder 76c4ae5683 Add back LICENSE file due to (f4pga/actions#49) 2026-02-02 19:34:10 -05:00
Wilson Snyder bb979a00c8 Fix `$stacktrace` to decode through internal-c++filt (#6985). 2026-02-02 19:01:24 -05:00