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Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>

test_regress/t/t_constraint_unsup.v

@@ -1,21 +1,19 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed under the Creative Commons Public Domain.
-// SPDX-FileCopyrightText: 2026 Antmicro
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2026 by PlanV GmbH.
 // SPDX-License-Identifier: CC0-1.0
 
 class Packet;
-   rand real x;
-   constraint cons { x + 1.0 > 0.0; }
+  rand real x;
+  constraint cons { x + 1.0 > 0.0; }
 endclass
 
 module t;
+  Packet p;
 
-   Packet p;
-
-   initial begin
-      p = new;
-      void'(p.randomize());
-      $finish;
-   end
+  initial begin
+    p = new;
+    void'(p.randomize());
+  end
 endmodule