Fix t_constraint_unsup out message
Signed-off-by: Kamil Danecki <kdanecki@internships.antmicro.com>
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@ -1,5 +1,5 @@
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%Error-UNSUPPORTED: t/t_constraint_unsup.v:9:27: Unsupported expression inside constraint
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9 | constraint cons { m_one ** 2 > 0; }
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| ^~
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9 | constraint cons { x + 1.0 > 0.0; }
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| ^
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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@ -5,8 +5,8 @@
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand real m_one;
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constraint cons { m_one + 1.0 > 0.0; }
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rand real x;
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constraint cons { x + 1.0 > 0.0; }
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endclass
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module t;
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