3865c726f2
074-dump_all: increase jobs and tiles per job
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
63bb8337f8
072-ordered_wires: increased parallel jobs.
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This changes also the way the ordered wires final files are generated.
In fact, now, with the help of a Lock, all the suprocesses directly
access the final files, updating them. Once the write completes, the
temporary file is deleted.
This saves up disk space.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
c5a33cb161
005-tilegrid: further increasing to 6 number of specimens for mmcm
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e8a2777a17
005-tilegrid: reduce number of specimens
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
5c829daa8c
005-tilegrid: fixed some over-specific settings in generate_full
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Also added specimens to make some rquired fuzzers find all necessary
features
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
93d1ae82f7
Enable the generation of extra part-dependents files
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This change affects the extra-db target, by adding also the generation
of other part-dependent files, such as tilegrid, tileconn, and others.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
cce638930c
Add clock_region to tilegrid.json for constructing clock networks.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-12-14 22:28:22 -08:00
cc9e00da8f
Merge pull request #1174 from antmicro/zynq_ps7_clocks
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Zynq PS7 clocks
2019-12-12 13:05:29 -08:00
0d0a38cf52
Merge pull request #1175 from antmicro/zynq_ps7_ppips
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Dumping PPIPs for Zynq PS7
2019-12-12 08:50:12 -08:00
810473ef46
Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 17:20:53 +01:00
ef8d405bdb
Added dumping of PPIPs for Zynq PS7 tiles and interconnects.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 09:57:41 +01:00
0507f92345
Ran make format
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-12 09:31:59 +01:00
24ccfb3bb5
Automatic inference of CLK_HROW with PS7 clocks, use of todo list for PS7 clock sources.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 22:39:04 +01:00
fb65464c42
A little hacky but working version.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 19:05:04 +01:00
d84c28b38c
Modified fuzzer 075 to dump IO bank number for each pin.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 17:10:41 +01:00
6086e6d6f5
Modified fuzzer 041 to solve Zynq PS7 FCLK clocks.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-11 16:25:45 +01:00
7bd13efdcb
WIP
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-10 15:21:28 +01:00
a4a033226f
Modified fuzzer 001 to include required features for Zynq parts.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-12-10 14:38:24 +01:00
9401d1c730
071-ppips: fix wrong ppip in ioi tiles
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-12-05 16:40:33 +01:00
24070da931
001-part-yaml: Add iobanks information to part's json
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-12-02 21:39:32 +01:00
cc7ba29c6b
Added forcing of manual routing through "BB" pips to toggle more bits.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-15 12:14:06 +01:00
03b0b9cefc
Added separate clock inputs for PLLs.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-15 12:13:49 +01:00
6fd00834b2
Fixed bit names formatting.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-11-14 16:09:44 +01:00
99d31d2e67
071-ppips: skip HCLK_IOI_CK_IGCLK0 ppips addition
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-11-07 15:03:44 +01:00
4cec0817ab
Merge pull request #1080 from JakeMercer/dsp
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DSP - Add Attribute Fuzzing
2019-11-04 08:16:53 -08:00
827081b3b5
hlck-ioi: fix empty list bug in generate.tcl
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-11-04 11:02:52 +01:00
6a3db24da1
FUZZER - DSP - Fixes Following Review
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Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
15cfb5bd46
FUZZER - DSP - Add Ports & ROI Module
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Added code for ports to the DSP48E1 instances. Moved DSP instances
inside an ROI module and using the verilog top harness as in other
fuzzers.
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
e0fb0c0cb1
FUZZER - DSP - Refactor
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Refactor the DSP Python scripts to be easier to manage. Use JSON
instead of CSV.
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
2019-11-02 11:43:12 +00:00
596bb27e3b
FUZZER - DSP - Add All Attributes
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Added the rest of the DSP attributes; there are still some issues with mapping the bits.
AREG/BREG mode 2 will require inputs to be connected.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
8da263c502
FUZZER - DSP - Refactor for Readability & Extensibility
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Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
624de250e8
FUZZER - DSP - Cleared Bits
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Changed some tags to be prefixed with 'Z'; these bits are cleared and need the prefix to indicate
the inversion so that they are resolved to the DB correctly.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
78d64f7558
FUZZER - DSP - Add AUTORESET_PATDET Attribute Fuzzing
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Added fuzzing for the AUTORESET_PATDET attribute of the DSP48 block. Values are RESET_MATCH,
NO_RESET, and RESET_NOT_MATCH; so this can be represented by 2 bits.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
c575adf8a0
FUZZER - DSP - Add A & B Input Attributes
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Adding `A_INPUT` and `B_INPUT` attribute fuzzing for the DSP48 tiles.
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
2019-11-02 11:43:12 +00:00
13361904ee
hclk-ioi: make 047a dependent on 47 to avoid race condition on piplist
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 17:00:33 +01:00
949cf722d1
hclk-ioi: re-add IDELAYCTRL to exclude-RE
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 12:04:43 +01:00
b057e35e73
hclk-ioi: addressed review comments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
0cf48f337a
hclk-ioi: re-added whole top.py file to avoid having const1
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
1ad84b2b44
hclk-ioi: reduce probability of using lut output as BUFR clock
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
2fb40d0232
hclk-ioi: moved IDELAYCTRL to new parallel fuzzer
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
127022c2a9
hclk-ioi: added IMUX to BEFORE_DIV pips
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-10-31 11:58:11 +01:00
78cf96be0f
Merge pull request #1122 from JakeMercer/whitespace
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Whitespace
2019-10-29 15:04:39 -07:00
b99bd85fa4
Added handling of routing failure in the TCL script.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 18:20:50 +01:00
0377b5fb4c
Disabled reading PIPs and PPIPs for "R" version of CMT tiles for Zynq7.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 17:43:10 +01:00
573ee1a38d
Fixed bug in tag_groups.txt
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 11:55:03 +01:00
bf380f2bdd
PIPs and PPIPs are now not read from the db.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-29 11:50:40 +01:00
8267bcdaeb
Updated regex for PIP todo list.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
5ab90a604d
Inceased N
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
355a571400
Removed the INTERNAL_FEEDBACK tag as it is the same as the PLLE2.COMPENSATION.INTENAL
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
4a6930694f
Reworked fuzzer, added README.md
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-10-28 15:59:38 +01:00
Alessandro Comodi
Keith Rothman
Maciej Kurc
Tomasz Michalak
Jake Mercer
Jake Mercer