6fa0ebd22d
Merge pull request #190 from rwhitby/kintex7_compressed_bitstream
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spiOverJtag: compress the kintex7 bitstreams
2022-03-11 06:49:29 +01:00
9854f4c590
spiOverJtag: compress the kintex7 bitstreams
2022-03-11 15:08:49 +10:30
73e9a31e51
doc/cable: fix build failure
2022-03-10 20:09:42 +01:00
259914910f
board: Xilinx ZC706
2022-03-10 18:53:41 +01:00
6ba1968952
part: Zynq XC7Z045
2022-03-10 18:53:12 +01:00
74eb812c6d
cable: digilent jtag-smt2-nc
2022-03-10 18:52:47 +01:00
2eac30c24e
ftdiJtagMPSSE: fix read/write polarity: always write on neg, read is by default on pos but may on neg with arty
2022-03-10 07:43:14 +01:00
28ebc98b1b
board: add CERN SPEC150
2022-03-03 15:40:42 +01:00
75e3d82a92
part: xc6slx150T
2022-03-03 15:37:18 +01:00
03769be937
spiOverJtag: Xilinx Spartan6 LX150T
2022-03-03 15:36:11 +01:00
8d1ac49ac2
doc: install: in tree build
2022-03-03 15:33:30 +01:00
70b06300f7
Update install.rst
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Build instructions from source for debian-based distros fixed
- a git clone line was added to clarify when and where source should be
- tested on Debian GNU/Linux 11 (bullseye) / WSL2
2022-02-27 17:51:41 +01:00
e7c5af25dc
Merge pull request #186 from pepijndevos/patch-1
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Fix debian command
2022-02-27 17:41:13 +01:00
f88ece80cc
Fix debian command
2022-02-27 16:48:04 +01:00
86fa1e01de
spiFlash: force subsector only for SST26VF032B
2022-02-26 19:10:18 +01:00
02e93ffec6
spiFlashdb: fix bp_offset list
2022-02-26 17:02:38 +01:00
9cd2555820
scripts/msys2/PKGBUILD: try to fix msys2 build failure
2022-02-26 16:52:10 +01:00
add794ab67
spiFlashdb: add microchip SST26VF032B
2022-02-26 16:31:41 +01:00
aada7fe26b
spiFlash: when no subsector_erase compute end_addr with correct block size
2022-02-26 16:17:49 +01:00
655f2c61ec
spiFlash: add no block protect use case
2022-02-26 16:15:50 +01:00
c737347089
Merge pull request #184 from jeanthom/ci-macos
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Add CI for macOS
2022-02-25 07:02:57 +01:00
129bf6ebe6
.github/workflows/Test.yml: Add CI for macOS
2022-02-24 21:15:20 +01:00
3b3e5efcb2
Merge pull request #183 from jrrk2/darwin_cmake_fix
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Darwin cmake config is missing Security framework
2022-02-24 11:56:04 +01:00
9226077998
Darwin cmake config is missing Security framework
2022-02-24 10:41:04 +00:00
4c3d55d408
Merge pull request #180 from jrrk2/genesys2
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Add board and cable defaults for genesys2
2022-02-22 19:04:24 +01:00
e2fc0a3713
Merge pull request #2 from unbtorsten/genesys2
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add spiOverJtag build process for Kintex7
2022-02-22 17:19:28 +00:00
d54dae0d2a
Merge branch 'jrrk2:genesys2' into genesys2
2022-02-22 13:14:35 -04:00
255d90b750
add spiOverJtag build process for Kintex7 ffg900-2 packages, amend and extend build process for ff676-1 package
2022-02-22 13:01:02 -04:00
25c44e409a
Merge pull request #1 from unbtorsten/genesys2
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Update board.hpp
2022-02-22 09:51:47 +00:00
3cfdfb1856
Update board.hpp
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Use default cable. This is equivalent to 6MHz setting, albeit more versatile.
2022-02-21 23:05:37 -04:00
d4e8eef676
Add board and cable defaults for genesys2
2022-02-21 08:11:57 +00:00
52696309bb
spiFlashdb: spansion S25FL256S
2022-02-21 08:27:33 +01:00
4482deec18
doc/cable: move to yml
2022-02-20 15:47:35 +01:00
7384573992
doc/boards: fix naming format for colorlight-ix boards
2022-02-20 15:11:04 +01:00
2800ebbefb
Merge pull request #179 from splinedrive/master
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add support for colorlight-i9
2022-02-20 15:09:51 +01:00
7a7f1723ea
add support for colorlight-i9
2022-02-20 01:41:17 +01:00
fc4f35fe76
Merge pull request #178 from rwhitby/qmtechKintex7
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Xilinx XC7K325T support
2022-02-19 07:48:00 +01:00
6059c9dbfb
Remove the Tigard default cable, as the board does not have an on-board JTAG adapter.
2022-02-19 17:14:49 +10:30
7022e2101a
Add support for the QMTech Kintex7 Core Board
2022-02-19 14:22:55 +10:30
1cb85a5a21
Add support for the Spansion S25FL256L flash on the QMTech Kintex 7 board
2022-02-19 14:22:26 +10:30
18a24c65ea
Add spiOverJtag support for Xilinx xc7k325tffg676 part.
2022-02-19 13:14:50 +10:30
951c4f0f51
Merge pull request #176 from hansemro/zybo_z7
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Add digilent_zybo_z7 10/20 support
2022-02-16 07:23:03 +01:00
905e96dfec
Add digilent_zybo_z7 10/20 support
2022-02-15 21:01:11 -08:00
5099b57ce3
Merge pull request #174 from tarikgraba/master
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Add support for Terasic DE1-SoC board
2022-02-09 20:14:38 +01:00
94ca103360
doc: add reference to the Terasic DE1-SoC board
2022-02-09 18:40:16 +01:00
89e1fb89d2
doc: add Cyclone V SE SoC FPGA to the supported parts
2022-02-09 18:40:16 +01:00
56457a4023
Merge pull request #173 from rstephan/tables
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Nicer layout for the boards/fpga/cables table
2022-02-09 18:17:35 +01:00
63c9ec01b7
Fixed right alignment problem.
2022-02-09 17:55:16 +01:00
5aa34c6364
board: add Terasic DE1-SoC board
2022-02-09 17:22:38 +01:00
d188314ae3
part: add altera 5CSEMA5 (cyclone V Soc)
2022-02-09 17:21:19 +01:00
Gwenhael Goavec-Merou
Rod Whitby
RGD2
Pepijn de Vos
Jean THOMAS
Jonathan Kimmitt
Torsten Reuschel
unbtorsten
Hirosh Dabui
Hansem Ro
TG
Stephan Ruloff