spiOverJtag: Xilinx Spartan6 LX150T

doc/FPGAs.yml

@@ -192,6 +192,7 @@ Xilinx:
       - xc6slx16
       - xc6slx25
       - xc6slx45
+      - xc6slx150T
     URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html
     Memory: OK
     Flash: OK

spiOverJtag/Makefile

@@ -1,4 +1,5 @@
 XILINX_PARTS := xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
+	xc6slx150tfgg484 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
 	xc7a50tcpg236 xc7a75tfgg484 xc7a100tcsg324 xc7a100tfgg484 xc7a200tsbg484 \
 	xc7s25csga324 xc7s50csga324 \

spiOverJtag/build.py

@@ -54,6 +54,7 @@ if tool in ["ise", "vivado"]:
         "xc6slx16csg324"   : "xc6s_csg324",
         "xc6slx45csg324"   : "xc6s_csg324",
         "xc6slx100fgg484"  : "xc6s_fgg484",
+        "xc6slx150tfgg484" : "xc6s_fgg484",
         "xc7a35tcpg236"    : "xc7a_cpg236",
         "xc7a35tcsg324"    : "xc7a_csg324",
         "xc7a35tftg256"    : "xc7a_ftg256",
@@ -75,12 +76,14 @@ if tool in ["ise", "vivado"]:
                             "xc6slx16ftg256": "xc6slx16",
                             "xc6slx16csg324": "xc6slx16",
                             "xc6slx45csg324": "xc6slx45",
-                            "xc6slx100fgg484": "xc6slx100"}[part],
+                            "xc6slx100fgg484": "xc6slx100",
+                            "xc6slx150tfgg484": "xc6slx150t"}[part],
                         'package': {
                             "xc6slx16ftg256": "ftg256",
                             "xc6slx16csg324": "csg324",
                             "xc6slx45csg324": "csg324",
-                            "xc6slx100fgg484": "fgg384"}[part],
+                            "xc6slx100fgg484": "fgg384",
+                            "xc6slx150tfgg484": "fgg484"}[part],
                         'speed' : -3
                 }
     else:

spiOverJtag/constr_xc6s_fgg484.ucf

@@ -0,0 +1,8 @@
+CONFIG VCCAUX = "2.5";
+
+NET "sdi_dq0"  LOC = AB20 | IOSTANDARD = LVCMOS25;
+NET "sdo_dq1"  LOC = AA20 | IOSTANDARD = LVCMOS25;
+NET "wpn_dq2"  LOC = R13  | IOSTANDARD = LVCMOS25;
+NET "hldn_dq3" LOC = T14  | IOSTANDARD = LVCMOS25;
+NET "csn"      LOC = AA3  | IOSTANDARD = LVCMOS25;
+NET "sck"      LOC = Y20  | IOSTANDARD = LVCMOS25;