doc/cable: move to yml
This commit is contained in:
Gwenhael Goavec-Merou
parent
7384573992
commit
4482deec18
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@ -43,4 +43,5 @@ build/
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/doc/_build/
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/doc/_theme/
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/doc/compatibility/boards.inc
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/doc/compatibility/cable.inc
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/doc/compatibility/fpga.inc
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@ -0,0 +1,199 @@
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anlogicCable:
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- Name: anlogic JTAG adapter
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Description: JTAG adapter firmware for stm32
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URL: https://github.com/AnlogicInfo/anlogic-usbjtag
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arm-usb-ocd-h:
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- Name: Olimex ARM-USB-OCD-H adapter
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Description: High-speed 3-IN-1 fast USB ARM JTAG, USB-to-RS232 virtual port and power supply 5VDC device
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URL: https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/
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bus_blaster:
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- Name: Dangerousprototypes Bus Blaster
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Description: Jtag adapter based on ft2232
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URL: http://dangerousprototypes.com/docs/Bus_Blaster
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bus_blaster_b:
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- Name: Dangerousprototypes Bus Blaster
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Description: Jtag adapter based on ft2232 (interface B)
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URL: http://dangerousprototypes.com/docs/Bus_Blaster
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ch552_jtag:
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- Name: ch552 JTAG adapter
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Description: Tang Nano USB-JTAG interface. FT2232C clone firmware for CH552 microcontroler
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URL: https://github.com/diodep/ch55x_jtag
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cmsisdap:
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- Name: ARM CMSIS DAP protocol interface
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Description: ARM CMSIS DAP protocol interface (hid only)
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URL: https://os.mbed.com/docs/mbed-os/v6.11/debug-test/daplink.html
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gatemate_pgm:
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- Name: gatemate pgm
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Description: Cologne Chip GateMate FPGA Programmer. FT232H-based JTAG/SPI programmer cable
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URL: https://colognechip.com/programmable-logic/gatemate/
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gatemate_evb_jtag:
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- Name: gatemate evb JTAG
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Description: Cologne Chip GateMate JTAG programmer
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URL: https://colognechip.com/programmable-logic/gatemate/
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gatemate_evb_spi:
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- Name: gatemate evb spi
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Description: Cologne Chip GateMate SPI programmer
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URL: https://colognechip.com/programmable-logic/gatemate/
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dfu:
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- Name: DFU interface
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Description: DFU (Device Firmware Upgrade) USB device compatible with DFU protocol
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URL: http://www.usb.org/developers/docs/devclass_docs/DFU_1.1.pdf
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digilent:
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- Name: digilent cable
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Description: FT2232 JTAG / UART cable
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diglent_b:
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- Name: digilent cable
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Description: digilent FT2232 JTAG / UART cable (interface B)
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digilent_hs2:
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- Name: digilent hs2 cable
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Description: FT232H JTAG programmer cable from digilent
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URL: https://store.digilentinc.com/jtag-hs2-programming-cable/
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digilent_hs3:
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- Name: digilent hs3
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Description: JTAG programmer cable from digilent
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URL: https://digilent.com/shop/jtag-hs3-programming-cable/
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dirtyJtag:
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- Name: dirty Jtag
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Description: JTAG probe firmware for STM32F1
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URL: https://github.com/jeanthom/DirtyJTAG
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Note: Best to use release (1.4 or newer) or limit the --freq to 600000 with older releases.
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New version `dirtyjtag2 <https://github.com/jeanthom/DirtyJTAG/tree/dirtyjtag2>`__ is also supported
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efinix_spi_ft4232:
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- Name: efinix SPI (ft4232)
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Description: efinix SPI interface (FTDI4232 interface A)
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efinix_jtag_ft4232:
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- Name: efinix JTAG (ft4232)
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Description: efinix JTAG interface (FTDI4232 interface B)
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efinix_spi_ft2232:
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- Name: efinix SPI (ft2232)
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Description: efinix SPI interface (FTDI2232 interface A)
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ft2232:
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- Name: FT2232 C/D/H
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Description: generic programmer cable based on Ftdi FT2232 (interface A)
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- Name: Tang Nano (1k, 4k, 8k) USB-JTAG interface
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Description: USB-JTAG/UART debugger based on BL702 microcontroler.
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URL: https://github.com/sipeed/RV-Debugger-BL702
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- Name: honeycomb USB-JTAG interface.
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Description: FT2232C clone based on STM32F042 microcontroler
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URL: https://github.com/Disasm/f042-ftdi
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ft2232_b:
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- Name: FT2232 C/D/H
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Description: generic programmer cable based on Ftdi FT2232 (interface B)
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ft231X:
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- Name: FT231X
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Description: generic USB<->UART converters in bitbang mode (with some limitations and workaround)
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URL: https://www.ftdichip.com/old2020/Products/ICs/FT231X.html
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ft232:
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- Name: FT232H
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Description: generic programmer cable based on Ftdi FT232Hx. One interface, MPSSE capable
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URL: https://ftdichip.com/products/ft232hl/
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ft232RL:
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- Name: FT232RL
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Description: generic USB<->UART converters in bitbang mode (with some limitations and workaround)
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URL: https://ftdichip.com/products/ft232rl/
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ft4232:
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- Name: FT4232
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Description: quad interface programmer cable. MPSSE capable.
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URL: https://ftdichip.com/products/ft4232h-56q/
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ecpix5-debug:
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- Name: ecpix5-debug
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Description: LambdaConcept ECPIX5 (45k/85k) UART/JTAG interface
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URL: https://shop.lambdaconcept.com/home/46-ecpix-5.html
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orbtrace:
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- Name: orbtrace interface
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Description: Open source FPGA-based debug and trace interface
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URL: https://github.com/orbcode/orbtrace
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tigard:
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- Name: tigard
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Description: SWD/JTAG/UART/SPI programmer based on Ftdi FT2232HQ
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URL: https://www.crowdsupply.com/securinghw/tigard
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usb-blaster:
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- Name: intel USB Blaster I interface
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Description: JTAG programmer cable from intel/altera (FT245 + EPM7064)
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usb-blasterII:
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- Name: intel USB Blaster II interface
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Description: JTAG programmer cable from intel/altera (EZ-USB FX2 + EPM570)
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URL: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pdf
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@ -3,22 +3,4 @@
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Cables
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######
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* anlogic JTAG adapter
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* `arm-usb-ocd-h <https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/>`__: jtag programmer cable from olimex
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* `digilent_hs2 <https://store.digilentinc.com/jtag-hs2-programming-cable/>`__: jtag programmer cable from digilent
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* `cmsisdap <https://os.mbed.com/docs/mbed-os/v6.11/debug-test/daplink.html>`__: ARM CMSIS DAP protocol interface (hid only)
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* `Orbtrace <https://github.com/orbcode/orbtrace>`__: Open source FPGA-based debug and trace interface
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* `DFU (Device Firmware Upgrade) <http://www.usb.org/developers/docs/devclass_docs/DFU_1.1.pdf>`__: USB device compatible with DFU protocol
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* `DirtyJTAG <https://github.com/jeanthom/DirtyJTAG>`__: JTAG probe firmware for STM32F1
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(Best to use release (1.4 or newer) or limit the --freq to 600000 with older releases.
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New version `dirtyjtag2 <https://github.com/jeanthom/DirtyJTAG/tree/dirtyjtag2>`__ is also supported)
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* Intel USB Blaster I & II : jtag programmer cable from intel/altera
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* JTAG-HS3: jtag programmer cable from digilent
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* FT2232: generic programmer cable based on Ftdi FT2232
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* FT232RL and FT231X: generic USB<->UART converters in bitbang mode
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* `Tang Nano USB-JTAG interface <https://github.com/diodep/ch55x_jtag>`__: FT2232C clone based on CH552 microcontroler
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(with some limitations and workaround)
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* `Tang Nano 4k USB-JTAG interface <https://github.com/sipeed/RV-Debugger-BL702>`__: USB-JTAG/UART debugger based on BL702 microcontroler.
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* `Tigard <https://www.crowdsupply.com/securinghw/tigard>`__: SWD/JTAG/UART/SPI programmer based on Ftdi FT2232HQ
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* `honeycomb USB-JTAG interface <https://github.com/Disasm/f042-ftdi>`__: FT2232C clone based on STM32F042 microcontroler
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* `Cologne Chip GateMate FPGA Programmer <https://colognechip.com/programmable-logic/gatemate/>`__: FT232H-based JTAG/SPI programmer cable
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.. include:: cable.inc
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10
doc/conf.py
10
doc/conf.py
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@ -15,7 +15,9 @@ from data import (
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ReadBoardDataFromYAML,
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BoardDataToTable,
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ReadFPGADataFromYAML,
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FPGADataToTable
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FPGADataToTable,
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ReadCableDataFromYAML,
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CableDataToTable
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)
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# -- General configuration ------------------------------------------------
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@ -34,7 +36,7 @@ source_suffix = {
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master_doc = "index"
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project = u"openFPGALoader: universal utility for programming FPGA"
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copyright = u"2019-2021, Gwenhael Goavec-Merou and contributors"
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copyright = u"2019-2022, Gwenhael Goavec-Merou and contributors"
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author = u"Gwenhael Goavec-Merou and contributors"
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version = "latest"
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@ -121,3 +123,7 @@ with (ROOT / "compatibility/boards.inc").open("w", encoding="utf-8") as wptr:
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with (ROOT / "compatibility/fpga.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(FPGADataToTable(ReadFPGADataFromYAML()))
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# -- Generate partial Cable compatibility page (`cable.inc`) with data from `cable.yml`
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with (ROOT / "compatibility/cable.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(CableDataToTable(ReadCableDataFromYAML()))
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35
doc/data.py
35
doc/data.py
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@ -80,3 +80,38 @@ def FPGADataToTable(data, tablefmt: str = "rst"):
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headers=["Vendor", "Description", "Model", "Memory", "Flash"],
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tablefmt=tablefmt
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)
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@dataclass
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class Cable:
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Name: str
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Description: str
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URL: str = None
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Note: str = None
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def ReadCableDataFromYAML():
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with (ROOT / 'cable.yml').open('r', encoding='utf-8') as fptr:
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data = yaml_load(fptr, yaml_loader)
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for keyword, content in data.items():
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data[keyword] = [Cable(**item) for item in content]
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return data
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def CableDataToTable(data, tablefmt: str = "rst"):
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def processURL(name, url):
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if url is None:
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return f"{name}"
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else:
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return f"`{name} <{url}>`__"
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return tabulate(
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[
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[
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f"{vendor}",
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processURL(item.Name, item.URL),
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item.Description
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] for vendor, content in data.items() for item in content
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],
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headers=["keyword", "Name", "Description"],
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tablefmt=tablefmt
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)
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