Merge pull request #180 from jrrk2/genesys2

Add board and cable defaults for genesys2

doc/boards.yml

@@ -361,6 +361,13 @@
   Memory: OK
   Flash: OK
 
+- ID: genesys2
+  Description: Digilent Kintex7 Evaluation Board
+  URL: https://digilent.com/reference/programmable-logic/genesys-2/start
+  FPGA: Kintex xc7k325tffg900
+  Memory: OK
+  Flash: OK
+
 - ID: runber
   Description: SeeedStudio Gowin RUNBER
   URL: https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html

spiOverJtag/Makefile

@@ -1,7 +1,8 @@
 XILINX_PARTS := xc6slx16ftg256 xc6slx16csg324 xc6slx45csg324 xc6slx100fgg484 \
 	xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 \
 	xc7a50tcpg236 xc7a75tfgg484 xc7a100tcsg324 xc7a100tfgg484 xc7a200tsbg484 \
-	xc7s25csga324 xc7s50csga324
+	xc7s25csga324 xc7s50csga324 \
+	xc7k325tffg676 xc7k325tffg900
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
 ALTERA_PARTS := 10cl025256 ep4ce2217 ep4ce1523 5ce223 5ce423

spiOverJtag/build.py

@@ -35,6 +35,9 @@ elif subpart[0:2] == '5c':
 elif subpart == "xc7a":
     family = "Artix"
     tool = "vivado"
+elif subpart == "xc7k":
+    family = "Kintex 7"
+    tool = "vivado"
 elif subpart == "xc7s":
     family = "Spartan 7"
     tool = "vivado"
@@ -60,6 +63,8 @@ if tool in ["ise", "vivado"]:
         "xc7a100tfgg484"   : "xc7a_fgg484",
         "xc7a200tsbg484"   : "xc7a_sbg484",
         "xc7a200tfbg484"   : "xc7a_fbg484",
+        "xc7k325tffg676"   : "xc7k_ffg676",
+        "xc7k325tffg900"   : "xc7k_ffg900",
         "xc7s25csga324"    : "xc7s_csga324",
         "xc7s50csga324"    : "xc7s_csga324"
         }[part]

spiOverJtag/constr_xc7k_ffg900.xdc

@@ -0,0 +1,10 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVTTL} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
+set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
+set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
+set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
+

spiOverJtag/xilinx_spiOverJtag.tcl

@@ -15,6 +15,7 @@ set grade [dict create \
 	xc7a100tfgg484 -2 \
 	xc7a200tsbg484 -1 \
 	xc7k325tffg676 -1 \
+	xc7k325tffg900 -2 \
 	xc7s50csga324  -1 \
 	]
 
@@ -28,6 +29,7 @@ set pkg_name [dict create \
 	xc7a200tsbg484 xc7a_sbg484 \
 	xc7a200tfbg484 xc7a_fbg484 \
 	xc7k325tffg676 xc7k_ffg676 \
+	xc7k325tffg900 xc7k_ffg900 \
 	xc7s50csga324  xc7s_csga324 \
 	]
 

src/board.hpp

@@ -162,6 +162,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "",  0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("qmtechCycloneV",  "5ce223", "",     0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("qmtechKintex7",   "xc7k325tffg676", "", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("genesys2",        "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("runber",          "", "ft232",      0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("tangnano",        "", "ch552_jtag", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("tangnano1k",      "", "ft2232",     0, 0, CABLE_DEFAULT),