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Merge pull request #176 from hansemro/zybo_z7 

Add digilent_zybo_z7 10/20 support
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Gwenhael Goavec-Merou 2022-02-16 07:23:03 +01:00 committed by GitHub
parent 5099b57ce3 905e96dfec
commit 951c4f0f51
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2 changed files with 16 additions and 0 deletions
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14
doc/boards.yml
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@ -469,3 +469,17 @@
Memory: OK
Flash: NA
Constraints: ZedBoard
- ID: zybo_z7_10
Description: Digilent Zybo Z7-10
URL: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
FPGA: zynq7000 xc7z010clg400
Memory: OK
Flash: NA
- ID: zybo_z7_20
Description: Digilent Zybo Z7-20
URL: https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/start
FPGA: zynq7000 xc7z020clg400
Memory: OK
Flash: NA

2
src/board.hpp
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@ -118,6 +118,8 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),