Add board and cable defaults for genesys2

doc/boards.yml

@@ -361,6 +361,13 @@
   Memory: OK
   Flash: OK
 
+- ID: genesys2
+  Description: Digilent Kintex7 Evaluation Board
+  URL: https://digilent.com/reference/programmable-logic/genesys-2/start
+  FPGA: Kintex xc7k325tffg900
+  Memory: OK
+  Flash: OK
+
 - ID: runber
   Description: SeeedStudio Gowin RUNBER
   URL: https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html

src/board.hpp

@@ -162,6 +162,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "",  0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("qmtechCycloneV",  "5ce223", "",     0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("qmtechKintex7",   "xc7k325tffg676", "", 0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("genesys2",        "xc7k325tffg900", "digilent_b", 0, 0, CABLE_MHZ(6)),
 	JTAG_BOARD("runber",          "", "ft232",      0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("tangnano",        "", "ch552_jtag", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("tangnano1k",      "", "ft2232",     0, 0, CABLE_DEFAULT),