Merge pull request #174 from tarikgraba/master

Add support  for Terasic DE1-SoC board

doc/FPGAs.yml

@@ -81,6 +81,15 @@ Intel:
     Memory: OK
     Flash: OK
 
+  - Description: Cyclone V SE SoC
+    Model:
+      - 5CSEBA6
+      - 5CSEMA4
+      - 5CSEMA5
+    URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
+    Memory: OK
+    Flash: NT
+
   - Description: Cyclone 10 LP
     Model: 10CL025
     URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html

doc/boards.yml

@@ -170,6 +170,12 @@
   FPGA: Cyclone V SoC 5CSEBA6U23I7
   Memory: OK
 
+- ID: de1Soc
+  Description: Terasic DE1-SoC
+  URL: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836
+  FPGA: Cyclone V SoC 5CSEMA5F31C6
+  Memory: OK
+
 - ID: ecp5_evn
   Description: Lattice ECP5 5G Evaluation Board
   URL: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard

src/board.hpp

@@ -126,6 +126,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("de0nano",         "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de0nanoSoc",      "", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("de10nano",        "", "usb-blasterII",0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("de1Soc",          "5CSEMA5", "usb-blasterII",0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("ecp5_evn",        "", "ft2232",     0, 0, CABLE_DEFAULT),
 	SPI_BOARD("fireant",              "efinix", "ft232",
 			DBUS4, DBUS5, 0, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),

src/part.hpp

@@ -71,6 +71,7 @@ static std::map <int, fpga_model> fpga_list = {
 	{0x02b050dd, {"altera", "cyclone V", "5CEBA4", 10}},
 	{0x02d020dd, {"altera", "cyclone V Soc", "5CSEBA6", 10}},
 	{0x02d010dd, {"altera", "cyclone V Soc", "5CSEMA4", 10}},
+	{0x02d120dd, {"altera", "cyclone V Soc", "5CSEMA5", 10}},
 
 	{0x00000001, {"efinix", "Trion",    "T4/T8",            4}},
 	{0x00210a79, {"efinix", "Trion",    "T8QFP144/T13/T20", 4}},