board: Xilinx ZC706

doc/boards.yml

@@ -491,6 +491,14 @@
   Memory: OK
   Flash: NA
 
+- ID: zc706
+  Description: Xilinx ZC706
+  URL: https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html
+  FPGA: zynq7000 xc7z045ffg900
+  Memory: OK
+  Flash: NA
+  Constraints: ZC706
+
 - ID: zedboard
   Description: Avnet ZedBoard
   URL: https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/

src/board.hpp

@@ -186,6 +186,7 @@ static std::map <std::string, target_board_t> board_list = {
 	SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232",
 			DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
 	JTAG_BOARD("titanium_ti60_f225_jtag", "","efinix_jtag_ft4232",  0, 0, CABLE_DEFAULT),
+	JTAG_BOARD("zc706",           "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("zedboard",        "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
 };