Fischer Moseley
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daedb91ff2
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b1caec9c57
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meta: switch from black to ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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ecfbdaa86b
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cli: remove JSON loader, add test for instantiation generation
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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fa80a49145
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deps: load liteeth from PyPI
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b31a655d58
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tests: include building examples in test suite
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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6eae490061
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formatting
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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8f45546b5a
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manta: fix code generation from config file, update tests
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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3ba93efd2f
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meta: expose Amaranth API via __all__
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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0d15abe4d1
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ethernet: update __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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0bdfd9a5f7
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tests: fix mem_core_hw
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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165c6e46ca
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tests: fix logic_analyzer_sim
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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55884a11df
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ci: check formatting with black
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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a01b6981e2
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tests: refactor to use Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b20d7c7822
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logic analyzer: move __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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743f434652
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meta: add boilerplate for Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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d582dc24c8
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uart: update length checking to accomodate extra newlines
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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ed2dfd141b
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add newline every 32 read requests
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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080af6c5ee
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logic_analyzer: find nearest integer timestep in VCD export
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2024-10-07 13:39:39 -06:00 |
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Fischer Moseley
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49e8d340ba
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logic_analyzer: obtain clock frequency in capture_vcd from self
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2024-10-07 13:39:39 -06:00 |
Carlos Azevedo
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ebcb11fdba
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VCD time step is calculated from the frequency of the clock provided to Manta. The value changes are also timed accurately, instead of expressed in 10 ns intervals always.
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2024-10-07 13:39:39 -06:00 |
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Fischer Moseley
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929312181e
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ci: clone entire repo when building docs
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2024-10-06 13:11:32 -06:00 |
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Fischer Moseley
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b998d21810
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ci: do not cache clone between builds
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2024-10-06 13:05:22 -06:00 |
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Fischer Moseley
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6f2a0eab15
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ci: add GitHub Actions user to fix mike deploy
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2024-10-06 13:03:30 -06:00 |
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Fischer Moseley
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ead8a7b5bf
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docs: push to dev instead of latest from main
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2024-10-06 11:42:57 -06:00 |
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Fischer Moseley
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c5bc148a57
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docs: fix old version warning
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2024-10-06 11:34:31 -06:00 |
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Fischer Moseley
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4e93a049cd
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docs: deploy using mike in CI
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2024-10-06 11:25:14 -06:00 |
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Fischer Moseley
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1f8bf643fd
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docs: add mike
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2024-10-06 10:52:23 -06:00 |
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Fischer Moseley
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19342c4735
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ci: add codecov.yml
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2024-09-10 17:33:55 -06:00 |
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Fischer Moseley
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236305729e
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ci: invoke codecov via Python, not from command line
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2024-09-10 15:21:41 -06:00 |
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Fischer Moseley
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3fb5bfb4ad
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ci: run codecov directly instead of via GitHub Action
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2024-09-10 13:45:40 -06:00 |
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Fischer Moseley
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354309394d
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meta: export JSON during tests for codecov to injest
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2024-09-10 10:09:56 -06:00 |
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Fischer Moseley
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129f991dda
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meta: add codecov
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2024-09-10 07:17:50 -06:00 |
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Fischer Moseley
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0715788ed7
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meta: update description in pyproject.toml
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2024-07-18 06:35:37 -07:00 |
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Fischer Moseley
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fd65d9a009
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meta: increment version to 1.0.1
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2024-07-18 06:34:34 -07:00 |
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Fischer Moseley
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24b4ca2468
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docs: add mention of CSV export from logic analyzer
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2024-07-17 19:47:18 -07:00 |
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Fischer Moseley
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f687f071dd
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cli: enable CSV export from logic analyzer capture
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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67103ad70e
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doc: remove warning about bidirectional mem cores on xilinx platforms
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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b87f8cbc48
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meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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753a3f9427
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meta: finish moving simulations to new async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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8fd943257c
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sim: update testbenches to async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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978937e4bc
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modify example design naming convention
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2024-05-12 10:25:00 -07:00 |
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Fischer Moseley
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6c25f6e8d3
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add sponsor button
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2024-05-11 11:52:35 -06:00 |
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Fischer Moseley
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7957e5d74e
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doc: change WaveDrom render branch to main
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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f6127791c7
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doc: add inline CSS to fix WaveDrom renders in dark mode
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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b35bfa1152
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doc: fix typo and migrate read timing diagram
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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697d6a00d9
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doc: directly render read transaction timing diagram
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2024-04-14 16:11:46 -06:00 |
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Fischer Moseley
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8da5b27010
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Merge pull request #17 from KennethWilke/main
add warning about reset polarity in Manta instance
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2024-04-06 00:50:19 -06:00 |
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Fischer Moseley
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7a44f34ae3
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tweak wording of active low reset warning
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2024-04-05 23:46:54 -07:00 |
Kenneth Wilke
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af0dec7d76
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Updated reset note and a doc link
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2024-04-05 19:03:01 -05:00 |