Fischer Moseley
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adf355c633
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make examples build
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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f5caca613a
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simplify uart/ether APIs, improve lazy loading
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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ab58af0bfc
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add video_sprite_ether example
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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54b97fd120
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add working ethernet verilog autogeneration woot woot :)
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7f9012b542
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tidy examples
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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7cd8a2cfa5
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tidy up mac stack
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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6210e3cc39
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add working python api for ethernet tx/rx
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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8e139bba3a
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add working l2 mac in hardware - need to fix ethertype to get scapy to play nice
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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0bb3f9c74a
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clean up mac_tx, working in simulation
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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64a582c786
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add working mac tx
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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dab6e3f272
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add working mac testbench - also found a problem in VCD logging
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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28f40f2b7b
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add working l2 send in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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870d299c74
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add docs and add trigger config for logic analyzer
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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102bdee410
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update makefile to match positional args from PATH'd binaries
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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f6f9096895
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add batch read/write UART for speedo mode
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9cc2357ea4
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update command line positional args
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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7c1e4fc2c0
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add logic analyzer playback module auto-generation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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9d8836bda3
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add prototype simulation replay
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1c74d4a714
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add running the logic analyzer to the python API
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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d8eeb65b8f
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fix pipelining in video_sprite exmaple
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2023-04-13 18:00:22 -04:00 |
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Fischer Moseley
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153ae7e3df
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video sprite example working! kinda frankensteined tho
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2023-04-13 17:02:55 -04:00 |
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Fischer Moseley
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d3213c6369
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update docs site outline
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2023-04-12 20:55:09 -04:00 |
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Fischer Moseley
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c1dcc7faa6
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slim down video_sprite example, ready for manta brams
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2023-04-12 20:37:43 -04:00 |
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Fischer Moseley
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4ece833ea1
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add video sprite example
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2023-04-12 20:03:22 -04:00 |
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Fischer Moseley
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db76ce3579
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reasonably tidy BRAM core - might be dependent on icarus 13
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2023-04-10 17:51:43 -04:00 |
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Fischer Moseley
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4837b2787a
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add (half) working BRAM core example
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2023-04-10 17:02:48 -04:00 |
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Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |
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Fischer Moseley
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1710da6f87
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update makefile to represent new functional sim locations
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2023-04-09 22:33:58 -04:00 |
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Fischer Moseley
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3c06b74c7a
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add working io_core over ethernet (rx)
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2023-04-09 15:03:54 -04:00 |
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Fischer Moseley
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ab8582a570
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move building examples into makefile, add working logic analyzer test
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2023-04-03 23:47:36 -04:00 |
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Fischer Moseley
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c604614428
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autogenerate logic_analyzer and sample_mem
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2023-04-03 23:15:09 -04:00 |
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Fischer Moseley
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c5ceccc980
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add icestick lut_ram example
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2023-04-03 21:30:59 -04:00 |
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Fischer Moseley
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aec2850280
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update examples directory structure with thoughts from bikeride
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2023-04-03 21:29:28 -04:00 |
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Fischer Moseley
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ce41d7ec41
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clean up inferred BRAM, trim whitespace
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2023-04-03 21:20:36 -04:00 |
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Fischer Moseley
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8f08dffc70
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consolidate logic analyzer testbench
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2023-04-03 12:20:24 -04:00 |
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Fischer Moseley
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1b27a6f948
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add working icestick io core example
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2023-04-02 23:16:25 -04:00 |
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Fischer Moseley
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f682e5386f
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add working hand-parameterized logic analyzer! still buggy but this is super neato 🤠
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2023-04-02 22:49:48 -04:00 |
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Fischer Moseley
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18fcbfe1f2
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add IO core example
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2023-03-23 23:15:55 -04:00 |
Fischer Moseley
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a562c8136c
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add ability to autodetect serial port
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2023-03-23 20:46:49 -04:00 |
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Fischer Moseley
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f7077f96d8
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add lut ram operations to Python API
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2023-03-23 19:38:19 -04:00 |
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Fischer Moseley
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c85cc4d357
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tweak lut_ram example
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2023-03-23 18:24:29 -04:00 |
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Fischer Moseley
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edd50168e2
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refactor IO core read/write to be less ugly
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2023-03-17 20:12:57 -04:00 |
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Fischer Moseley
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d46e833529
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can now successfully autogenerate and build io cores
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2023-03-16 12:13:46 -04:00 |
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Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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4540aebf6d
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add some fixes for macos serial prots
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2023-03-14 16:24:56 -04:00 |